Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/rt2860reg.h
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* $OpenBSD: rt2860reg.h,v 1.35 2018/10/02 02:05:34 kevlo Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 /* PCI registers */ 21 #define RT2860_PCI_CFG 0x0000 22 #define RT2860_PCI_EECTRL 0x0004 23 #define RT2860_PCI_MCUCTRL 0x0008 24 #define RT2860_PCI_SYSCTRL 0x000c 25 #define RT2860_PCIE_JTAG 0x0010 26 27 /* RT3290 registers */ 28 #define RT3290_CMB_CTRL 0x0020 29 #define RT3290_EFUSE_CTRL 0x0024 30 #define RT3290_EFUSE_DATA3 0x0028 31 #define RT3290_EFUSE_DATA2 0x002c 32 #define RT3290_EFUSE_DATA1 0x0030 33 #define RT3290_EFUSE_DATA0 0x0034 34 #define RT3290_OSC_CTRL 0x0038 35 #define RT3290_COEX_CFG0 0x0040 36 #define RT3290_PLL_CTRL 0x0050 37 #define RT3290_WLAN_CTRL 0x0080 38 39 #define RT3090_AUX_CTRL 0x010c 40 41 #define RT3070_OPT_14 0x0114 42 43 /* SCH/DMA registers */ 44 #define RT2860_INT_STATUS 0x0200 45 #define RT2860_INT_MASK 0x0204 46 #define RT2860_WPDMA_GLO_CFG 0x0208 47 #define RT2860_WPDMA_RST_IDX 0x020c 48 #define RT2860_DELAY_INT_CFG 0x0210 49 #define RT2860_WMM_AIFSN_CFG 0x0214 50 #define RT2860_WMM_CWMIN_CFG 0x0218 51 #define RT2860_WMM_CWMAX_CFG 0x021c 52 #define RT2860_WMM_TXOP0_CFG 0x0220 53 #define RT2860_WMM_TXOP1_CFG 0x0224 54 #define RT2860_GPIO_CTRL 0x0228 55 #define RT2860_MCU_CMD_REG 0x022c 56 #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) 57 #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) 58 #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) 59 #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) 60 #define RT2860_RX_BASE_PTR 0x0290 61 #define RT2860_RX_MAX_CNT 0x0294 62 #define RT2860_RX_CALC_IDX 0x0298 63 #define RT2860_FS_DRX_IDX 0x029c 64 #define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ 65 #define RT2860_US_CYC_CNT 0x02a4 66 67 /* PBF registers */ 68 #define RT2860_SYS_CTRL 0x0400 69 #define RT2860_HOST_CMD 0x0404 70 #define RT2860_PBF_CFG 0x0408 71 #define RT2860_MAX_PCNT 0x040c 72 #define RT2860_BUF_CTRL 0x0410 73 #define RT2860_MCU_INT_STA 0x0414 74 #define RT2860_MCU_INT_ENA 0x0418 75 #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) 76 #define RT2860_RX0Q_IO 0x0424 77 #define RT2860_BCN_OFFSET0 0x042c 78 #define RT2860_BCN_OFFSET1 0x0430 79 #define RT2860_TXRXQ_STA 0x0434 80 #define RT2860_TXRXQ_PCNT 0x0438 81 #define RT2860_PBF_DBG 0x043c 82 #define RT2860_CAP_CTRL 0x0440 83 84 /* RT3070 registers */ 85 #define RT3070_RF_CSR_CFG 0x0500 86 #define RT3070_EFUSE_CTRL 0x0580 87 #define RT3070_EFUSE_DATA0 0x0590 88 #define RT3070_EFUSE_DATA1 0x0594 89 #define RT3070_EFUSE_DATA2 0x0598 90 #define RT3070_EFUSE_DATA3 0x059c 91 #define RT3090_OSC_CTRL 0x05a4 92 #define RT3070_LDO_CFG0 0x05d4 93 #define RT3070_GPIO_SWITCH 0x05dc 94 95 /* RT5592 registers */ 96 #define RT5592_DEBUG_INDEX 0x05e8 97 98 /* MAC registers */ 99 #define RT2860_ASIC_VER_ID 0x1000 100 #define RT2860_MAC_SYS_CTRL 0x1004 101 #define RT2860_MAC_ADDR_DW0 0x1008 102 #define RT2860_MAC_ADDR_DW1 0x100c 103 #define RT2860_MAC_BSSID_DW0 0x1010 104 #define RT2860_MAC_BSSID_DW1 0x1014 105 #define RT2860_MAX_LEN_CFG 0x1018 106 #define RT2860_BBP_CSR_CFG 0x101c 107 #define RT2860_RF_CSR_CFG0 0x1020 108 #define RT2860_RF_CSR_CFG1 0x1024 109 #define RT2860_RF_CSR_CFG2 0x1028 110 #define RT2860_LED_CFG 0x102c 111 112 /* undocumented registers */ 113 #define RT2860_DEBUG 0x10f4 114 115 /* MAC Timing control registers */ 116 #define RT2860_XIFS_TIME_CFG 0x1100 117 #define RT2860_BKOFF_SLOT_CFG 0x1104 118 #define RT2860_NAV_TIME_CFG 0x1108 119 #define RT2860_CH_TIME_CFG 0x110c 120 #define RT2860_PBF_LIFE_TIMER 0x1110 121 #define RT2860_BCN_TIME_CFG 0x1114 122 #define RT2860_TBTT_SYNC_CFG 0x1118 123 #define RT2860_TSF_TIMER_DW0 0x111c 124 #define RT2860_TSF_TIMER_DW1 0x1120 125 #define RT2860_TBTT_TIMER 0x1124 126 #define RT2860_INT_TIMER_CFG 0x1128 127 #define RT2860_INT_TIMER_EN 0x112c 128 #define RT2860_CH_IDLE_TIME 0x1130 129 130 /* MAC Power Save configuration registers */ 131 #define RT2860_MAC_STATUS_REG 0x1200 132 #define RT2860_PWR_PIN_CFG 0x1204 133 #define RT2860_AUTO_WAKEUP_CFG 0x1208 134 135 /* MAC TX configuration registers */ 136 #define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) 137 #define RT2860_EDCA_TID_AC_MAP 0x1310 138 #define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) 139 #define RT2860_TX_PIN_CFG 0x1328 140 #define RT2860_TX_BAND_CFG 0x132c 141 #define RT2860_TX_SW_CFG0 0x1330 142 #define RT2860_TX_SW_CFG1 0x1334 143 #define RT2860_TX_SW_CFG2 0x1338 144 #define RT2860_TXOP_THRES_CFG 0x133c 145 #define RT2860_TXOP_CTRL_CFG 0x1340 146 #define RT2860_TX_RTS_CFG 0x1344 147 #define RT2860_TX_TIMEOUT_CFG 0x1348 148 #define RT2860_TX_RTY_CFG 0x134c 149 #define RT2860_TX_LINK_CFG 0x1350 150 #define RT2860_HT_FBK_CFG0 0x1354 151 #define RT2860_HT_FBK_CFG1 0x1358 152 #define RT2860_LG_FBK_CFG0 0x135c 153 #define RT2860_LG_FBK_CFG1 0x1360 154 #define RT2860_CCK_PROT_CFG 0x1364 155 #define RT2860_OFDM_PROT_CFG 0x1368 156 #define RT2860_MM20_PROT_CFG 0x136c 157 #define RT2860_MM40_PROT_CFG 0x1370 158 #define RT2860_GF20_PROT_CFG 0x1374 159 #define RT2860_GF40_PROT_CFG 0x1378 160 #define RT2860_EXP_CTS_TIME 0x137c 161 #define RT2860_EXP_ACK_TIME 0x1380 162 163 /* MAC RX configuration registers */ 164 #define RT2860_RX_FILTR_CFG 0x1400 165 #define RT2860_AUTO_RSP_CFG 0x1404 166 #define RT2860_LEGACY_BASIC_RATE 0x1408 167 #define RT2860_HT_BASIC_RATE 0x140c 168 #define RT2860_HT_CTRL_CFG 0x1410 169 #define RT2860_SIFS_COST_CFG 0x1414 170 #define RT2860_RX_PARSER_CFG 0x1418 171 172 /* MAC Security configuration registers */ 173 #define RT2860_TX_SEC_CNT0 0x1500 174 #define RT2860_RX_SEC_CNT0 0x1504 175 #define RT2860_CCMP_FC_MUTE 0x1508 176 177 /* MAC HCCA/PSMP configuration registers */ 178 #define RT2860_TXOP_HLDR_ADDR0 0x1600 179 #define RT2860_TXOP_HLDR_ADDR1 0x1604 180 #define RT2860_TXOP_HLDR_ET 0x1608 181 #define RT2860_QOS_CFPOLL_RA_DW0 0x160c 182 #define RT2860_QOS_CFPOLL_A1_DW1 0x1610 183 #define RT2860_QOS_CFPOLL_QC 0x1614 184 185 /* MAC Statistics Counters */ 186 #define RT2860_RX_STA_CNT0 0x1700 187 #define RT2860_RX_STA_CNT1 0x1704 188 #define RT2860_RX_STA_CNT2 0x1708 189 #define RT2860_TX_STA_CNT0 0x170c 190 #define RT2860_TX_STA_CNT1 0x1710 191 #define RT2860_TX_STA_CNT2 0x1714 192 #define RT2860_TX_STAT_FIFO 0x1718 193 194 /* RX WCID search table */ 195 #define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) 196 197 #define RT2860_FW_BASE 0x2000 198 #define RT2870_FW_BASE 0x3000 199 200 /* Pair-wise key table */ 201 #define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) 202 203 /* IV/EIV table */ 204 #define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) 205 206 /* WCID attribute table */ 207 #define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) 208 209 /* Shared Key Table */ 210 #define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) 211 212 /* Shared Key Mode */ 213 #define RT2860_SKEY_MODE_0_7 0x7000 214 #define RT2860_SKEY_MODE_8_15 0x7004 215 #define RT2860_SKEY_MODE_16_23 0x7008 216 #define RT2860_SKEY_MODE_24_31 0x700c 217 218 /* Shared Memory between MCU and host */ 219 #define RT2860_H2M_MAILBOX 0x7010 220 #define RT2860_H2M_MAILBOX_CID 0x7014 221 #define RT2860_H2M_MAILBOX_STATUS 0x701c 222 #define RT2860_H2M_INTSRC 0x7024 223 #define RT2860_H2M_BBPAGENT 0x7028 224 #define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) 225 226 227 /* possible flags for RT2860_PCI_CFG */ 228 #define RT2860_PCI_CFG_USB (1 << 17) 229 #define RT2860_PCI_CFG_PCI (1 << 16) 230 231 /* possible flags for register RT2860_PCI_EECTRL */ 232 #define RT2860_C (1 << 0) 233 #define RT2860_S (1 << 1) 234 #define RT2860_D (1 << 2) 235 #define RT2860_SHIFT_D 2 236 #define RT2860_Q (1 << 3) 237 #define RT2860_SHIFT_Q 3 238 239 /* possible flags for register RT3290_CMB_CTRL */ 240 #define RT3290_XTAL_RDY (1U << 22) 241 #define RT3290_PLL_LD (1U << 23) 242 #define RT3290_LDO_CORE_LEVEL (0xf << 24) 243 #define RT3290_LDO_BGSEL (3 << 29) 244 #define RT3290_LDO3_EN (1U << 30) 245 #define RT3290_LDO0_EN (1U << 31) 246 247 /* possible flags for register RT3290_OSC_CTRL */ 248 #define RT3290_OSC_REF_CYCLE 0x1fff 249 #define RT3290_OSC_CAL_CNT (0xfff << 16) 250 #define RT3290_OSC_CAL_ACK (1U << 28) 251 #define RT3290_OSC_CLK_32K_VLD (1U << 29) 252 #define RT3290_OSC_CAL_REQ (1U << 30) 253 #define RT3290_ROSC_EN (1U << 31) 254 255 /* possible flags for register RT3290_COEX_CFG0 */ 256 #define RT3290_CFG0_DEF (0x59 << 24) 257 258 /* possible flags for register RT3290_PLL_CTRL */ 259 #define RT3290_PLL_CONTROL (7 << 16) 260 261 /* possible flags for register RT3290_WLAN_CTRL */ 262 #define RT3290_WLAN_EN (1U << 0) 263 #define RT3290_WLAN_CLK_EN (1U << 1) 264 #define RT3290_WLAN_RSV1 (1U << 2) 265 #define RT3290_WLAN_RESET (1U << 3) 266 #define RT3290_PCIE_APP0_CLK_REQ (1U << 4) 267 #define RT3290_FRC_WL_ANT_SET (1U << 5) 268 #define RT3290_INV_TR_SW0 (1U << 6) 269 #define RT3290_RADIO_EN (1U << 8) 270 #define RT3290_GPIO_IN_ALL (0xff << 8) 271 #define RT3290_GPIO_OUT_ALL (0xff << 16) 272 #define RT3290_GPIO_OUT_OE_ALL (0xff << 24) 273 274 /* possible flags for registers INT_STATUS/INT_MASK */ 275 #define RT2860_TX_COHERENT (1 << 17) 276 #define RT2860_RX_COHERENT (1 << 16) 277 #define RT2860_MAC_INT_4 (1 << 15) 278 #define RT2860_MAC_INT_3 (1 << 14) 279 #define RT2860_MAC_INT_2 (1 << 13) 280 #define RT2860_MAC_INT_1 (1 << 12) 281 #define RT2860_MAC_INT_0 (1 << 11) 282 #define RT2860_TX_RX_COHERENT (1 << 10) 283 #define RT2860_MCU_CMD_INT (1 << 9) 284 #define RT2860_TX_DONE_INT5 (1 << 8) 285 #define RT2860_TX_DONE_INT4 (1 << 7) 286 #define RT2860_TX_DONE_INT3 (1 << 6) 287 #define RT2860_TX_DONE_INT2 (1 << 5) 288 #define RT2860_TX_DONE_INT1 (1 << 4) 289 #define RT2860_TX_DONE_INT0 (1 << 3) 290 #define RT2860_RX_DONE_INT (1 << 2) 291 #define RT2860_TX_DLY_INT (1 << 1) 292 #define RT2860_RX_DLY_INT (1 << 0) 293 294 /* possible flags for register WPDMA_GLO_CFG */ 295 #define RT2860_HDR_SEG_LEN_SHIFT 8 296 #define RT2860_BIG_ENDIAN (1 << 7) 297 #define RT2860_TX_WB_DDONE (1 << 6) 298 #define RT2860_WPDMA_BT_SIZE_SHIFT 4 299 #define RT2860_WPDMA_BT_SIZE16 0 300 #define RT2860_WPDMA_BT_SIZE32 1 301 #define RT2860_WPDMA_BT_SIZE64 2 302 #define RT2860_WPDMA_BT_SIZE128 3 303 #define RT2860_RX_DMA_BUSY (1 << 3) 304 #define RT2860_RX_DMA_EN (1 << 2) 305 #define RT2860_TX_DMA_BUSY (1 << 1) 306 #define RT2860_TX_DMA_EN (1 << 0) 307 308 /* possible flags for register DELAY_INT_CFG */ 309 #define RT2860_TXDLY_INT_EN (1U << 31) 310 #define RT2860_TXMAX_PINT_SHIFT 24 311 #define RT2860_TXMAX_PTIME_SHIFT 16 312 #define RT2860_RXDLY_INT_EN (1U << 15) 313 #define RT2860_RXMAX_PINT_SHIFT 8 314 #define RT2860_RXMAX_PTIME_SHIFT 0 315 316 /* possible flags for register GPIO_CTRL */ 317 #define RT2860_GPIO_D_SHIFT 8 318 #define RT2860_GPIO_O_SHIFT 0 319 320 /* possible flags for register USB_DMA_CFG */ 321 #define RT2860_USB_TX_BUSY (1U << 31) 322 #define RT2860_USB_RX_BUSY (1U << 30) 323 #define RT2860_USB_EPOUT_VLD_SHIFT 24 324 #define RT2860_USB_TX_EN (1U << 23) 325 #define RT2860_USB_RX_EN (1U << 22) 326 #define RT2860_USB_RX_AGG_EN (1U << 21) 327 #define RT2860_USB_TXOP_HALT (1U << 20) 328 #define RT2860_USB_TX_CLEAR (1U << 19) 329 #define RT2860_USB_PHY_WD_EN (1U << 16) 330 #define RT2860_USB_PHY_MAN_RST (1U << 15) 331 #define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ 332 #define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ 333 334 /* possible flags for register US_CYC_CNT */ 335 #define RT2860_TEST_EN (1 << 24) 336 #define RT2860_TEST_SEL_SHIFT 16 337 #define RT2860_BT_MODE_EN (1 << 8) 338 #define RT2860_US_CYC_CNT_SHIFT 0 339 340 /* possible flags for register SYS_CTRL */ 341 #define RT2860_HST_PM_SEL (1 << 16) 342 #define RT2860_CAP_MODE (1 << 14) 343 #define RT2860_PME_OEN (1 << 13) 344 #define RT2860_CLKSELECT (1 << 12) 345 #define RT2860_PBF_CLK_EN (1 << 11) 346 #define RT2860_MAC_CLK_EN (1 << 10) 347 #define RT2860_DMA_CLK_EN (1 << 9) 348 #define RT2860_MCU_READY (1 << 7) 349 #define RT2860_ASY_RESET (1 << 4) 350 #define RT2860_PBF_RESET (1 << 3) 351 #define RT2860_MAC_RESET (1 << 2) 352 #define RT2860_DMA_RESET (1 << 1) 353 #define RT2860_MCU_RESET (1 << 0) 354 355 /* possible values for register HOST_CMD */ 356 #define RT2860_MCU_CMD_SLEEP 0x30 357 #define RT2860_MCU_CMD_WAKEUP 0x31 358 #define RT2860_MCU_CMD_LEDS 0x50 359 #define RT2860_MCU_CMD_LED_RSSI 0x51 360 #define RT2860_MCU_CMD_LED1 0x52 361 #define RT2860_MCU_CMD_LED2 0x53 362 #define RT2860_MCU_CMD_LED3 0x54 363 #define RT2860_MCU_CMD_RFRESET 0x72 364 #define RT2860_MCU_CMD_ANTSEL 0x73 365 #define RT2860_MCU_CMD_BBP 0x80 366 #define RT2860_MCU_CMD_PSLEVEL 0x83 367 368 /* possible flags for register PBF_CFG */ 369 #define RT2860_TX1Q_NUM_SHIFT 21 370 #define RT2860_TX2Q_NUM_SHIFT 16 371 #define RT2860_NULL0_MODE (1 << 15) 372 #define RT2860_NULL1_MODE (1 << 14) 373 #define RT2860_RX_DROP_MODE (1 << 13) 374 #define RT2860_TX0Q_MANUAL (1 << 12) 375 #define RT2860_TX1Q_MANUAL (1 << 11) 376 #define RT2860_TX2Q_MANUAL (1 << 10) 377 #define RT2860_RX0Q_MANUAL (1 << 9) 378 #define RT2860_HCCA_EN (1 << 8) 379 #define RT2860_TX0Q_EN (1 << 4) 380 #define RT2860_TX1Q_EN (1 << 3) 381 #define RT2860_TX2Q_EN (1 << 2) 382 #define RT2860_RX0Q_EN (1 << 1) 383 384 /* possible flags for register BUF_CTRL */ 385 #define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid))) 386 #define RT2860_NULL0_KICK (1 << 7) 387 #define RT2860_NULL1_KICK (1 << 6) 388 #define RT2860_BUF_RESET (1 << 5) 389 #define RT2860_READ_TXQ(qid) (1 << (3 - (qid)) 390 #define RT2860_READ_RX0Q (1 << 0) 391 392 /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ 393 #define RT2860_MCU_MAC_INT_8 (1 << 24) 394 #define RT2860_MCU_MAC_INT_7 (1 << 23) 395 #define RT2860_MCU_MAC_INT_6 (1 << 22) 396 #define RT2860_MCU_MAC_INT_4 (1 << 20) 397 #define RT2860_MCU_MAC_INT_3 (1 << 19) 398 #define RT2860_MCU_MAC_INT_2 (1 << 18) 399 #define RT2860_MCU_MAC_INT_1 (1 << 17) 400 #define RT2860_MCU_MAC_INT_0 (1 << 16) 401 #define RT2860_DTX0_INT (1 << 11) 402 #define RT2860_DTX1_INT (1 << 10) 403 #define RT2860_DTX2_INT (1 << 9) 404 #define RT2860_DRX0_INT (1 << 8) 405 #define RT2860_HCMD_INT (1 << 7) 406 #define RT2860_N0TX_INT (1 << 6) 407 #define RT2860_N1TX_INT (1 << 5) 408 #define RT2860_BCNTX_INT (1 << 4) 409 #define RT2860_MTX0_INT (1 << 3) 410 #define RT2860_MTX1_INT (1 << 2) 411 #define RT2860_MTX2_INT (1 << 1) 412 #define RT2860_MRX0_INT (1 << 0) 413 414 /* possible flags for register TXRXQ_PCNT */ 415 #define RT2860_RX0Q_PCNT_MASK 0xff000000 416 #define RT2860_TX2Q_PCNT_MASK 0x00ff0000 417 #define RT2860_TX1Q_PCNT_MASK 0x0000ff00 418 #define RT2860_TX0Q_PCNT_MASK 0x000000ff 419 420 /* possible flags for register CAP_CTRL */ 421 #define RT2860_CAP_ADC_FEQ (1U << 31) 422 #define RT2860_CAP_START (1U << 30) 423 #define RT2860_MAN_TRIG (1U << 29) 424 #define RT2860_TRIG_OFFSET_SHIFT 16 425 #define RT2860_START_ADDR_SHIFT 0 426 427 /* possible flags for register RF_CSR_CFG */ 428 #define RT3070_RF_KICK (1 << 17) 429 #define RT3070_RF_WRITE (1 << 16) 430 431 /* possible flags for register EFUSE_CTRL */ 432 #define RT3070_SEL_EFUSE (1U << 31) 433 #define RT3070_EFSROM_KICK (1U << 30) 434 #define RT3070_EFSROM_AIN_MASK 0x03ff0000 435 #define RT3070_EFSROM_AIN_SHIFT 16 436 #define RT3070_EFSROM_MODE_MASK 0x000000c0 437 #define RT3070_EFUSE_AOUT_MASK 0x0000003f 438 439 /* possible flag for register DEBUG_INDEX */ 440 #define RT5592_SEL_XTAL (1U << 31) 441 442 /* possible flags for register MAC_SYS_CTRL */ 443 #define RT2860_RX_TS_EN (1 << 7) 444 #define RT2860_WLAN_HALT_EN (1 << 6) 445 #define RT2860_PBF_LOOP_EN (1 << 5) 446 #define RT2860_CONT_TX_TEST (1 << 4) 447 #define RT2860_MAC_RX_EN (1 << 3) 448 #define RT2860_MAC_TX_EN (1 << 2) 449 #define RT2860_BBP_HRST (1 << 1) 450 #define RT2860_MAC_SRST (1 << 0) 451 452 /* possible flags for register MAC_BSSID_DW1 */ 453 #define RT2860_MULTI_BCN_NUM_SHIFT 18 454 #define RT2860_MULTI_BSSID_MODE_SHIFT 16 455 456 /* possible flags for register MAX_LEN_CFG */ 457 #define RT2860_MIN_MPDU_LEN_SHIFT 16 458 #define RT2860_MAX_PSDU_LEN_SHIFT 12 459 #define RT2860_MAX_PSDU_LEN8K 0 460 #define RT2860_MAX_PSDU_LEN16K 1 461 #define RT2860_MAX_PSDU_LEN32K 2 462 #define RT2860_MAX_PSDU_LEN64K 3 463 #define RT2860_MAX_MPDU_LEN_SHIFT 0 464 465 /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */ 466 #define RT2860_BBP_RW_PARALLEL (1 << 19) 467 #define RT2860_BBP_PAR_DUR_112_5 (1 << 18) 468 #define RT2860_BBP_CSR_KICK (1 << 17) 469 #define RT2860_BBP_CSR_READ (1 << 16) 470 #define RT2860_BBP_ADDR_SHIFT 8 471 #define RT2860_BBP_DATA_SHIFT 0 472 473 /* possible flags for register RF_CSR_CFG0 */ 474 #define RT2860_RF_REG_CTRL (1U << 31) 475 #define RT2860_RF_LE_SEL1 (1U << 30) 476 #define RT2860_RF_LE_STBY (1U << 29) 477 #define RT2860_RF_REG_WIDTH_SHIFT 24 478 #define RT2860_RF_REG_0_SHIFT 0 479 480 /* possible flags for register RF_CSR_CFG1 */ 481 #define RT2860_RF_DUR_5 (1 << 24) 482 #define RT2860_RF_REG_1_SHIFT 0 483 484 /* possible flags for register LED_CFG */ 485 #define RT2860_LED_POL (1 << 30) 486 #define RT2860_Y_LED_MODE_SHIFT 28 487 #define RT2860_G_LED_MODE_SHIFT 26 488 #define RT2860_R_LED_MODE_SHIFT 24 489 #define RT2860_LED_MODE_OFF 0 490 #define RT2860_LED_MODE_BLINK_TX 1 491 #define RT2860_LED_MODE_SLOW_BLINK 2 492 #define RT2860_LED_MODE_ON 3 493 #define RT2860_SLOW_BLK_TIME_SHIFT 16 494 #define RT2860_LED_OFF_TIME_SHIFT 8 495 #define RT2860_LED_ON_TIME_SHIFT 0 496 497 /* possible flags for register XIFS_TIME_CFG */ 498 #define RT2860_BB_RXEND_EN (1 << 29) 499 #define RT2860_EIFS_TIME_SHIFT 20 500 #define RT2860_OFDM_XIFS_TIME_SHIFT 16 501 #define RT2860_OFDM_SIFS_TIME_SHIFT 8 502 #define RT2860_CCK_SIFS_TIME_SHIFT 0 503 504 /* possible flags for register BKOFF_SLOT_CFG */ 505 #define RT2860_CC_DELAY_TIME_SHIFT 8 506 #define RT2860_SLOT_TIME 0 507 508 /* possible flags for register NAV_TIME_CFG */ 509 #define RT2860_NAV_UPD (1U << 31) 510 #define RT2860_NAV_UPD_VAL_SHIFT 16 511 #define RT2860_NAV_CLR_EN (1U << 15) 512 #define RT2860_NAV_TIMER_SHIFT 0 513 514 /* possible flags for register CH_TIME_CFG */ 515 #define RT2860_EIFS_AS_CH_BUSY (1 << 4) 516 #define RT2860_NAV_AS_CH_BUSY (1 << 3) 517 #define RT2860_RX_AS_CH_BUSY (1 << 2) 518 #define RT2860_TX_AS_CH_BUSY (1 << 1) 519 #define RT2860_CH_STA_TIMER_EN (1 << 0) 520 521 /* possible values for register BCN_TIME_CFG */ 522 #define RT2860_TSF_INS_COMP_SHIFT 24 523 #define RT2860_BCN_TX_EN (1 << 20) 524 #define RT2860_TBTT_TIMER_EN (1 << 19) 525 #define RT2860_TSF_SYNC_MODE_SHIFT 17 526 #define RT2860_TSF_SYNC_MODE_DIS 0 527 #define RT2860_TSF_SYNC_MODE_STA 1 528 #define RT2860_TSF_SYNC_MODE_IBSS 2 529 #define RT2860_TSF_SYNC_MODE_HOSTAP 3 530 #define RT2860_TSF_TIMER_EN (1 << 16) 531 #define RT2860_BCN_INTVAL_SHIFT 0 532 533 /* possible flags for register TBTT_SYNC_CFG */ 534 #define RT2860_BCN_CWMIN_SHIFT 20 535 #define RT2860_BCN_AIFSN_SHIFT 16 536 #define RT2860_BCN_EXP_WIN_SHIFT 8 537 #define RT2860_TBTT_ADJUST_SHIFT 0 538 539 /* possible flags for register INT_TIMER_CFG */ 540 #define RT2860_GP_TIMER_SHIFT 16 541 #define RT2860_PRE_TBTT_TIMER_SHIFT 0 542 543 /* possible flags for register INT_TIMER_EN */ 544 #define RT2860_GP_TIMER_EN (1 << 1) 545 #define RT2860_PRE_TBTT_INT_EN (1 << 0) 546 547 /* possible flags for register MAC_STATUS_REG */ 548 #define RT2860_RX_STATUS_BUSY (1 << 1) 549 #define RT2860_TX_STATUS_BUSY (1 << 0) 550 551 /* possible flags for register PWR_PIN_CFG */ 552 #define RT2860_IO_ADDA_PD (1 << 3) 553 #define RT2860_IO_PLL_PD (1 << 2) 554 #define RT2860_IO_RA_PE (1 << 1) 555 #define RT2860_IO_RF_PE (1 << 0) 556 557 /* possible flags for register AUTO_WAKEUP_CFG */ 558 #define RT2860_AUTO_WAKEUP_EN (1 << 15) 559 #define RT2860_SLEEP_TBTT_NUM_SHIFT 8 560 #define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 561 562 /* possible flags for register TX_PIN_CFG */ 563 #define RT3593_LNA_PE_G2_POL (1U << 31) 564 #define RT3593_LNA_PE_A2_POL (1U << 30) 565 #define RT3593_LNA_PE_G2_EN (1U << 29) 566 #define RT3593_LNA_PE_A2_EN (1U << 28) 567 #define RT3593_LNA_PE2_EN (RT3593_LNA_PE_A2_EN | RT3593_LNA_PE_G2_EN) 568 #define RT3593_PA_PE_G2_POL (1U << 27) 569 #define RT3593_PA_PE_A2_POL (1U << 26) 570 #define RT3593_PA_PE_G2_EN (1U << 25) 571 #define RT3593_PA_PE_A2_EN (1U << 24) 572 #define RT2860_TRSW_POL (1U << 19) 573 #define RT2860_TRSW_EN (1U << 18) 574 #define RT2860_RFTR_POL (1U << 17) 575 #define RT2860_RFTR_EN (1U << 16) 576 #define RT2860_LNA_PE_G1_POL (1U << 15) 577 #define RT2860_LNA_PE_A1_POL (1U << 14) 578 #define RT2860_LNA_PE_G0_POL (1U << 13) 579 #define RT2860_LNA_PE_A0_POL (1U << 12) 580 #define RT2860_LNA_PE_G1_EN (1U << 11) 581 #define RT2860_LNA_PE_A1_EN (1U << 10) 582 #define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) 583 #define RT2860_LNA_PE_G0_EN (1U << 9) 584 #define RT2860_LNA_PE_A0_EN (1U << 8) 585 #define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) 586 #define RT2860_PA_PE_G1_POL (1U << 7) 587 #define RT2860_PA_PE_A1_POL (1U << 6) 588 #define RT2860_PA_PE_G0_POL (1U << 5) 589 #define RT2860_PA_PE_A0_POL (1U << 4) 590 #define RT2860_PA_PE_G1_EN (1U << 3) 591 #define RT2860_PA_PE_A1_EN (1U << 2) 592 #define RT2860_PA_PE_G0_EN (1U << 1) 593 #define RT2860_PA_PE_A0_EN (1U << 0) 594 595 /* possible flags for register TX_BAND_CFG */ 596 #define RT2860_5G_BAND_SEL_N (1 << 2) 597 #define RT2860_5G_BAND_SEL_P (1 << 1) 598 #define RT2860_TX_BAND_SEL (1 << 0) 599 600 /* possible flags for register TX_SW_CFG0 */ 601 #define RT2860_DLY_RFTR_EN_SHIFT 24 602 #define RT2860_DLY_TRSW_EN_SHIFT 16 603 #define RT2860_DLY_PAPE_EN_SHIFT 8 604 #define RT2860_DLY_TXPE_EN_SHIFT 0 605 606 /* possible flags for register TX_SW_CFG1 */ 607 #define RT2860_DLY_RFTR_DIS_SHIFT 16 608 #define RT2860_DLY_TRSW_DIS_SHIFT 8 609 #define RT2860_DLY_PAPE_DIS SHIFT 0 610 611 /* possible flags for register TX_SW_CFG2 */ 612 #define RT2860_DLY_LNA_EN_SHIFT 24 613 #define RT2860_DLY_LNA_DIS_SHIFT 16 614 #define RT2860_DLY_DAC_EN_SHIFT 8 615 #define RT2860_DLY_DAC_DIS_SHIFT 0 616 617 /* possible flags for register TXOP_THRES_CFG */ 618 #define RT2860_TXOP_REM_THRES_SHIFT 24 619 #define RT2860_CF_END_THRES_SHIFT 16 620 #define RT2860_RDG_IN_THRES 8 621 #define RT2860_RDG_OUT_THRES 0 622 623 /* possible flags for register TXOP_CTRL_CFG */ 624 #define RT2860_EXT_CW_MIN_SHIFT 16 625 #define RT2860_EXT_CCA_DLY_SHIFT 8 626 #define RT2860_EXT_CCA_EN (1 << 7) 627 #define RT2860_LSIG_TXOP_EN (1 << 6) 628 #define RT2860_TXOP_TRUN_EN_MIMOPS (1 << 4) 629 #define RT2860_TXOP_TRUN_EN_TXOP (1 << 3) 630 #define RT2860_TXOP_TRUN_EN_RATE (1 << 2) 631 #define RT2860_TXOP_TRUN_EN_AC (1 << 1) 632 #define RT2860_TXOP_TRUN_EN_TIMEOUT (1 << 0) 633 634 /* possible flags for register TX_RTS_CFG */ 635 #define RT2860_RTS_FBK_EN (1 << 24) 636 #define RT2860_RTS_THRES_SHIFT 8 637 #define RT2860_RTS_RTY_LIMIT_SHIFT 0 638 639 /* possible flags for register TX_TIMEOUT_CFG */ 640 #define RT2860_TXOP_TIMEOUT_SHIFT 16 641 #define RT2860_RX_ACK_TIMEOUT_SHIFT 8 642 #define RT2860_MPDU_LIFE_TIME_SHIFT 4 643 644 /* possible flags for register TX_RTY_CFG */ 645 #define RT2860_TX_AUTOFB_EN (1 << 30) 646 #define RT2860_AGG_RTY_MODE_TIMER (1 << 29) 647 #define RT2860_NAG_RTY_MODE_TIMER (1 << 28) 648 #define RT2860_LONG_RTY_THRES_SHIFT 16 649 #define RT2860_LONG_RTY_LIMIT_SHIFT 8 650 #define RT2860_SHORT_RTY_LIMIT_SHIFT 0 651 652 /* possible flags for register TX_LINK_CFG */ 653 #define RT2860_REMOTE_MFS_SHIFT 24 654 #define RT2860_REMOTE_MFB_SHIFT 16 655 #define RT2860_TX_CFACK_EN (1 << 12) 656 #define RT2860_TX_RDG_EN (1 << 11) 657 #define RT2860_TX_MRQ_EN (1 << 10) 658 #define RT2860_REMOTE_UMFS_EN (1 << 9) 659 #define RT2860_TX_MFB_EN (1 << 8) 660 #define RT2860_REMOTE_MFB_LT_SHIFT 0 661 662 /* possible flags for registers *_PROT_CFG */ 663 #define RT2860_RTSTH_EN (1 << 26) 664 #define RT2860_TXOP_ALLOW_GF40 (1 << 25) 665 #define RT2860_TXOP_ALLOW_GF20 (1 << 24) 666 #define RT2860_TXOP_ALLOW_MM40 (1 << 23) 667 #define RT2860_TXOP_ALLOW_MM20 (1 << 22) 668 #define RT2860_TXOP_ALLOW_OFDM (1 << 21) 669 #define RT2860_TXOP_ALLOW_CCK (1 << 20) 670 #define RT2860_TXOP_ALLOW_ALL (0x3f << 20) 671 #define RT2860_PROT_NAV_SHORT (1 << 18) 672 #define RT2860_PROT_NAV_LONG (2 << 18) 673 #define RT2860_PROT_CTRL_RTS_CTS (1 << 16) 674 #define RT2860_PROT_CTRL_CTS (2 << 16) 675 676 /* possible flags for registers EXP_{CTS,ACK}_TIME */ 677 #define RT2860_EXP_OFDM_TIME_SHIFT 16 678 #define RT2860_EXP_CCK_TIME_SHIFT 0 679 680 /* possible flags for register RX_FILTR_CFG */ 681 #define RT2860_DROP_CTRL_RSV (1 << 16) 682 #define RT2860_DROP_BAR (1 << 15) 683 #define RT2860_DROP_BA (1 << 14) 684 #define RT2860_DROP_PSPOLL (1 << 13) 685 #define RT2860_DROP_RTS (1 << 12) 686 #define RT2860_DROP_CTS (1 << 11) 687 #define RT2860_DROP_ACK (1 << 10) 688 #define RT2860_DROP_CFEND (1 << 9) 689 #define RT2860_DROP_CFACK (1 << 8) 690 #define RT2860_DROP_DUPL (1 << 7) 691 #define RT2860_DROP_BC (1 << 6) 692 #define RT2860_DROP_MC (1 << 5) 693 #define RT2860_DROP_VER_ERR (1 << 4) 694 #define RT2860_DROP_NOT_MYBSS (1 << 3) 695 #define RT2860_DROP_UC_NOME (1 << 2) 696 #define RT2860_DROP_PHY_ERR (1 << 1) 697 #define RT2860_DROP_CRC_ERR (1 << 0) 698 699 /* possible flags for register AUTO_RSP_CFG */ 700 #define RT2860_CTRL_PWR_BIT (1 << 7) 701 #define RT2860_BAC_ACK_POLICY (1 << 6) 702 #define RT2860_CCK_SHORT_EN (1 << 4) 703 #define RT2860_CTS_40M_REF_EN (1 << 3) 704 #define RT2860_CTS_40M_MODE_EN (1 << 2) 705 #define RT2860_BAC_ACKPOLICY_EN (1 << 1) 706 #define RT2860_AUTO_RSP_EN (1 << 0) 707 708 /* possible flags for register SIFS_COST_CFG */ 709 #define RT2860_OFDM_SIFS_COST_SHIFT 8 710 #define RT2860_CCK_SIFS_COST_SHIFT 0 711 712 /* possible flags for register TXOP_HLDR_ET */ 713 #define RT2860_TXOP_ETM1_EN (1 << 25) 714 #define RT2860_TXOP_ETM0_EN (1 << 24) 715 #define RT2860_TXOP_ETM_THRES_SHIFT 16 716 #define RT2860_TXOP_ETO_EN (1 << 8) 717 #define RT2860_TXOP_ETO_THRES_SHIFT 1 718 #define RT2860_PER_RX_RST_EN (1 << 0) 719 720 /* possible flags for register TX_STAT_FIFO */ 721 #define RT2860_TXQ_MCS_SHIFT 16 722 #define RT2860_TXQ_WCID_SHIFT 8 723 #define RT2860_TXQ_ACKREQ (1 << 7) 724 #define RT2860_TXQ_AGG (1 << 6) 725 #define RT2860_TXQ_OK (1 << 5) 726 #define RT2860_TXQ_PID_SHIFT 1 727 #define RT2860_TXQ_VLD (1 << 0) 728 729 /* possible flags for register WCID_ATTR */ 730 #define RT2860_MODE_NOSEC 0 731 #define RT2860_MODE_WEP40 1 732 #define RT2860_MODE_WEP104 2 733 #define RT2860_MODE_TKIP 3 734 #define RT2860_MODE_AES_CCMP 4 735 #define RT2860_MODE_CKIP40 5 736 #define RT2860_MODE_CKIP104 6 737 #define RT2860_MODE_CKIP128 7 738 #define RT2860_RX_PKEY_EN (1 << 0) 739 740 /* possible flags for register H2M_MAILBOX */ 741 #define RT2860_H2M_BUSY (1 << 24) 742 #define RT2860_TOKEN_NO_INTR 0xff 743 744 745 /* possible flags for MCU command RT2860_MCU_CMD_LEDS */ 746 #define RT2860_LED_RADIO (1 << 13) 747 #define RT2860_LED_LINK_2GHZ (1 << 14) 748 #define RT2860_LED_LINK_5GHZ (1 << 15) 749 750 751 /* possible flags for RT3020 RF register 1 */ 752 #define RT3070_RF_BLOCK (1 << 0) 753 #define RT3070_PLL_PD (1 << 1) 754 #define RT3070_RX0_PD (1 << 2) 755 #define RT3070_TX0_PD (1 << 3) 756 #define RT3070_RX1_PD (1 << 4) 757 #define RT3070_TX1_PD (1 << 5) 758 #define RT3070_RX2_PD (1 << 6) 759 #define RT3070_TX2_PD (1 << 7) 760 761 /* possible flags for RT3020 RF register 7 */ 762 #define RT3070_TUNE (1 << 0) 763 764 /* possible flags for RT3020 RF register 15 */ 765 #define RT3070_TX_LO2 (1 << 3) 766 767 /* possible flags for RT3020 RF register 17 */ 768 #define RT3070_TX_LO1 (1 << 3) 769 770 /* possible flags for RT3020 RF register 20 */ 771 #define RT3070_RX_LO1 (1 << 3) 772 773 /* possible flags for RT3020 RF register 21 */ 774 #define RT3070_RX_LO2 (1 << 3) 775 #define RT3070_RX_CTB (1 << 7) 776 777 /* possible flags for RT3020 RF register 22 */ 778 #define RT3070_BB_LOOPBACK (1 << 0) 779 780 /* possible flags for RT3053 RF register 1 */ 781 #define RT3593_VCO (1 << 0) 782 783 /* possible flags for RT3053 RF register 2 */ 784 #define RT3593_RESCAL (1 << 7) 785 786 /* possible flags for RT3053 RF register 3 */ 787 #define RT3593_VCOCAL (1 << 7) 788 789 /* possible flags for RT3053 RF register 6 */ 790 #define RT3593_VCO_IC (1 << 6) 791 792 /* possible flags for RT3053 RF register 18 */ 793 #define RT3593_AUTOTUNE_BYPASS (1 << 6) 794 795 /* possible flags for RT3053 RF register 20 */ 796 #define RT3593_LDO_PLL_VC_MASK 0x0e 797 #define RT3593_LDO_RF_VC_MASK 0xe0 798 799 /* possible flags for RT3053 RF register 22 */ 800 #define RT3593_CP_IC_MASK 0xe0 801 #define RT3593_CP_IC_SHIFT 5 802 803 /* possible flags for RT5390 RF register 38. */ 804 #define RT5390_RX_LO1 (1 << 5) 805 806 /* possible flags for RT5390 RF register 39. */ 807 #define RT5390_RX_LO2 (1 << 7) 808 809 /* possible flags for RT5390 RF register 42 */ 810 #define RT5390_RX_CTB (1 << 6) 811 812 /* possible flags for RT3053 RF register 46 */ 813 #define RT3593_RX_CTB (1 << 5) 814 815 /* possible flags for RT3053 RF register 50 */ 816 #define RT3593_TX_LO2 (1 << 4) 817 818 /* possible flags for RT3053 RF register 51 */ 819 #define RT3593_TX_LO1 (1 << 4) 820 821 /* Possible flags for RT5390 BBP register 4. */ 822 #define RT5390_MAC_IF_CTRL (1 << 6) 823 824 /* possible flags for RT5390 BBP register 105. */ 825 #define RT5390_MLD (1 << 2) 826 #define RT5390_EN_SIG_MODULATION (1 << 3) 827 828 #define RT3090_DEF_LNA 10 829 830 /* RT2860 TX descriptor */ 831 struct rt2860_txd { 832 uint32_t sdp0; /* Segment Data Pointer 0 */ 833 uint16_t sdl1; /* Segment Data Length 1 */ 834 #define RT2860_TX_BURST (1 << 15) 835 #define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */ 836 837 uint16_t sdl0; /* Segment Data Length 0 */ 838 #define RT2860_TX_DDONE (1 << 15) 839 #define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */ 840 841 uint32_t sdp1; /* Segment Data Pointer 1 */ 842 uint8_t reserved[3]; 843 uint8_t flags; 844 #define RT2860_TX_QSEL_SHIFT 1 845 #define RT2860_TX_QSEL_MGMT (0 << 1) 846 #define RT2860_TX_QSEL_HCCA (1 << 1) 847 #define RT2860_TX_QSEL_EDCA (2 << 1) 848 #define RT2860_TX_WIV (1 << 0) 849 } __packed; 850 851 /* RT2870 TX descriptor */ 852 struct rt2870_txd { 853 uint16_t len; 854 uint8_t pad; 855 uint8_t flags; 856 } __packed; 857 858 /* TX Wireless Information */ 859 struct rt2860_txwi { 860 uint8_t flags; 861 #define RT2860_TX_MPDU_DSITY_SHIFT 5 862 #define RT2860_TX_AMPDU (1 << 4) 863 #define RT2860_TX_TS (1 << 3) 864 #define RT2860_TX_CFACK (1 << 2) 865 #define RT2860_TX_MMPS (1 << 1) 866 #define RT2860_TX_FRAG (1 << 0) 867 868 uint8_t txop; 869 #define RT2860_TX_TXOP_HT 0 870 #define RT2860_TX_TXOP_PIFS 1 871 #define RT2860_TX_TXOP_SIFS 2 872 #define RT2860_TX_TXOP_BACKOFF 3 873 874 uint16_t phy; 875 #define RT2860_PHY_MODE 0xc000 876 #define RT2860_PHY_CCK (0 << 14) 877 #define RT2860_PHY_OFDM (1 << 14) 878 #define RT2860_PHY_HT (2 << 14) 879 #define RT2860_PHY_HT_GF (3 << 14) 880 #define RT2860_PHY_SGI (1 << 8) 881 #define RT2860_PHY_BW40 (1 << 7) 882 #define RT2860_PHY_MCS 0x7f 883 #define RT2860_PHY_SHPRE (1 << 3) 884 885 uint8_t xflags; 886 #define RT2860_TX_BAWINSIZE_SHIFT 2 887 #define RT2860_TX_NSEQ (1 << 1) 888 #define RT2860_TX_ACK (1 << 0) 889 890 uint8_t wcid; /* Wireless Client ID */ 891 uint16_t len; 892 #define RT2860_TX_PID_SHIFT 12 893 894 uint32_t iv; 895 uint32_t eiv; 896 } __packed; 897 898 /* RT2860 RX descriptor */ 899 struct rt2860_rxd { 900 uint32_t sdp0; 901 uint16_t sdl1; /* unused */ 902 uint16_t sdl0; 903 #define RT2860_RX_DDONE (1 << 15) 904 #define RT2860_RX_LS0 (1 << 14) 905 906 uint32_t sdp1; /* unused */ 907 uint32_t flags; 908 #define RT2860_RX_DEC (1 << 16) 909 #define RT2860_RX_AMPDU (1 << 15) 910 #define RT2860_RX_L2PAD (1 << 14) 911 #define RT2860_RX_RSSI (1 << 13) 912 #define RT2860_RX_HTC (1 << 12) 913 #define RT2860_RX_AMSDU (1 << 11) 914 #define RT2860_RX_MICERR (1 << 10) 915 #define RT2860_RX_ICVERR (1 << 9) 916 #define RT2860_RX_CRCERR (1 << 8) 917 #define RT2860_RX_MYBSS (1 << 7) 918 #define RT2860_RX_BC (1 << 6) 919 #define RT2860_RX_MC (1 << 5) 920 #define RT2860_RX_UC2ME (1 << 4) 921 #define RT2860_RX_FRAG (1 << 3) 922 #define RT2860_RX_NULL (1 << 2) 923 #define RT2860_RX_DATA (1 << 1) 924 #define RT2860_RX_BA (1 << 0) 925 } __packed; 926 927 /* RT2870 RX descriptor */ 928 struct rt2870_rxd { 929 /* single 32-bit field */ 930 uint32_t flags; 931 } __packed; 932 933 /* RX Wireless Information */ 934 struct rt2860_rxwi { 935 uint8_t wcid; 936 uint8_t keyidx; 937 #define RT2860_RX_UDF_SHIFT 5 938 #define RT2860_RX_BSS_IDX_SHIFT 2 939 940 uint16_t len; 941 #define RT2860_RX_TID_SHIFT 12 942 943 uint16_t seq; 944 uint16_t phy; 945 uint8_t rssi[3]; 946 uint8_t reserved1; 947 uint8_t snr[2]; 948 uint16_t reserved2; 949 } __packed; 950 951 952 /* first DMA segment contains TXWI + 802.11 header + 32-bit padding */ 953 #define RT2860_TXWI_DMASZ \ 954 (sizeof (struct rt2860_txwi) + \ 955 sizeof (struct ieee80211_htframe) + \ 956 sizeof (uint16_t)) 957 958 #define RT2860_RF1 0 959 #define RT2860_RF2 2 960 #define RT2860_RF3 1 961 #define RT2860_RF4 3 962 963 #define RT2860_RF_2820 0x0001 /* 2T3R */ 964 #define RT2860_RF_2850 0x0002 /* dual-band 2T3R */ 965 #define RT2860_RF_2720 0x0003 /* 1T2R */ 966 #define RT2860_RF_2750 0x0004 /* dual-band 1T2R */ 967 #define RT3070_RF_3020 0x0005 /* 1T1R */ 968 #define RT3070_RF_2020 0x0006 /* b/g */ 969 #define RT3070_RF_3021 0x0007 /* 1T2R */ 970 #define RT3070_RF_3022 0x0008 /* 2T2R */ 971 #define RT3070_RF_3052 0x0009 /* dual-band 2T2R */ 972 #define RT3070_RF_3320 0x000b /* 1T1R */ 973 #define RT3070_RF_3053 0x000d /* dual-band 3T3R */ 974 #define RT5592_RF_5592 0x000f /* dual-band 2T2R */ 975 #define RT3290_RF_3290 0x3290 /* 1T1R */ 976 #define RT5390_RF_5360 0x5360 /* 1T1R */ 977 #define RT5390_RF_5370 0x5370 /* 1T1R */ 978 #define RT5390_RF_5372 0x5372 /* 2T2R */ 979 #define RT5390_RF_5390 0x5390 /* 1T1R */ 980 #define RT5390_RF_5392 0x5392 /* 2T2R */ 981 982 /* USB commands for RT2870 only */ 983 #define RT2870_RESET 1 984 #define RT2870_WRITE_2 2 985 #define RT2870_WRITE_REGION_1 6 986 #define RT2870_READ_REGION_1 7 987 #define RT2870_EEPROM_READ 9 988 989 #define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 990 991 #define RT2860_EEPROM_CHIPID 0x00 992 #define RT2860_EEPROM_VERSION 0x01 993 #define RT2860_EEPROM_MAC01 0x02 994 #define RT2860_EEPROM_MAC23 0x03 995 #define RT2860_EEPROM_MAC45 0x04 996 #define RT2860_EEPROM_PCIE_PSLEVEL 0x11 997 #define RT2860_EEPROM_REV 0x12 998 #define RT2860_EEPROM_ANTENNA 0x1a 999 #define RT2860_EEPROM_CONFIG 0x1b 1000 #define RT2860_EEPROM_COUNTRY 0x1c 1001 #define RT2860_EEPROM_FREQ_LEDS 0x1d 1002 #define RT2860_EEPROM_LED1 0x1e 1003 #define RT2860_EEPROM_LED2 0x1f 1004 #define RT2860_EEPROM_LED3 0x20 1005 #define RT2860_EEPROM_LNA 0x22 1006 #define RT2860_EEPROM_RSSI1_2GHZ 0x23 1007 #define RT2860_EEPROM_RSSI2_2GHZ 0x24 1008 #define RT2860_EEPROM_RSSI1_5GHZ 0x25 1009 #define RT2860_EEPROM_RSSI2_5GHZ 0x26 1010 #define RT2860_EEPROM_DELTAPWR 0x28 1011 #define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 1012 #define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 1013 #define RT2860_EEPROM_TSSI1_2GHZ 0x37 1014 #define RT2860_EEPROM_TSSI2_2GHZ 0x38 1015 #define RT2860_EEPROM_TSSI3_2GHZ 0x39 1016 #define RT2860_EEPROM_TSSI4_2GHZ 0x3a 1017 #define RT2860_EEPROM_TSSI5_2GHZ 0x3b 1018 #define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c 1019 #define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 1020 #define RT2860_EEPROM_TSSI1_5GHZ 0x6a 1021 #define RT2860_EEPROM_TSSI2_5GHZ 0x6b 1022 #define RT2860_EEPROM_TSSI3_5GHZ 0x6c 1023 #define RT2860_EEPROM_TSSI4_5GHZ 0x6d 1024 #define RT2860_EEPROM_TSSI5_5GHZ 0x6e 1025 #define RT2860_EEPROM_RPWR 0x6f 1026 #define RT2860_EEPROM_BBP_BASE 0x78 1027 #define RT3071_EEPROM_RF_BASE 0x82 1028 1029 /* EEPROM registers for RT3593. */ 1030 #define RT3593_EEPROM_FREQ_LEDS 0x21 1031 #define RT3593_EEPROM_FREQ 0x22 1032 #define RT3593_EEPROM_LED1 0x22 1033 #define RT3593_EEPROM_LED2 0x23 1034 #define RT3593_EEPROM_LED3 0x24 1035 #define RT3593_EEPROM_LNA 0x26 1036 #define RT3593_EEPROM_LNA_5GHZ 0x27 1037 #define RT3593_EEPROM_RSSI1_2GHZ 0x28 1038 #define RT3593_EEPROM_RSSI2_2GHZ 0x29 1039 #define RT3593_EEPROM_RSSI1_5GHZ 0x2a 1040 #define RT3593_EEPROM_RSSI2_5GHZ 0x2b 1041 #define RT3593_EEPROM_PWR2GHZ_BASE1 0x30 1042 #define RT3593_EEPROM_PWR2GHZ_BASE2 0x37 1043 #define RT3593_EEPROM_PWR2GHZ_BASE3 0x3e 1044 #define RT3593_EEPROM_PWR5GHZ_BASE1 0x4b 1045 #define RT3593_EEPROM_PWR5GHZ_BASE2 0x65 1046 #define RT3593_EEPROM_PWR5GHZ_BASE3 0x7f 1047 1048 /* 1049 * EEPROM IQ calibration. 1050 */ 1051 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ 0x130 1052 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ 0x131 1053 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ 0x133 1054 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ 0x134 1055 #define RT5390_EEPROM_RF_IQ_COMPENSATION_CTL 0x13c 1056 #define RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL 0x13d 1057 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ 0x144 1058 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ 0x145 1059 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ 0x146 1060 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ 0x147 1061 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ 0x148 1062 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ 0x149 1063 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ 0x14a 1064 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ 0x14b 1065 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ 0x14c 1066 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ 0x14d 1067 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ 0x14e 1068 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ 0x14f 1069 1070 #define RT2860_RIDX_CCK1 0 1071 #define RT2860_RIDX_CCK11 3 1072 #define RT2860_RIDX_OFDM6 4 1073 #define RT2860_RIDX_MAX 11 1074 static const struct rt2860_rate { 1075 uint8_t rate; 1076 uint8_t mcs; 1077 enum ieee80211_phytype phy; 1078 uint8_t ctl_ridx; 1079 uint16_t sp_ack_dur; 1080 uint16_t lp_ack_dur; 1081 } rt2860_rates[] = { 1082 { 2, 0, IEEE80211_T_DS, 0, 314, 314 }, 1083 { 4, 1, IEEE80211_T_DS, 1, 258, 162 }, 1084 { 11, 2, IEEE80211_T_DS, 2, 223, 127 }, 1085 { 22, 3, IEEE80211_T_DS, 3, 213, 117 }, 1086 { 12, 0, IEEE80211_T_OFDM, 4, 60, 60 }, 1087 { 18, 1, IEEE80211_T_OFDM, 4, 52, 52 }, 1088 { 24, 2, IEEE80211_T_OFDM, 6, 48, 48 }, 1089 { 36, 3, IEEE80211_T_OFDM, 6, 44, 44 }, 1090 { 48, 4, IEEE80211_T_OFDM, 8, 44, 44 }, 1091 { 72, 5, IEEE80211_T_OFDM, 8, 40, 40 }, 1092 { 96, 6, IEEE80211_T_OFDM, 8, 40, 40 }, 1093 { 108, 7, IEEE80211_T_OFDM, 8, 40, 40 } 1094 }; 1095 1096 /* 1097 * Control and status registers access macros. 1098 */ 1099 #define RAL_READ(sc, reg) \ 1100 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 1101 1102 #define RAL_WRITE(sc, reg, val) \ 1103 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 1104 1105 #define RAL_BARRIER_WRITE(sc) \ 1106 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 1107 BUS_SPACE_BARRIER_WRITE) 1108 1109 #define RAL_BARRIER_READ_WRITE(sc) \ 1110 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 1111 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 1112 1113 #define RAL_WRITE_REGION_1(sc, offset, datap, count) \ 1114 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 1115 (datap), (count)) 1116 1117 #define RAL_SET_REGION_4(sc, offset, val, count) \ 1118 bus_space_set_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 1119 (val), (count)) 1120 1121 /* 1122 * EEPROM access macro. 1123 */ 1124 #define RT2860_EEPROM_CTL(sc, val) do { \ 1125 RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \ 1126 RAL_BARRIER_READ_WRITE((sc)); \ 1127 DELAY(RT2860_EEPROM_DELAY); \ 1128 } while (/* CONSTCOND */0) 1129 1130 /* 1131 * Default values for MAC registers; values taken from the reference driver. 1132 */ 1133 #define RT2860_DEF_MAC \ 1134 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 1135 { RT2860_BCN_OFFSET1, 0x6f77d0c8 }, \ 1136 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 1137 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 1138 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 1139 { RT2860_RX_FILTR_CFG, 0x00017f97 }, \ 1140 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 1141 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 1142 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 1143 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 1144 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1145 { RT2860_MAX_LEN_CFG, 0x00001f00 }, \ 1146 { RT2860_LED_CFG, 0x7f031e46 }, \ 1147 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 1148 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 1149 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 1150 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 1151 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 1152 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 1153 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 1154 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 1155 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 1156 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1157 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1158 { RT2860_MM40_PROT_CFG, 0x03f54084 }, \ 1159 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1160 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1161 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1162 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1163 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1164 { RT2860_PWR_PIN_CFG, 0x00000003 } 1165 1166 /* XXX only a few registers differ from above, try to merge? */ 1167 #define RT2870_DEF_MAC \ 1168 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 1169 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 1170 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 1171 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 1172 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 1173 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 1174 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 1175 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 1176 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1177 { RT2860_LED_CFG, 0x7f031e46 }, \ 1178 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 1179 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 1180 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 1181 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 1182 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 1183 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 1184 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 1185 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 1186 { RT2860_PBF_CFG, 0x00f40006 }, \ 1187 { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \ 1188 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 1189 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1190 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1191 { RT2860_MM40_PROT_CFG, 0x03f44084 }, \ 1192 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1193 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1194 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1195 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1196 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1197 { RT2860_PWR_PIN_CFG, 0x00000003 } 1198 1199 /* 1200 * Default values for BBP registers; values taken from the reference driver. 1201 */ 1202 #define RT2860_DEF_BBP \ 1203 { 65, 0x2c }, \ 1204 { 66, 0x38 }, \ 1205 { 68, 0x0b }, \ 1206 { 69, 0x12 }, \ 1207 { 70, 0x0a }, \ 1208 { 73, 0x10 }, \ 1209 { 81, 0x37 }, \ 1210 { 82, 0x62 }, \ 1211 { 83, 0x6a }, \ 1212 { 84, 0x99 }, \ 1213 { 86, 0x00 }, \ 1214 { 91, 0x04 }, \ 1215 { 92, 0x00 }, \ 1216 { 103, 0x00 }, \ 1217 { 105, 0x05 }, \ 1218 { 106, 0x35 } 1219 1220 #define RT3290_DEF_BBP \ 1221 { 31, 0x08 }, \ 1222 { 68, 0x0b }, \ 1223 { 73, 0x13 }, \ 1224 { 75, 0x46 }, \ 1225 { 76, 0x28 }, \ 1226 { 77, 0x59 }, \ 1227 { 82, 0x62 }, \ 1228 { 83, 0x7a }, \ 1229 { 84, 0x9a }, \ 1230 { 86, 0x38 }, \ 1231 { 91, 0x04 }, \ 1232 { 103, 0xc0 }, \ 1233 { 104, 0x92 }, \ 1234 { 105, 0x3c }, \ 1235 { 106, 0x03 }, \ 1236 { 128, 0x12 } 1237 1238 #define RT5390_DEF_BBP \ 1239 { 31, 0x08 }, \ 1240 { 65, 0x2c }, \ 1241 { 66, 0x38 }, \ 1242 { 68, 0x0b }, \ 1243 { 69, 0x0d }, \ 1244 { 70, 0x06 }, \ 1245 { 73, 0x13 }, \ 1246 { 75, 0x46 }, \ 1247 { 76, 0x28 }, \ 1248 { 77, 0x59 }, \ 1249 { 81, 0x37 }, \ 1250 { 82, 0x62 }, \ 1251 { 83, 0x7a }, \ 1252 { 84, 0x9a }, \ 1253 { 86, 0x38 }, \ 1254 { 91, 0x04 }, \ 1255 { 92, 0x02 }, \ 1256 { 103, 0xc0 }, \ 1257 { 104, 0x92 }, \ 1258 { 105, 0x3c }, \ 1259 { 106, 0x03 }, \ 1260 { 128, 0x12 } 1261 1262 #define RT5592_DEF_BBP \ 1263 { 20, 0x06 }, \ 1264 { 31, 0x08 }, \ 1265 { 65, 0x2c }, \ 1266 { 66, 0x38 }, \ 1267 { 68, 0xdd }, \ 1268 { 69, 0x1a }, \ 1269 { 70, 0x05 }, \ 1270 { 73, 0x13 }, \ 1271 { 74, 0x0f }, \ 1272 { 75, 0x4f }, \ 1273 { 76, 0x28 }, \ 1274 { 77, 0x59 }, \ 1275 { 81, 0x37 }, \ 1276 { 82, 0x62 }, \ 1277 { 83, 0x6a }, \ 1278 { 84, 0x9a }, \ 1279 { 86, 0x38 }, \ 1280 { 88, 0x90 }, \ 1281 { 91, 0x04 }, \ 1282 { 92, 0x02 }, \ 1283 { 95, 0x9a }, \ 1284 { 98, 0x12 }, \ 1285 { 103, 0xc0 }, \ 1286 { 104, 0x92 }, \ 1287 { 105, 0x3c }, \ 1288 { 106, 0x35 }, \ 1289 { 128, 0x12 }, \ 1290 { 134, 0xd0 }, \ 1291 { 135, 0xf6 }, \ 1292 { 137, 0x0f } 1293 1294 /* 1295 * Default settings for RF registers; values derived from the reference driver. 1296 */ 1297 #define RT2860_RF2850 \ 1298 { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, \ 1299 { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, \ 1300 { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 }, \ 1301 { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, \ 1302 { 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, \ 1303 { 6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 }, \ 1304 { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 }, \ 1305 { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, \ 1306 { 9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 }, \ 1307 { 10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 }, \ 1308 { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 }, \ 1309 { 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, \ 1310 { 13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 }, \ 1311 { 14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 }, \ 1312 { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 }, \ 1313 { 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, \ 1314 { 40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 }, \ 1315 { 44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 }, \ 1316 { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 }, \ 1317 { 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, \ 1318 { 52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 }, \ 1319 { 54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 }, \ 1320 { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 }, \ 1321 { 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, \ 1322 { 62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 }, \ 1323 { 64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 }, \ 1324 { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 }, \ 1325 { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 }, \ 1326 { 104, 0x100bb2, 0x1701ac, 0x15e014, 0x001408 }, \ 1327 { 108, 0x100bb3, 0x17028c, 0x15e014, 0x001404 }, \ 1328 { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 }, \ 1329 { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, \ 1330 { 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 }, \ 1331 { 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 }, \ 1332 { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 }, \ 1333 { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, \ 1334 { 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 }, \ 1335 { 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 }, \ 1336 { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 }, \ 1337 { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, \ 1338 { 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 }, \ 1339 { 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 }, \ 1340 { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 }, \ 1341 { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, \ 1342 { 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 }, \ 1343 { 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 }, \ 1344 { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 }, \ 1345 { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, \ 1346 { 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 }, \ 1347 { 167, 0x100bb1, 0x1300f4, 0x05e014, 0x001407 }, \ 1348 { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 }, \ 1349 { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 }, \ 1350 { 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 } 1351 1352 #define RT3070_RF3052 \ 1353 { 0xf1, 2, 2 }, \ 1354 { 0xf1, 2, 7 }, \ 1355 { 0xf2, 2, 2 }, \ 1356 { 0xf2, 2, 7 }, \ 1357 { 0xf3, 2, 2 }, \ 1358 { 0xf3, 2, 7 }, \ 1359 { 0xf4, 2, 2 }, \ 1360 { 0xf4, 2, 7 }, \ 1361 { 0xf5, 2, 2 }, \ 1362 { 0xf5, 2, 7 }, \ 1363 { 0xf6, 2, 2 }, \ 1364 { 0xf6, 2, 7 }, \ 1365 { 0xf7, 2, 2 }, \ 1366 { 0xf8, 2, 4 }, \ 1367 { 0x56, 0, 4 }, \ 1368 { 0x56, 0, 6 }, \ 1369 { 0x56, 0, 8 }, \ 1370 { 0x57, 0, 0 }, \ 1371 { 0x57, 0, 2 }, \ 1372 { 0x57, 0, 4 }, \ 1373 { 0x57, 0, 8 }, \ 1374 { 0x57, 0, 10 }, \ 1375 { 0x58, 0, 0 }, \ 1376 { 0x58, 0, 4 }, \ 1377 { 0x58, 0, 6 }, \ 1378 { 0x58, 0, 8 }, \ 1379 { 0x5b, 0, 8 }, \ 1380 { 0x5b, 0, 10 }, \ 1381 { 0x5c, 0, 0 }, \ 1382 { 0x5c, 0, 4 }, \ 1383 { 0x5c, 0, 6 }, \ 1384 { 0x5c, 0, 8 }, \ 1385 { 0x5d, 0, 0 }, \ 1386 { 0x5d, 0, 2 }, \ 1387 { 0x5d, 0, 4 }, \ 1388 { 0x5d, 0, 8 }, \ 1389 { 0x5d, 0, 10 }, \ 1390 { 0x5e, 0, 0 }, \ 1391 { 0x5e, 0, 4 }, \ 1392 { 0x5e, 0, 6 }, \ 1393 { 0x5e, 0, 8 }, \ 1394 { 0x5f, 0, 0 }, \ 1395 { 0x5f, 0, 9 }, \ 1396 { 0x5f, 0, 11 }, \ 1397 { 0x60, 0, 1 }, \ 1398 { 0x60, 0, 5 }, \ 1399 { 0x60, 0, 7 }, \ 1400 { 0x60, 0, 9 }, \ 1401 { 0x61, 0, 1 }, \ 1402 { 0x61, 0, 3 }, \ 1403 { 0x61, 0, 5 }, \ 1404 { 0x61, 0, 7 }, \ 1405 { 0x61, 0, 9 } 1406 1407 #define RT5592_RF5592_20MHZ \ 1408 { 0x1e2, 4, 10, 3 }, \ 1409 { 0x1e3, 4, 10, 3 }, \ 1410 { 0x1e4, 4, 10, 3 }, \ 1411 { 0x1e5, 4, 10, 3 }, \ 1412 { 0x1e6, 4, 10, 3 }, \ 1413 { 0x1e7, 4, 10, 3 }, \ 1414 { 0x1e8, 4, 10, 3 }, \ 1415 { 0x1e9, 4, 10, 3 }, \ 1416 { 0x1ea, 4, 10, 3 }, \ 1417 { 0x1eb, 4, 10, 3 }, \ 1418 { 0x1ec, 4, 10, 3 }, \ 1419 { 0x1ed, 4, 10, 3 }, \ 1420 { 0x1ee, 4, 10, 3 }, \ 1421 { 0x1f0, 8, 10, 3 }, \ 1422 { 0xac, 8, 12, 1 }, \ 1423 { 0xad, 0, 12, 1 }, \ 1424 { 0xad, 4, 12, 1 }, \ 1425 { 0xae, 0, 12, 1 }, \ 1426 { 0xae, 4, 12, 1 }, \ 1427 { 0xae, 8, 12, 1 }, \ 1428 { 0xaf, 4, 12, 1 }, \ 1429 { 0xaf, 8, 12, 1 }, \ 1430 { 0xb0, 0, 12, 1 }, \ 1431 { 0xb0, 8, 12, 1 }, \ 1432 { 0xb1, 0, 12, 1 }, \ 1433 { 0xb1, 4, 12, 1 }, \ 1434 { 0xb7, 4, 12, 1 }, \ 1435 { 0xb7, 8, 12, 1 }, \ 1436 { 0xb8, 0, 12, 1 }, \ 1437 { 0xb8, 8, 12, 1 }, \ 1438 { 0xb9, 0, 12, 1 }, \ 1439 { 0xb9, 4, 12, 1 }, \ 1440 { 0xba, 0, 12, 1 }, \ 1441 { 0xba, 4, 12, 1 }, \ 1442 { 0xba, 8, 12, 1 }, \ 1443 { 0xbb, 4, 12, 1 }, \ 1444 { 0xbb, 8, 12, 1 }, \ 1445 { 0xbc, 0, 12, 1 }, \ 1446 { 0xbc, 8, 12, 1 }, \ 1447 { 0xbd, 0, 12, 1 }, \ 1448 { 0xbd, 4, 12, 1 }, \ 1449 { 0xbe, 0, 12, 1 }, \ 1450 { 0xbf, 6, 12, 1 }, \ 1451 { 0xbf, 10, 12, 1 }, \ 1452 { 0xc0, 2, 12, 1 }, \ 1453 { 0xc0, 10, 12, 1 }, \ 1454 { 0xc1, 2, 12, 1 }, \ 1455 { 0xc1, 6, 12, 1 }, \ 1456 { 0xc2, 2, 12, 1 }, \ 1457 { 0xa4, 0, 12, 1 }, \ 1458 { 0xa4, 4, 12, 1 }, \ 1459 { 0xa5, 8, 12, 1 }, \ 1460 { 0xa6, 0, 12, 1 } 1461 1462 #define RT5592_RF5592_40MHZ \ 1463 { 0xf1, 2, 10, 3 }, \ 1464 { 0xf1, 7, 10, 3 }, \ 1465 { 0xf2, 2, 10, 3 }, \ 1466 { 0xf2, 7, 10, 3 }, \ 1467 { 0xf3, 2, 10, 3 }, \ 1468 { 0xf3, 7, 10, 3 }, \ 1469 { 0xf4, 2, 10, 3 }, \ 1470 { 0xf4, 7, 10, 3 }, \ 1471 { 0xf5, 2, 10, 3 }, \ 1472 { 0xf5, 7, 10, 3 }, \ 1473 { 0xf6, 2, 10, 3 }, \ 1474 { 0xf6, 7, 10, 3 }, \ 1475 { 0xf7, 2, 10, 3 }, \ 1476 { 0xf8, 4, 10, 3 }, \ 1477 { 0x56, 4, 12, 1 }, \ 1478 { 0x56, 6, 12, 1 }, \ 1479 { 0x56, 8, 12, 1 }, \ 1480 { 0x57, 0, 12, 1 }, \ 1481 { 0x57, 2, 12, 1 }, \ 1482 { 0x57, 4, 12, 1 }, \ 1483 { 0x57, 8, 12, 1 }, \ 1484 { 0x57, 10, 12, 1 }, \ 1485 { 0x58, 0, 12, 1 }, \ 1486 { 0x58, 4, 12, 1 }, \ 1487 { 0x58, 6, 12, 1 }, \ 1488 { 0x58, 8, 12, 1 }, \ 1489 { 0x5b, 8, 12, 1 }, \ 1490 { 0x5b, 10, 12, 1 }, \ 1491 { 0x5c, 0, 12, 1 }, \ 1492 { 0x5c, 4, 12, 1 }, \ 1493 { 0x5c, 6, 12, 1 }, \ 1494 { 0x5c, 8, 12, 1 }, \ 1495 { 0x5d, 0, 12, 1 }, \ 1496 { 0x5d, 2, 12, 1 }, \ 1497 { 0x5d, 4, 12, 1 }, \ 1498 { 0x5d, 8, 12, 1 }, \ 1499 { 0x5d, 10, 12, 1 }, \ 1500 { 0x5e, 0, 12, 1 }, \ 1501 { 0x5e, 4, 12, 1 }, \ 1502 { 0x5e, 6, 12, 1 }, \ 1503 { 0x5e, 8, 12, 1 }, \ 1504 { 0x5f, 0, 12, 1 }, \ 1505 { 0x5f, 9, 12, 1 }, \ 1506 { 0x5f, 11, 12, 1 }, \ 1507 { 0x60, 1, 12, 1 }, \ 1508 { 0x60, 5, 12, 1 }, \ 1509 { 0x60, 7, 12, 1 }, \ 1510 { 0x60, 9, 12, 1 }, \ 1511 { 0x61, 1, 12, 1 }, \ 1512 { 0x52, 0, 12, 1 }, \ 1513 { 0x52, 4, 12, 1 }, \ 1514 { 0x52, 8, 12, 1 }, \ 1515 { 0x53, 0, 12, 1 } 1516 1517 #define RT3070_DEF_RF \ 1518 { 4, 0x40 }, \ 1519 { 5, 0x03 }, \ 1520 { 6, 0x02 }, \ 1521 { 7, 0x60 }, \ 1522 { 9, 0x0f }, \ 1523 { 10, 0x41 }, \ 1524 { 11, 0x21 }, \ 1525 { 12, 0x7b }, \ 1526 { 14, 0x90 }, \ 1527 { 15, 0x58 }, \ 1528 { 16, 0xb3 }, \ 1529 { 17, 0x92 }, \ 1530 { 18, 0x2c }, \ 1531 { 19, 0x02 }, \ 1532 { 20, 0xba }, \ 1533 { 21, 0xdb }, \ 1534 { 24, 0x16 }, \ 1535 { 25, 0x01 }, \ 1536 { 29, 0x1f } 1537 1538 #define RT3290_DEF_RF \ 1539 { 1, 0x0f }, \ 1540 { 2, 0x80 }, \ 1541 { 3, 0x08 }, \ 1542 { 4, 0x00 }, \ 1543 { 6, 0xa0 }, \ 1544 { 8, 0xf3 }, \ 1545 { 9, 0x02 }, \ 1546 { 10, 0x53 }, \ 1547 { 11, 0x4a }, \ 1548 { 12, 0x46 }, \ 1549 { 13, 0x9f }, \ 1550 { 18, 0x03 }, \ 1551 { 22, 0x20 }, \ 1552 { 25, 0x80 }, \ 1553 { 27, 0x09 }, \ 1554 { 29, 0x10 }, \ 1555 { 30, 0x10 }, \ 1556 { 31, 0x80 }, \ 1557 { 32, 0x80 }, \ 1558 { 33, 0x00 }, \ 1559 { 34, 0x05 }, \ 1560 { 35, 0x12 }, \ 1561 { 36, 0x00 }, \ 1562 { 38, 0x85 }, \ 1563 { 39, 0x1b }, \ 1564 { 40, 0x0b }, \ 1565 { 41, 0xbb }, \ 1566 { 42, 0xd5 }, \ 1567 { 43, 0x7b }, \ 1568 { 44, 0x0e }, \ 1569 { 45, 0xa2 }, \ 1570 { 46, 0x73 }, \ 1571 { 47, 0x00 }, \ 1572 { 48, 0x10 }, \ 1573 { 49, 0x98 }, \ 1574 { 52, 0x38 }, \ 1575 { 53, 0x00 }, \ 1576 { 54, 0x78 }, \ 1577 { 55, 0x43 }, \ 1578 { 56, 0x02 }, \ 1579 { 57, 0x80 }, \ 1580 { 58, 0x7f }, \ 1581 { 59, 0x09 }, \ 1582 { 60, 0x45 }, \ 1583 { 61, 0xc1 } 1584 1585 #define RT3572_DEF_RF \ 1586 { 0, 0x70 }, \ 1587 { 1, 0x81 }, \ 1588 { 2, 0xf1 }, \ 1589 { 3, 0x02 }, \ 1590 { 4, 0x4c }, \ 1591 { 5, 0x05 }, \ 1592 { 6, 0x4a }, \ 1593 { 7, 0xd8 }, \ 1594 { 9, 0xc3 }, \ 1595 { 10, 0xf1 }, \ 1596 { 11, 0xb9 }, \ 1597 { 12, 0x70 }, \ 1598 { 13, 0x65 }, \ 1599 { 14, 0xa0 }, \ 1600 { 15, 0x53 }, \ 1601 { 16, 0x4c }, \ 1602 { 17, 0x23 }, \ 1603 { 18, 0xac }, \ 1604 { 19, 0x93 }, \ 1605 { 20, 0xb3 }, \ 1606 { 21, 0xd0 }, \ 1607 { 22, 0x00 }, \ 1608 { 23, 0x3c }, \ 1609 { 24, 0x16 }, \ 1610 { 25, 0x15 }, \ 1611 { 26, 0x85 }, \ 1612 { 27, 0x00 }, \ 1613 { 28, 0x00 }, \ 1614 { 29, 0x9b }, \ 1615 { 30, 0x09 }, \ 1616 { 31, 0x10 } 1617 1618 #define RT3593_DEF_RF \ 1619 { 1, 0x03 }, \ 1620 { 3, 0x80 }, \ 1621 { 5, 0x00 }, \ 1622 { 6, 0x40 }, \ 1623 { 8, 0xf1 }, \ 1624 { 9, 0x02 }, \ 1625 { 10, 0xd3 }, \ 1626 { 11, 0x40 }, \ 1627 { 12, 0x4e }, \ 1628 { 13, 0x12 }, \ 1629 { 18, 0x40 }, \ 1630 { 22, 0x20 }, \ 1631 { 30, 0x10 }, \ 1632 { 31, 0x80 }, \ 1633 { 32, 0x78 }, \ 1634 { 33, 0x3b }, \ 1635 { 34, 0x3c }, \ 1636 { 35, 0xe0 }, \ 1637 { 38, 0x86 }, \ 1638 { 39, 0x23 }, \ 1639 { 44, 0xd3 }, \ 1640 { 45, 0xbb }, \ 1641 { 46, 0x60 }, \ 1642 { 49, 0x81 }, \ 1643 { 50, 0x86 }, \ 1644 { 51, 0x75 }, \ 1645 { 52, 0x45 }, \ 1646 { 53, 0x18 }, \ 1647 { 54, 0x18 }, \ 1648 { 55, 0x18 }, \ 1649 { 56, 0xdb }, \ 1650 { 57, 0x6e } 1651 1652 #define RT5390_DEF_RF \ 1653 { 1, 0x0f }, \ 1654 { 2, 0x80 }, \ 1655 { 3, 0x88 }, \ 1656 { 5, 0x10 }, \ 1657 { 6, 0xa0 }, \ 1658 { 7, 0x00 }, \ 1659 { 10, 0x53 }, \ 1660 { 11, 0x4a }, \ 1661 { 12, 0x46 }, \ 1662 { 13, 0x9f }, \ 1663 { 14, 0x00 }, \ 1664 { 15, 0x00 }, \ 1665 { 16, 0x00 }, \ 1666 { 18, 0x03 }, \ 1667 { 19, 0x00 }, \ 1668 { 20, 0x00 }, \ 1669 { 21, 0x00 }, \ 1670 { 22, 0x20 }, \ 1671 { 23, 0x00 }, \ 1672 { 24, 0x00 }, \ 1673 { 25, 0xc0 }, \ 1674 { 26, 0x00 }, \ 1675 { 27, 0x09 }, \ 1676 { 28, 0x00 }, \ 1677 { 29, 0x10 }, \ 1678 { 30, 0x10 }, \ 1679 { 31, 0x80 }, \ 1680 { 32, 0x80 }, \ 1681 { 33, 0x00 }, \ 1682 { 34, 0x07 }, \ 1683 { 35, 0x12 }, \ 1684 { 36, 0x00 }, \ 1685 { 37, 0x08 }, \ 1686 { 38, 0x85 }, \ 1687 { 39, 0x1b }, \ 1688 { 40, 0x0b }, \ 1689 { 41, 0xbb }, \ 1690 { 42, 0xd2 }, \ 1691 { 43, 0x9a }, \ 1692 { 44, 0x0e }, \ 1693 { 45, 0xa2 }, \ 1694 { 46, 0x7b }, \ 1695 { 47, 0x00 }, \ 1696 { 48, 0x10 }, \ 1697 { 49, 0x94 }, \ 1698 { 52, 0x38 }, \ 1699 { 53, 0x84 }, \ 1700 { 54, 0x78 }, \ 1701 { 55, 0x44 }, \ 1702 { 56, 0x22 }, \ 1703 { 57, 0x80 }, \ 1704 { 58, 0x7f }, \ 1705 { 59, 0x8f }, \ 1706 { 60, 0x45 }, \ 1707 { 61, 0xdd }, \ 1708 { 62, 0x00 }, \ 1709 { 63, 0x00 } 1710 1711 #define RT5392_DEF_RF \ 1712 { 1, 0x17 }, \ 1713 { 3, 0x88 }, \ 1714 { 5, 0x10 }, \ 1715 { 6, 0xe0 }, \ 1716 { 7, 0x00 }, \ 1717 { 10, 0x53 }, \ 1718 { 11, 0x4a }, \ 1719 { 12, 0x46 }, \ 1720 { 13, 0x9f }, \ 1721 { 14, 0x00 }, \ 1722 { 15, 0x00 }, \ 1723 { 16, 0x00 }, \ 1724 { 18, 0x03 }, \ 1725 { 19, 0x4d }, \ 1726 { 20, 0x00 }, \ 1727 { 21, 0x8d }, \ 1728 { 22, 0x20 }, \ 1729 { 23, 0x0b }, \ 1730 { 24, 0x44 }, \ 1731 { 25, 0x80 }, \ 1732 { 26, 0x82 }, \ 1733 { 27, 0x09 }, \ 1734 { 28, 0x00 }, \ 1735 { 29, 0x10 }, \ 1736 { 30, 0x10 }, \ 1737 { 31, 0x80 }, \ 1738 { 32, 0x20 }, \ 1739 { 33, 0xc0 }, \ 1740 { 34, 0x07 }, \ 1741 { 35, 0x12 }, \ 1742 { 36, 0x00 }, \ 1743 { 37, 0x08 }, \ 1744 { 38, 0x89 }, \ 1745 { 39, 0x1b }, \ 1746 { 40, 0x0f }, \ 1747 { 41, 0xbb }, \ 1748 { 42, 0xd5 }, \ 1749 { 43, 0x9b }, \ 1750 { 44, 0x0e }, \ 1751 { 45, 0xa2 }, \ 1752 { 46, 0x73 }, \ 1753 { 47, 0x0c }, \ 1754 { 48, 0x10 }, \ 1755 { 49, 0x94 }, \ 1756 { 50, 0x94 }, \ 1757 { 51, 0x3a }, \ 1758 { 52, 0x48 }, \ 1759 { 53, 0x44 }, \ 1760 { 54, 0x38 }, \ 1761 { 55, 0x43 }, \ 1762 { 56, 0xa1 }, \ 1763 { 57, 0x00 }, \ 1764 { 58, 0x39 }, \ 1765 { 59, 0x07 }, \ 1766 { 60, 0x45 }, \ 1767 { 61, 0x91 }, \ 1768 { 62, 0x39 }, \ 1769 { 63, 0x07 } 1770 1771 #define RT5592_DEF_RF \ 1772 { 1, 0x3f }, \ 1773 { 3, 0x08 }, \ 1774 { 5, 0x10 }, \ 1775 { 6, 0xe4 }, \ 1776 { 7, 0x00 }, \ 1777 { 14, 0x00 }, \ 1778 { 15, 0x00 }, \ 1779 { 16, 0x00 }, \ 1780 { 18, 0x03 }, \ 1781 { 19, 0x4d }, \ 1782 { 20, 0x10 }, \ 1783 { 21, 0x8d }, \ 1784 { 26, 0x82 }, \ 1785 { 28, 0x00 }, \ 1786 { 29, 0x10 }, \ 1787 { 33, 0xc0 }, \ 1788 { 34, 0x07 }, \ 1789 { 35, 0x12 }, \ 1790 { 47, 0x0c }, \ 1791 { 53, 0x22 }, \ 1792 { 63, 0x07 } 1793 1794 #define RT5592_2GHZ_DEF_RF \ 1795 { 10, 0x90 }, \ 1796 { 11, 0x4a }, \ 1797 { 12, 0x52 }, \ 1798 { 13, 0x42 }, \ 1799 { 22, 0x40 }, \ 1800 { 24, 0x4a }, \ 1801 { 25, 0x80 }, \ 1802 { 27, 0x42 }, \ 1803 { 36, 0x80 }, \ 1804 { 37, 0x08 }, \ 1805 { 38, 0x89 }, \ 1806 { 39, 0x1b }, \ 1807 { 40, 0x0d }, \ 1808 { 41, 0x9b }, \ 1809 { 42, 0xd5 }, \ 1810 { 43, 0x72 }, \ 1811 { 44, 0x0e }, \ 1812 { 45, 0xa2 }, \ 1813 { 46, 0x6b }, \ 1814 { 48, 0x10 }, \ 1815 { 51, 0x3e }, \ 1816 { 52, 0x48 }, \ 1817 { 54, 0x38 }, \ 1818 { 56, 0xa1 }, \ 1819 { 57, 0x00 }, \ 1820 { 58, 0x39 }, \ 1821 { 60, 0x45 }, \ 1822 { 61, 0x91 }, \ 1823 { 62, 0x39 } 1824 1825 #define RT5592_5GHZ_DEF_RF \ 1826 { 10, 0x97 }, \ 1827 { 11, 0x40 }, \ 1828 { 25, 0xbf }, \ 1829 { 27, 0x42 }, \ 1830 { 36, 0x00 }, \ 1831 { 37, 0x04 }, \ 1832 { 38, 0x85 }, \ 1833 { 40, 0x42 }, \ 1834 { 41, 0xbb }, \ 1835 { 42, 0xd7 }, \ 1836 { 45, 0x41 }, \ 1837 { 48, 0x00 }, \ 1838 { 57, 0x77 }, \ 1839 { 60, 0x05 }, \ 1840 { 61, 0x01 } 1841 1842 #define RT5592_CHAN_5GHZ \ 1843 { 36, 64, 12, 0x2e }, \ 1844 { 100, 165, 12, 0x0e }, \ 1845 { 36, 64, 13, 0x22 }, \ 1846 { 100, 165, 13, 0x42 }, \ 1847 { 36, 64, 22, 0x60 }, \ 1848 { 100, 165, 22, 0x40 }, \ 1849 { 36, 64, 23, 0x7f }, \ 1850 { 100, 153, 23, 0x3c }, \ 1851 { 155, 165, 23, 0x38 }, \ 1852 { 36, 50, 24, 0x09 }, \ 1853 { 52, 64, 24, 0x07 }, \ 1854 { 100, 153, 24, 0x06 }, \ 1855 { 155, 165, 24, 0x05 }, \ 1856 { 36, 64, 39, 0x1c }, \ 1857 { 100, 138, 39, 0x1a }, \ 1858 { 140, 165, 39, 0x18 }, \ 1859 { 36, 64, 43, 0x5b }, \ 1860 { 100, 138, 43, 0x3b }, \ 1861 { 140, 165, 43, 0x1b }, \ 1862 { 36, 64, 44, 0x40 }, \ 1863 { 100, 138, 44, 0x20 }, \ 1864 { 140, 165, 44, 0x10 }, \ 1865 { 36, 64, 46, 0x00 }, \ 1866 { 100, 138, 46, 0x18 }, \ 1867 { 140, 165, 46, 0x08 }, \ 1868 { 36, 64, 51, 0xfe }, \ 1869 { 100, 124, 51, 0xfc }, \ 1870 { 126, 165, 51, 0xec }, \ 1871 { 36, 64, 52, 0x0c }, \ 1872 { 100, 138, 52, 0x06 }, \ 1873 { 140, 165, 52, 0x06 }, \ 1874 { 36, 64, 54, 0xf8 }, \ 1875 { 100, 165, 54, 0xeb }, \ 1876 { 36, 50, 55, 0x06 }, \ 1877 { 52, 64, 55, 0x04 }, \ 1878 { 100, 138, 55, 0x01 }, \ 1879 { 140, 165, 55, 0x00 }, \ 1880 { 36, 50, 56, 0xd3 }, \ 1881 { 52, 128, 56, 0xbb }, \ 1882 { 130, 165, 56, 0xab }, \ 1883 { 36, 64, 58, 0x15 }, \ 1884 { 100, 116, 58, 0x1d }, \ 1885 { 118, 165, 58, 0x15 }, \ 1886 { 36, 64, 59, 0x7f }, \ 1887 { 100, 138, 59, 0x3f }, \ 1888 { 140, 165, 59, 0x7c }, \ 1889 { 36, 64, 62, 0x15 }, \ 1890 { 100, 116, 62, 0x1d }, \ 1891 { 118, 165, 62, 0x15 }
Cache object: e30437c1d5b9630c61fa35396294ce94
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]