rtl80x9reg.h

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    1 /*      $NetBSD: rtl80x9reg.h,v 1.4 2004/02/13 10:05:50 wiz Exp $       */
    2 
    3 /*-
    4  * Copyright (c) 1998 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
    9  * NASA Ames Research Center.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  * 3. All advertising materials mentioning features or use of this software
   20  *    must display the following acknowledgement:
   21  *      This product includes software developed by the NetBSD
   22  *      Foundation, Inc. and its contributors.
   23  * 4. Neither the name of The NetBSD Foundation nor the names of its
   24  *    contributors may be used to endorse or promote products derived
   25  *    from this software without specific prior written permission.
   26  *
   27  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   28  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   29  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   30  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   31  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   32  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   33  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   34  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   35  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   36  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   37  * POSSIBILITY OF SUCH DAMAGE.
   38  */
   39 
   40 /*
   41  * Registers on Realtek 8019 and 8029 NE2000-compatible network interfaces.
   42  *
   43  * Data sheets for these chips can be found at:
   44  *
   45  *      http://www.realtek.com.tw
   46  */
   47 
   48 #ifndef _DEV_IC_RTL80x9_REG_H_
   49 #define _DEV_IC_RTL80x9_REG_H_
   50 
   51 /*
   52  * Page 0 register offsets.
   53  */
   54 #define NERTL_RTL0_8019ID0      0x0a    /* 8019 ID Register 0 */
   55 #define RTL0_8019ID0            'P'
   56 
   57 #define NERTL_RTL0_8019ID1      0x0b    /* 8019 ID Register 1 */
   58 #define RTL0_8019ID1            'p'
   59 
   60 /*
   61  * Page 3 register offsets.
   62  */
   63 #define NERTL_RTL3_EECR         0x01    /* EEPROM Command Register */
   64 #define RTL3_EECR_EEM1          0x80    /* EEPROM Operating Mode */
   65 #define RTL3_EECR_EEM0          0x40    
   66                                         /* 0 0 Normal operation */
   67                                         /* 0 1 Auto-load */
   68                                         /* 1 0 9346 programming */
   69                                         /* 1 1 Config register write enab */
   70 #define RTL3_EECR_EECS          0x08    /* EEPROM Chip Select */
   71 #define RTL3_EECR_EESK          0x04    /* EEPROM Clock */
   72 #define RTL3_EECR_EEDI          0x02    /* EEPROM Data In */
   73 #define RTL3_EECR_EEDO          0x01    /* EEPROM Data Out */
   74 
   75 #define NERTL_RTL3_BPAGE        0x02    /* BROM Page Register (8019) */
   76 
   77 #define NERTL_RTL3_CONFIG0      0x03    /* Configuration 0 (ro) */
   78 #define RTL3_CONFIG0_JP         0x08    /* jumper mode (8019) */
   79 #define RTL3_CONFIG0_BNC        0x04    /* BNC is active */
   80 
   81 #define NERTL_RTL3_CONFIG1      0x04    /* Configuration 1 (8019) */
   82 #define RTL3_CONFIG1_IRQEN      0x80    /* IRQ Enable */
   83 #define RTL3_CONFIG1_IRQS2      0x40    /* IRQ Select */
   84 #define RTL3_CONFIG1_IRQS1      0x20
   85 #define RTL3_CONFIG1_IRQS0      0x10
   86                                         /* 0 0 0 int 0 irq 2/9 */
   87                                         /* 0 0 1 int 1 irq 3 */
   88                                         /* 0 1 0 int 2 irq 4 */
   89                                         /* 0 1 1 int 3 irq 5 */
   90                                         /* 1 0 0 int 4 irq 10 */
   91                                         /* 1 0 1 int 5 irq 11 */
   92                                         /* 1 1 0 int 6 irq 12 */
   93                                         /* 1 1 1 int 7 irq 15 */
   94 #define RTL_CONFIG1_IOS3        0x08    /* I/O base Select */
   95 #define RTL_CONFIG1_IOS2        0x04
   96 #define RTL_CONFIG1_IOS1        0x02
   97 #define RTL_CONFIG1_IOS0        0x01
   98                                         /* 0 0 0 0 0x300 */
   99                                         /* 0 0 0 1 0x320 */
  100                                         /* 0 0 1 0 0x340 */
  101                                         /* 0 0 1 1 0x360 */
  102                                         /* 0 1 0 0 0x380 */
  103                                         /* 0 1 0 1 0x3a0 */
  104                                         /* 0 1 1 0 0x3c0 */
  105                                         /* 0 1 1 1 0x3e0 */
  106                                         /* 1 0 0 0 0x200 */
  107                                         /* 1 0 0 1 0x220 */
  108                                         /* 1 0 1 0 0x240 */
  109                                         /* 1 0 1 1 0x260 */
  110                                         /* 1 1 0 0 0x280 */
  111                                         /* 1 1 0 1 0x2a0 */
  112                                         /* 1 1 1 0 0x2c0 */
  113                                         /* 1 1 1 1 0x2e0 */
  114 
  115 #define NERTL_RTL3_CONFIG2      0x05    /* Configuration 2 */
  116 #define RTL3_CONFIG2_PL1        0x80    /* Network media type */
  117 #define RTL3_CONFIG2_PL0        0x40
  118                                         /* 0 0 TP/CX auto-detect */
  119                                         /* 0 1 10baseT */
  120                                         /* 1 0 10base5 */
  121                                         /* 1 1 10base2 */
  122 #define RTL3_CONFIG2_8029FCE    0x20    /* Flow Control Enable */
  123 #define RTL3_CONFIG2_8029PF     0x10    /* Pause Flag */
  124 #define RTL3_CONFIG2_8029BS1    0x02    /* Boot Rom Size */
  125 #define RTL3_CONFIG2_8029BS0    0x01
  126                                         /* 0 0 No Boot Rom */
  127                                         /* 0 1 8k */
  128                                         /* 1 0 16k */
  129                                         /* 1 1 32k */
  130 #define RTL3_CONFIG2_8019BSELB  0x20    /* BROM disable */
  131 #define RTL3_CONFIG2_8019BS4    0x10    /* BROM size/base */
  132 #define RTL3_CONFIG2_8019BS3    0x08
  133 #define RTL3_CONFIG2_8019BS2    0x04
  134 #define RTL3_CONFIG2_8019BS1    0x02
  135 #define RTL3_CONFIG2_8019BS0    0x01
  136 
  137 #define NERTL_RTL3_CONFIG3      0x06    /* Configuration 3 */
  138 #define RTL3_CONFIG3_8019PNP    0x80    /* PnP Mode */
  139 #define RTL3_CONFIG3_FUDUP      0x40    /* Full Duplex */
  140 #define RTL3_CONFIG3_LEDS1      0x20    /* LED1/2 pin configuration */
  141                                         /* 0 LED1 == LED_RX, LED2 == LED_TX */
  142                                         /* 1 LED1 == LED_CRS, LED2 == MCSB */
  143 #define RTL3_CONFIG3_LEDS0      0x10    /* LED0 pin configuration */
  144                                         /* 0 LED0 pin == LED_COL */
  145                                         /* 1 LED0 pin == LED_LINK */
  146 #define RTL3_CONFIG3_SLEEP      0x04    /* Sleep mode */
  147 #define RTL3_CONFIG3_PWRDN      0x02    /* Power Down */
  148 #define RTL3_CONFIG3_8019ACTIVEB 0x01   /* inverse of bit 0 in PnP Act Reg */
  149 
  150 #define NERTL_RTL3_CSNSAV       0x08    /* CSN Save Register (8019) */
  151 
  152 #define NERTL_RTL3_HLTCLK       0x09    /* Halt Clock */
  153 #define RTL3_HLTCLK_RUNNING     'R'     /* clock runs in power down */
  154 #define RTL3_HLTCLK_HALTED      'H'     /* clock halted in power down */
  155 
  156 #define NERTL_RTL3_INTR         0x0b    /* ISA bus states of INT7-0 (8019) */
  157 
  158 #define NERTL_RTL3_8029ID0      0x0e    /* ID register 0 */
  159 
  160 #define NERTL_RTL3_8029ID1      0x0f    /* ID register 1 */
  161 
  162 #endif /* _DEV_IC_RTL80x9_REG_H_ */

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FreeBSD/Linux Kernel Cross Reference sys/dev/ic/rtl80x9reg.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/rtl80x9reg.h