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sys/dev/ic/rtl8169.c
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1 /* $NetBSD: rtl8169.c,v 1.105.4.8 2009/06/19 21:51:43 snj Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.105.4.8 2009/06/19 21:51:43 snj Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 51 * and the RTL8110S. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 #include "bpfilter.h" 115 #include "vlan.h" 116 117 #include <sys/param.h> 118 #include <sys/endian.h> 119 #include <sys/systm.h> 120 #include <sys/sockio.h> 121 #include <sys/mbuf.h> 122 #include <sys/malloc.h> 123 #include <sys/kernel.h> 124 #include <sys/socket.h> 125 #include <sys/device.h> 126 127 #include <net/if.h> 128 #include <net/if_arp.h> 129 #include <net/if_dl.h> 130 #include <net/if_ether.h> 131 #include <net/if_media.h> 132 #include <net/if_vlanvar.h> 133 134 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 135 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 136 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 137 138 #if NBPFILTER > 0 139 #include <net/bpf.h> 140 #endif 141 142 #include <sys/bus.h> 143 144 #include <dev/mii/mii.h> 145 #include <dev/mii/miivar.h> 146 147 #include <dev/ic/rtl81x9reg.h> 148 #include <dev/ic/rtl81x9var.h> 149 150 #include <dev/ic/rtl8169var.h> 151 152 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 153 154 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 155 static int re_rx_list_init(struct rtk_softc *); 156 static int re_tx_list_init(struct rtk_softc *); 157 static void re_rxeof(struct rtk_softc *); 158 static void re_txeof(struct rtk_softc *); 159 static void re_tick(void *); 160 static void re_start(struct ifnet *); 161 static int re_ioctl(struct ifnet *, u_long, void *); 162 static int re_init(struct ifnet *); 163 static void re_stop(struct ifnet *, int); 164 static void re_watchdog(struct ifnet *); 165 166 static int re_enable(struct rtk_softc *); 167 static void re_disable(struct rtk_softc *); 168 169 static int re_gmii_readreg(struct device *, int, int); 170 static void re_gmii_writereg(struct device *, int, int, int); 171 172 static int re_miibus_readreg(struct device *, int, int); 173 static void re_miibus_writereg(struct device *, int, int, int); 174 static void re_miibus_statchg(struct device *); 175 176 static void re_reset(struct rtk_softc *); 177 178 static inline void 179 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 180 { 181 182 d->re_bufaddr_lo = htole32((uint32_t)addr); 183 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 184 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32); 185 else 186 d->re_bufaddr_hi = 0; 187 } 188 189 static int 190 re_gmii_readreg(device_t dev, int phy, int reg) 191 { 192 struct rtk_softc *sc = device_private(dev); 193 uint32_t rval; 194 int i; 195 196 if (phy != 7) 197 return 0; 198 199 /* Let the rgephy driver read the GMEDIASTAT register */ 200 201 if (reg == RTK_GMEDIASTAT) { 202 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 203 return rval; 204 } 205 206 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 207 DELAY(1000); 208 209 for (i = 0; i < RTK_TIMEOUT; i++) { 210 rval = CSR_READ_4(sc, RTK_PHYAR); 211 if (rval & RTK_PHYAR_BUSY) 212 break; 213 DELAY(100); 214 } 215 216 if (i == RTK_TIMEOUT) { 217 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 218 return 0; 219 } 220 221 return rval & RTK_PHYAR_PHYDATA; 222 } 223 224 static void 225 re_gmii_writereg(device_t dev, int phy, int reg, int data) 226 { 227 struct rtk_softc *sc = device_private(dev); 228 uint32_t rval; 229 int i; 230 231 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 232 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 233 DELAY(1000); 234 235 for (i = 0; i < RTK_TIMEOUT; i++) { 236 rval = CSR_READ_4(sc, RTK_PHYAR); 237 if (!(rval & RTK_PHYAR_BUSY)) 238 break; 239 DELAY(100); 240 } 241 242 if (i == RTK_TIMEOUT) { 243 printf("%s: PHY write reg %x <- %x failed\n", 244 device_xname(sc->sc_dev), reg, data); 245 } 246 } 247 248 static int 249 re_miibus_readreg(device_t dev, int phy, int reg) 250 { 251 struct rtk_softc *sc = device_private(dev); 252 uint16_t rval = 0; 253 uint16_t re8139_reg = 0; 254 int s; 255 256 s = splnet(); 257 258 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 259 rval = re_gmii_readreg(dev, phy, reg); 260 splx(s); 261 return rval; 262 } 263 264 /* Pretend the internal PHY is only at address 0 */ 265 if (phy) { 266 splx(s); 267 return 0; 268 } 269 switch (reg) { 270 case MII_BMCR: 271 re8139_reg = RTK_BMCR; 272 break; 273 case MII_BMSR: 274 re8139_reg = RTK_BMSR; 275 break; 276 case MII_ANAR: 277 re8139_reg = RTK_ANAR; 278 break; 279 case MII_ANER: 280 re8139_reg = RTK_ANER; 281 break; 282 case MII_ANLPAR: 283 re8139_reg = RTK_LPAR; 284 break; 285 case MII_PHYIDR1: 286 case MII_PHYIDR2: 287 splx(s); 288 return 0; 289 /* 290 * Allow the rlphy driver to read the media status 291 * register. If we have a link partner which does not 292 * support NWAY, this is the register which will tell 293 * us the results of parallel detection. 294 */ 295 case RTK_MEDIASTAT: 296 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 297 splx(s); 298 return rval; 299 default: 300 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 301 splx(s); 302 return 0; 303 } 304 rval = CSR_READ_2(sc, re8139_reg); 305 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 306 /* 8139C+ has different bit layout. */ 307 rval &= ~(BMCR_LOOP | BMCR_ISO); 308 } 309 splx(s); 310 return rval; 311 } 312 313 static void 314 re_miibus_writereg(device_t dev, int phy, int reg, int data) 315 { 316 struct rtk_softc *sc = device_private(dev); 317 uint16_t re8139_reg = 0; 318 int s; 319 320 s = splnet(); 321 322 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 323 re_gmii_writereg(dev, phy, reg, data); 324 splx(s); 325 return; 326 } 327 328 /* Pretend the internal PHY is only at address 0 */ 329 if (phy) { 330 splx(s); 331 return; 332 } 333 switch (reg) { 334 case MII_BMCR: 335 re8139_reg = RTK_BMCR; 336 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 337 /* 8139C+ has different bit layout. */ 338 data &= ~(BMCR_LOOP | BMCR_ISO); 339 } 340 break; 341 case MII_BMSR: 342 re8139_reg = RTK_BMSR; 343 break; 344 case MII_ANAR: 345 re8139_reg = RTK_ANAR; 346 break; 347 case MII_ANER: 348 re8139_reg = RTK_ANER; 349 break; 350 case MII_ANLPAR: 351 re8139_reg = RTK_LPAR; 352 break; 353 case MII_PHYIDR1: 354 case MII_PHYIDR2: 355 splx(s); 356 return; 357 break; 358 default: 359 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 360 splx(s); 361 return; 362 } 363 CSR_WRITE_2(sc, re8139_reg, data); 364 splx(s); 365 return; 366 } 367 368 static void 369 re_miibus_statchg(device_t dev) 370 { 371 372 return; 373 } 374 375 static void 376 re_reset(struct rtk_softc *sc) 377 { 378 int i; 379 380 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 381 382 for (i = 0; i < RTK_TIMEOUT; i++) { 383 DELAY(10); 384 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 385 break; 386 } 387 if (i == RTK_TIMEOUT) 388 printf("%s: reset never completed!\n", 389 device_xname(sc->sc_dev)); 390 391 /* 392 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3, 393 * but also says "Rtl8169s sigle chip detected". 394 */ 395 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0) 396 CSR_WRITE_1(sc, RTK_LDPS, 1); 397 398 } 399 400 /* 401 * The following routine is designed to test for a defect on some 402 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 403 * lines connected to the bus, however for a 32-bit only card, they 404 * should be pulled high. The result of this defect is that the 405 * NIC will not work right if you plug it into a 64-bit slot: DMA 406 * operations will be done with 64-bit transfers, which will fail 407 * because the 64-bit data lines aren't connected. 408 * 409 * There's no way to work around this (short of talking a soldering 410 * iron to the board), however we can detect it. The method we use 411 * here is to put the NIC into digital loopback mode, set the receiver 412 * to promiscuous mode, and then try to send a frame. We then compare 413 * the frame data we sent to what was received. If the data matches, 414 * then the NIC is working correctly, otherwise we know the user has 415 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 416 * slot. In the latter case, there's no way the NIC can work correctly, 417 * so we print out a message on the console and abort the device attach. 418 */ 419 420 int 421 re_diag(struct rtk_softc *sc) 422 { 423 struct ifnet *ifp = &sc->ethercom.ec_if; 424 struct mbuf *m0; 425 struct ether_header *eh; 426 struct re_rxsoft *rxs; 427 struct re_desc *cur_rx; 428 bus_dmamap_t dmamap; 429 uint16_t status; 430 uint32_t rxstat; 431 int total_len, i, s, error = 0; 432 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 433 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 434 435 /* Allocate a single mbuf */ 436 437 MGETHDR(m0, M_DONTWAIT, MT_DATA); 438 if (m0 == NULL) 439 return ENOBUFS; 440 441 /* 442 * Initialize the NIC in test mode. This sets the chip up 443 * so that it can send and receive frames, but performs the 444 * following special functions: 445 * - Puts receiver in promiscuous mode 446 * - Enables digital loopback mode 447 * - Leaves interrupts turned off 448 */ 449 450 ifp->if_flags |= IFF_PROMISC; 451 sc->re_testmode = 1; 452 re_init(ifp); 453 re_stop(ifp, 0); 454 DELAY(100000); 455 re_init(ifp); 456 457 /* Put some data in the mbuf */ 458 459 eh = mtod(m0, struct ether_header *); 460 memcpy(eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN); 461 memcpy(eh->ether_shost, (char *)&src, ETHER_ADDR_LEN); 462 eh->ether_type = htons(ETHERTYPE_IP); 463 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 464 465 /* 466 * Queue the packet, start transmission. 467 */ 468 469 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 470 s = splnet(); 471 IF_ENQUEUE(&ifp->if_snd, m0); 472 re_start(ifp); 473 splx(s); 474 m0 = NULL; 475 476 /* Wait for it to propagate through the chip */ 477 478 DELAY(100000); 479 for (i = 0; i < RTK_TIMEOUT; i++) { 480 status = CSR_READ_2(sc, RTK_ISR); 481 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 482 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 483 break; 484 DELAY(10); 485 } 486 if (i == RTK_TIMEOUT) { 487 aprint_error_dev(sc->sc_dev, 488 "diagnostic failed, failed to receive packet " 489 "in loopback mode\n"); 490 error = EIO; 491 goto done; 492 } 493 494 /* 495 * The packet should have been dumped into the first 496 * entry in the RX DMA ring. Grab it from there. 497 */ 498 499 rxs = &sc->re_ldata.re_rxsoft[0]; 500 dmamap = rxs->rxs_dmamap; 501 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 502 BUS_DMASYNC_POSTREAD); 503 bus_dmamap_unload(sc->sc_dmat, dmamap); 504 505 m0 = rxs->rxs_mbuf; 506 rxs->rxs_mbuf = NULL; 507 eh = mtod(m0, struct ether_header *); 508 509 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 510 cur_rx = &sc->re_ldata.re_rx_list[0]; 511 rxstat = le32toh(cur_rx->re_cmdstat); 512 total_len = rxstat & sc->re_rxlenmask; 513 514 if (total_len != ETHER_MIN_LEN) { 515 aprint_error_dev(sc->sc_dev, 516 "diagnostic failed, received short packet\n"); 517 error = EIO; 518 goto done; 519 } 520 521 /* Test that the received packet data matches what we sent. */ 522 523 if (memcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 524 memcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 525 ntohs(eh->ether_type) != ETHERTYPE_IP) { 526 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 527 "expected TX data: %s/%s/0x%x\n" 528 "received RX data: %s/%s/0x%x\n" 529 "You may have a defective 32-bit NIC plugged " 530 "into a 64-bit PCI slot.\n" 531 "Please re-install the NIC in a 32-bit slot " 532 "for proper operation.\n" 533 "Read the re(4) man page for more details.\n" , 534 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 535 ether_sprintf(eh->ether_dhost), 536 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 537 error = EIO; 538 } 539 540 done: 541 /* Turn interface off, release resources */ 542 543 sc->re_testmode = 0; 544 ifp->if_flags &= ~IFF_PROMISC; 545 re_stop(ifp, 0); 546 if (m0 != NULL) 547 m_freem(m0); 548 549 return error; 550 } 551 552 553 /* 554 * Attach the interface. Allocate softc structures, do ifmedia 555 * setup and ethernet/BPF attach. 556 */ 557 void 558 re_attach(struct rtk_softc *sc) 559 { 560 uint8_t eaddr[ETHER_ADDR_LEN]; 561 uint16_t val; 562 struct ifnet *ifp; 563 int error = 0, i, addr_len; 564 565 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 566 uint32_t hwrev; 567 568 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 569 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 570 switch (hwrev) { 571 case RTK_HWREV_8169: 572 sc->sc_quirk |= RTKQ_8169NONS; 573 break; 574 case RTK_HWREV_8169S: 575 case RTK_HWREV_8110S: 576 case RTK_HWREV_8169_8110SB: 577 case RTK_HWREV_8169_8110SC: 578 sc->sc_quirk |= RTKQ_MACLDPS; 579 break; 580 case RTK_HWREV_8168_SPIN1: 581 case RTK_HWREV_8168_SPIN2: 582 case RTK_HWREV_8168_SPIN3: 583 sc->sc_quirk |= RTKQ_MACSTAT; 584 break; 585 case RTK_HWREV_8168C: 586 case RTK_HWREV_8168C_SPIN2: 587 case RTK_HWREV_8168CP: 588 case RTK_HWREV_8168D: 589 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 590 RTKQ_MACSTAT | RTKQ_CMDSTOP; 591 /* 592 * From FreeBSD driver: 593 * 594 * These (8168/8111) controllers support jumbo frame 595 * but it seems that enabling it requires touching 596 * additional magic registers. Depending on MAC 597 * revisions some controllers need to disable 598 * checksum offload. So disable jumbo frame until 599 * I have better idea what it really requires to 600 * make it support. 601 * RTL8168C/CP : supports up to 6KB jumbo frame. 602 * RTL8111C/CP : supports up to 9KB jumbo frame. 603 */ 604 sc->sc_quirk |= RTKQ_NOJUMBO; 605 break; 606 case RTK_HWREV_8100E: 607 case RTK_HWREV_8100E_SPIN2: 608 case RTK_HWREV_8101E: 609 sc->sc_quirk |= RTKQ_NOJUMBO; 610 break; 611 case RTK_HWREV_8102E: 612 case RTK_HWREV_8102EL: 613 case RTK_HWREV_8103E: 614 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 615 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 616 break; 617 default: 618 aprint_normal_dev(sc->sc_dev, 619 "Unknown revision (0x%08x)\n", hwrev); 620 /* assume the latest features */ 621 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 622 sc->sc_quirk |= RTKQ_NOJUMBO; 623 } 624 625 /* Set RX length mask */ 626 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 627 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 628 } else { 629 sc->sc_quirk |= RTKQ_NOJUMBO; 630 631 /* Set RX length mask */ 632 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 633 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 634 } 635 636 /* Reset the adapter. */ 637 re_reset(sc); 638 639 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) { 640 /* 641 * Get station address from ID registers. 642 */ 643 for (i = 0; i < ETHER_ADDR_LEN; i++) 644 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 645 } else { 646 /* 647 * Get station address from the EEPROM. 648 */ 649 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 650 addr_len = RTK_EEADDR_LEN1; 651 else 652 addr_len = RTK_EEADDR_LEN0; 653 654 /* 655 * Get station address from the EEPROM. 656 */ 657 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 658 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 659 eaddr[(i * 2) + 0] = val & 0xff; 660 eaddr[(i * 2) + 1] = val >> 8; 661 } 662 } 663 664 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 665 ether_sprintf(eaddr)); 666 667 if (sc->re_ldata.re_tx_desc_cnt > 668 PAGE_SIZE / sizeof(struct re_desc)) { 669 sc->re_ldata.re_tx_desc_cnt = 670 PAGE_SIZE / sizeof(struct re_desc); 671 } 672 673 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 674 sc->re_ldata.re_tx_desc_cnt); 675 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 676 677 /* Allocate DMA'able memory for the TX ring */ 678 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 679 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 680 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 681 aprint_error_dev(sc->sc_dev, 682 "can't allocate tx listseg, error = %d\n", error); 683 goto fail_0; 684 } 685 686 /* Load the map for the TX ring. */ 687 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 688 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 689 (void **)&sc->re_ldata.re_tx_list, 690 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 691 aprint_error_dev(sc->sc_dev, 692 "can't map tx list, error = %d\n", error); 693 goto fail_1; 694 } 695 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 696 697 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 698 RE_TX_LIST_SZ(sc), 0, 0, 699 &sc->re_ldata.re_tx_list_map)) != 0) { 700 aprint_error_dev(sc->sc_dev, 701 "can't create tx list map, error = %d\n", error); 702 goto fail_2; 703 } 704 705 706 if ((error = bus_dmamap_load(sc->sc_dmat, 707 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 708 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 709 aprint_error_dev(sc->sc_dev, 710 "can't load tx list, error = %d\n", error); 711 goto fail_3; 712 } 713 714 /* Create DMA maps for TX buffers */ 715 for (i = 0; i < RE_TX_QLEN; i++) { 716 error = bus_dmamap_create(sc->sc_dmat, 717 round_page(IP_MAXPACKET), 718 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 719 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 720 if (error) { 721 aprint_error_dev(sc->sc_dev, 722 "can't create DMA map for TX\n"); 723 goto fail_4; 724 } 725 } 726 727 /* Allocate DMA'able memory for the RX ring */ 728 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 729 if ((error = bus_dmamem_alloc(sc->sc_dmat, 730 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 731 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 732 aprint_error_dev(sc->sc_dev, 733 "can't allocate rx listseg, error = %d\n", error); 734 goto fail_4; 735 } 736 737 /* Load the map for the RX ring. */ 738 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 739 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 740 (void **)&sc->re_ldata.re_rx_list, 741 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 742 aprint_error_dev(sc->sc_dev, 743 "can't map rx list, error = %d\n", error); 744 goto fail_5; 745 } 746 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 747 748 if ((error = bus_dmamap_create(sc->sc_dmat, 749 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 750 &sc->re_ldata.re_rx_list_map)) != 0) { 751 aprint_error_dev(sc->sc_dev, 752 "can't create rx list map, error = %d\n", error); 753 goto fail_6; 754 } 755 756 if ((error = bus_dmamap_load(sc->sc_dmat, 757 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 758 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 759 aprint_error_dev(sc->sc_dev, 760 "can't load rx list, error = %d\n", error); 761 goto fail_7; 762 } 763 764 /* Create DMA maps for RX buffers */ 765 for (i = 0; i < RE_RX_DESC_CNT; i++) { 766 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 767 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 768 if (error) { 769 aprint_error_dev(sc->sc_dev, 770 "can't create DMA map for RX\n"); 771 goto fail_8; 772 } 773 } 774 775 /* 776 * Record interface as attached. From here, we should not fail. 777 */ 778 sc->sc_flags |= RTK_ATTACHED; 779 780 ifp = &sc->ethercom.ec_if; 781 ifp->if_softc = sc; 782 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 783 ifp->if_mtu = ETHERMTU; 784 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 785 ifp->if_ioctl = re_ioctl; 786 sc->ethercom.ec_capabilities |= 787 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 788 ifp->if_start = re_start; 789 ifp->if_stop = re_stop; 790 791 /* 792 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 793 * so we have a workaround to handle the bug by padding 794 * such packets manually. 795 */ 796 ifp->if_capabilities |= 797 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 798 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 799 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 800 IFCAP_TSOv4; 801 802 /* 803 * XXX 804 * Still have no idea how to make TSO work on 8168C, 8168CP, 805 * 8102E, 8111C and 8111CP. 806 */ 807 if ((sc->sc_quirk & RTKQ_DESCV2) != 0) 808 ifp->if_capabilities &= ~IFCAP_TSOv4; 809 810 ifp->if_watchdog = re_watchdog; 811 ifp->if_init = re_init; 812 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 813 ifp->if_capenable = ifp->if_capabilities; 814 IFQ_SET_READY(&ifp->if_snd); 815 816 callout_init(&sc->rtk_tick_ch, 0); 817 818 /* Do MII setup */ 819 sc->mii.mii_ifp = ifp; 820 sc->mii.mii_readreg = re_miibus_readreg; 821 sc->mii.mii_writereg = re_miibus_writereg; 822 sc->mii.mii_statchg = re_miibus_statchg; 823 sc->ethercom.ec_mii = &sc->mii; 824 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange, 825 ether_mediastatus); 826 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 827 MII_OFFSET_ANY, 0); 828 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 829 830 /* 831 * Call MI attach routine. 832 */ 833 if_attach(ifp); 834 ether_ifattach(ifp, eaddr); 835 836 return; 837 838 fail_8: 839 /* Destroy DMA maps for RX buffers. */ 840 for (i = 0; i < RE_RX_DESC_CNT; i++) 841 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 842 bus_dmamap_destroy(sc->sc_dmat, 843 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 844 845 /* Free DMA'able memory for the RX ring. */ 846 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 847 fail_7: 848 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 849 fail_6: 850 bus_dmamem_unmap(sc->sc_dmat, 851 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 852 fail_5: 853 bus_dmamem_free(sc->sc_dmat, 854 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 855 856 fail_4: 857 /* Destroy DMA maps for TX buffers. */ 858 for (i = 0; i < RE_TX_QLEN; i++) 859 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 860 bus_dmamap_destroy(sc->sc_dmat, 861 sc->re_ldata.re_txq[i].txq_dmamap); 862 863 /* Free DMA'able memory for the TX ring. */ 864 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 865 fail_3: 866 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 867 fail_2: 868 bus_dmamem_unmap(sc->sc_dmat, 869 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 870 fail_1: 871 bus_dmamem_free(sc->sc_dmat, 872 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 873 fail_0: 874 return; 875 } 876 877 878 /* 879 * re_activate: 880 * Handle device activation/deactivation requests. 881 */ 882 int 883 re_activate(device_t self, enum devact act) 884 { 885 struct rtk_softc *sc = device_private(self); 886 int s, error = 0; 887 888 s = splnet(); 889 switch (act) { 890 case DVACT_ACTIVATE: 891 error = EOPNOTSUPP; 892 break; 893 case DVACT_DEACTIVATE: 894 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 895 if_deactivate(&sc->ethercom.ec_if); 896 break; 897 } 898 splx(s); 899 900 return error; 901 } 902 903 /* 904 * re_detach: 905 * Detach a rtk interface. 906 */ 907 int 908 re_detach(struct rtk_softc *sc) 909 { 910 struct ifnet *ifp = &sc->ethercom.ec_if; 911 int i; 912 913 /* 914 * Succeed now if there isn't any work to do. 915 */ 916 if ((sc->sc_flags & RTK_ATTACHED) == 0) 917 return 0; 918 919 /* Unhook our tick handler. */ 920 callout_stop(&sc->rtk_tick_ch); 921 922 /* Detach all PHYs. */ 923 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 924 925 /* Delete all remaining media. */ 926 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 927 928 ether_ifdetach(ifp); 929 if_detach(ifp); 930 931 /* Destroy DMA maps for RX buffers. */ 932 for (i = 0; i < RE_RX_DESC_CNT; i++) 933 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 934 bus_dmamap_destroy(sc->sc_dmat, 935 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 936 937 /* Free DMA'able memory for the RX ring. */ 938 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 939 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 940 bus_dmamem_unmap(sc->sc_dmat, 941 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 942 bus_dmamem_free(sc->sc_dmat, 943 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 944 945 /* Destroy DMA maps for TX buffers. */ 946 for (i = 0; i < RE_TX_QLEN; i++) 947 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 948 bus_dmamap_destroy(sc->sc_dmat, 949 sc->re_ldata.re_txq[i].txq_dmamap); 950 951 /* Free DMA'able memory for the TX ring. */ 952 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 953 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 954 bus_dmamem_unmap(sc->sc_dmat, 955 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 956 bus_dmamem_free(sc->sc_dmat, 957 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 958 959 return 0; 960 } 961 962 /* 963 * re_enable: 964 * Enable the RTL81X9 chip. 965 */ 966 static int 967 re_enable(struct rtk_softc *sc) 968 { 969 970 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 971 if ((*sc->sc_enable)(sc) != 0) { 972 printf("%s: device enable failed\n", 973 device_xname(sc->sc_dev)); 974 return EIO; 975 } 976 sc->sc_flags |= RTK_ENABLED; 977 } 978 return 0; 979 } 980 981 /* 982 * re_disable: 983 * Disable the RTL81X9 chip. 984 */ 985 static void 986 re_disable(struct rtk_softc *sc) 987 { 988 989 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 990 (*sc->sc_disable)(sc); 991 sc->sc_flags &= ~RTK_ENABLED; 992 } 993 } 994 995 static int 996 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 997 { 998 struct mbuf *n = NULL; 999 bus_dmamap_t map; 1000 struct re_desc *d; 1001 struct re_rxsoft *rxs; 1002 uint32_t cmdstat; 1003 int error; 1004 1005 if (m == NULL) { 1006 MGETHDR(n, M_DONTWAIT, MT_DATA); 1007 if (n == NULL) 1008 return ENOBUFS; 1009 1010 MCLGET(n, M_DONTWAIT); 1011 if ((n->m_flags & M_EXT) == 0) { 1012 m_freem(n); 1013 return ENOBUFS; 1014 } 1015 m = n; 1016 } else 1017 m->m_data = m->m_ext.ext_buf; 1018 1019 /* 1020 * Initialize mbuf length fields and fixup 1021 * alignment so that the frame payload is 1022 * longword aligned. 1023 */ 1024 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1025 m->m_data += RE_ETHER_ALIGN; 1026 1027 rxs = &sc->re_ldata.re_rxsoft[idx]; 1028 map = rxs->rxs_dmamap; 1029 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1030 BUS_DMA_READ|BUS_DMA_NOWAIT); 1031 1032 if (error) 1033 goto out; 1034 1035 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1036 BUS_DMASYNC_PREREAD); 1037 1038 d = &sc->re_ldata.re_rx_list[idx]; 1039 #ifdef DIAGNOSTIC 1040 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1041 cmdstat = le32toh(d->re_cmdstat); 1042 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1043 if (cmdstat & RE_RDESC_STAT_OWN) { 1044 panic("%s: tried to map busy RX descriptor", 1045 device_xname(sc->sc_dev)); 1046 } 1047 #endif 1048 1049 rxs->rxs_mbuf = m; 1050 1051 d->re_vlanctl = 0; 1052 cmdstat = map->dm_segs[0].ds_len; 1053 if (idx == (RE_RX_DESC_CNT - 1)) 1054 cmdstat |= RE_RDESC_CMD_EOR; 1055 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1056 d->re_cmdstat = htole32(cmdstat); 1057 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1058 cmdstat |= RE_RDESC_CMD_OWN; 1059 d->re_cmdstat = htole32(cmdstat); 1060 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1061 1062 return 0; 1063 out: 1064 if (n != NULL) 1065 m_freem(n); 1066 return ENOMEM; 1067 } 1068 1069 static int 1070 re_tx_list_init(struct rtk_softc *sc) 1071 { 1072 int i; 1073 1074 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1075 for (i = 0; i < RE_TX_QLEN; i++) { 1076 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1077 } 1078 1079 bus_dmamap_sync(sc->sc_dmat, 1080 sc->re_ldata.re_tx_list_map, 0, 1081 sc->re_ldata.re_tx_list_map->dm_mapsize, 1082 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1083 sc->re_ldata.re_txq_prodidx = 0; 1084 sc->re_ldata.re_txq_considx = 0; 1085 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1086 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1087 sc->re_ldata.re_tx_nextfree = 0; 1088 1089 return 0; 1090 } 1091 1092 static int 1093 re_rx_list_init(struct rtk_softc *sc) 1094 { 1095 int i; 1096 1097 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1098 1099 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1100 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1101 return ENOBUFS; 1102 } 1103 1104 sc->re_ldata.re_rx_prodidx = 0; 1105 sc->re_head = sc->re_tail = NULL; 1106 1107 return 0; 1108 } 1109 1110 /* 1111 * RX handler for C+ and 8169. For the gigE chips, we support 1112 * the reception of jumbo frames that have been fragmented 1113 * across multiple 2K mbuf cluster buffers. 1114 */ 1115 static void 1116 re_rxeof(struct rtk_softc *sc) 1117 { 1118 struct mbuf *m; 1119 struct ifnet *ifp; 1120 int i, total_len; 1121 struct re_desc *cur_rx; 1122 struct re_rxsoft *rxs; 1123 uint32_t rxstat, rxvlan; 1124 1125 ifp = &sc->ethercom.ec_if; 1126 1127 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1128 cur_rx = &sc->re_ldata.re_rx_list[i]; 1129 RE_RXDESCSYNC(sc, i, 1130 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1131 rxstat = le32toh(cur_rx->re_cmdstat); 1132 rxvlan = le32toh(cur_rx->re_vlanctl); 1133 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1134 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1135 break; 1136 } 1137 total_len = rxstat & sc->re_rxlenmask; 1138 rxs = &sc->re_ldata.re_rxsoft[i]; 1139 m = rxs->rxs_mbuf; 1140 1141 /* Invalidate the RX mbuf and unload its map */ 1142 1143 bus_dmamap_sync(sc->sc_dmat, 1144 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1145 BUS_DMASYNC_POSTREAD); 1146 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1147 1148 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1149 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1150 if (sc->re_head == NULL) 1151 sc->re_head = sc->re_tail = m; 1152 else { 1153 m->m_flags &= ~M_PKTHDR; 1154 sc->re_tail->m_next = m; 1155 sc->re_tail = m; 1156 } 1157 re_newbuf(sc, i, NULL); 1158 continue; 1159 } 1160 1161 /* 1162 * NOTE: for the 8139C+, the frame length field 1163 * is always 12 bits in size, but for the gigE chips, 1164 * it is 13 bits (since the max RX frame length is 16K). 1165 * Unfortunately, all 32 bits in the status word 1166 * were already used, so to make room for the extra 1167 * length bit, RealTek took out the 'frame alignment 1168 * error' bit and shifted the other status bits 1169 * over one slot. The OWN, EOR, FS and LS bits are 1170 * still in the same places. We have already extracted 1171 * the frame length and checked the OWN bit, so rather 1172 * than using an alternate bit mapping, we shift the 1173 * status bits one space to the right so we can evaluate 1174 * them using the 8169 status as though it was in the 1175 * same format as that of the 8139C+. 1176 */ 1177 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1178 rxstat >>= 1; 1179 1180 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1181 #ifdef RE_DEBUG 1182 printf("%s: RX error (rxstat = 0x%08x)", 1183 device_xname(sc->sc_dev), rxstat); 1184 if (rxstat & RE_RDESC_STAT_FRALIGN) 1185 printf(", frame alignment error"); 1186 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1187 printf(", out of buffer space"); 1188 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1189 printf(", FIFO overrun"); 1190 if (rxstat & RE_RDESC_STAT_GIANT) 1191 printf(", giant packet"); 1192 if (rxstat & RE_RDESC_STAT_RUNT) 1193 printf(", runt packet"); 1194 if (rxstat & RE_RDESC_STAT_CRCERR) 1195 printf(", CRC error"); 1196 printf("\n"); 1197 #endif 1198 ifp->if_ierrors++; 1199 /* 1200 * If this is part of a multi-fragment packet, 1201 * discard all the pieces. 1202 */ 1203 if (sc->re_head != NULL) { 1204 m_freem(sc->re_head); 1205 sc->re_head = sc->re_tail = NULL; 1206 } 1207 re_newbuf(sc, i, m); 1208 continue; 1209 } 1210 1211 /* 1212 * If allocating a replacement mbuf fails, 1213 * reload the current one. 1214 */ 1215 1216 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1217 ifp->if_ierrors++; 1218 if (sc->re_head != NULL) { 1219 m_freem(sc->re_head); 1220 sc->re_head = sc->re_tail = NULL; 1221 } 1222 re_newbuf(sc, i, m); 1223 continue; 1224 } 1225 1226 if (sc->re_head != NULL) { 1227 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1228 /* 1229 * Special case: if there's 4 bytes or less 1230 * in this buffer, the mbuf can be discarded: 1231 * the last 4 bytes is the CRC, which we don't 1232 * care about anyway. 1233 */ 1234 if (m->m_len <= ETHER_CRC_LEN) { 1235 sc->re_tail->m_len -= 1236 (ETHER_CRC_LEN - m->m_len); 1237 m_freem(m); 1238 } else { 1239 m->m_len -= ETHER_CRC_LEN; 1240 m->m_flags &= ~M_PKTHDR; 1241 sc->re_tail->m_next = m; 1242 } 1243 m = sc->re_head; 1244 sc->re_head = sc->re_tail = NULL; 1245 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1246 } else 1247 m->m_pkthdr.len = m->m_len = 1248 (total_len - ETHER_CRC_LEN); 1249 1250 ifp->if_ipackets++; 1251 m->m_pkthdr.rcvif = ifp; 1252 1253 /* Do RX checksumming */ 1254 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1255 /* Check IP header checksum */ 1256 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) { 1257 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1258 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1259 m->m_pkthdr.csum_flags |= 1260 M_CSUM_IPv4_BAD; 1261 1262 /* Check TCP/UDP checksum */ 1263 if (RE_TCPPKT(rxstat)) { 1264 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1265 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1266 m->m_pkthdr.csum_flags |= 1267 M_CSUM_TCP_UDP_BAD; 1268 } else if (RE_UDPPKT(rxstat)) { 1269 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1270 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1271 m->m_pkthdr.csum_flags |= 1272 M_CSUM_TCP_UDP_BAD; 1273 } 1274 } 1275 } else { 1276 /* Check IPv4 header checksum */ 1277 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) { 1278 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1279 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1280 m->m_pkthdr.csum_flags |= 1281 M_CSUM_IPv4_BAD; 1282 1283 /* Check TCPv4/UDPv4 checksum */ 1284 if (RE_TCPPKT(rxstat)) { 1285 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1286 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1287 m->m_pkthdr.csum_flags |= 1288 M_CSUM_TCP_UDP_BAD; 1289 } else if (RE_UDPPKT(rxstat)) { 1290 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1291 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1292 m->m_pkthdr.csum_flags |= 1293 M_CSUM_TCP_UDP_BAD; 1294 } 1295 } 1296 /* XXX Check TCPv6/UDPv6 checksum? */ 1297 } 1298 1299 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1300 VLAN_INPUT_TAG(ifp, m, 1301 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA), 1302 continue); 1303 } 1304 #if NBPFILTER > 0 1305 if (ifp->if_bpf) 1306 bpf_mtap(ifp->if_bpf, m); 1307 #endif 1308 (*ifp->if_input)(ifp, m); 1309 } 1310 1311 sc->re_ldata.re_rx_prodidx = i; 1312 } 1313 1314 static void 1315 re_txeof(struct rtk_softc *sc) 1316 { 1317 struct ifnet *ifp; 1318 struct re_txq *txq; 1319 uint32_t txstat; 1320 int idx, descidx; 1321 1322 ifp = &sc->ethercom.ec_if; 1323 1324 for (idx = sc->re_ldata.re_txq_considx; 1325 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1326 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1327 txq = &sc->re_ldata.re_txq[idx]; 1328 KASSERT(txq->txq_mbuf != NULL); 1329 1330 descidx = txq->txq_descidx; 1331 RE_TXDESCSYNC(sc, descidx, 1332 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1333 txstat = 1334 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1335 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1336 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1337 if (txstat & RE_TDESC_CMD_OWN) { 1338 break; 1339 } 1340 1341 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1342 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1343 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1344 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1345 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1346 m_freem(txq->txq_mbuf); 1347 txq->txq_mbuf = NULL; 1348 1349 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1350 ifp->if_collisions++; 1351 if (txstat & RE_TDESC_STAT_TXERRSUM) 1352 ifp->if_oerrors++; 1353 else 1354 ifp->if_opackets++; 1355 } 1356 1357 sc->re_ldata.re_txq_considx = idx; 1358 1359 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1360 ifp->if_flags &= ~IFF_OACTIVE; 1361 1362 /* 1363 * If not all descriptors have been released reaped yet, 1364 * reload the timer so that we will eventually get another 1365 * interrupt that will cause us to re-enter this routine. 1366 * This is done in case the transmitter has gone idle. 1367 */ 1368 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1369 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1370 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1371 /* 1372 * Some chips will ignore a second TX request 1373 * issued while an existing transmission is in 1374 * progress. If the transmitter goes idle but 1375 * there are still packets waiting to be sent, 1376 * we need to restart the channel here to flush 1377 * them out. This only seems to be required with 1378 * the PCIe devices. 1379 */ 1380 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1381 } 1382 } else 1383 ifp->if_timer = 0; 1384 } 1385 1386 static void 1387 re_tick(void *arg) 1388 { 1389 struct rtk_softc *sc = arg; 1390 int s; 1391 1392 /*XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1393 s = splnet(); 1394 1395 mii_tick(&sc->mii); 1396 splx(s); 1397 1398 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1399 } 1400 1401 int 1402 re_intr(void *arg) 1403 { 1404 struct rtk_softc *sc = arg; 1405 struct ifnet *ifp; 1406 uint16_t status; 1407 int handled = 0; 1408 1409 if (!device_has_power(sc->sc_dev)) 1410 return 0; 1411 1412 ifp = &sc->ethercom.ec_if; 1413 1414 if ((ifp->if_flags & IFF_UP) == 0) 1415 return 0; 1416 1417 for (;;) { 1418 1419 status = CSR_READ_2(sc, RTK_ISR); 1420 /* If the card has gone away the read returns 0xffff. */ 1421 if (status == 0xffff) 1422 break; 1423 if (status) { 1424 handled = 1; 1425 CSR_WRITE_2(sc, RTK_ISR, status); 1426 } 1427 1428 if ((status & RTK_INTRS_CPLUS) == 0) 1429 break; 1430 1431 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1432 re_rxeof(sc); 1433 1434 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1435 RTK_ISR_TX_DESC_UNAVAIL)) 1436 re_txeof(sc); 1437 1438 if (status & RTK_ISR_SYSTEM_ERR) { 1439 re_init(ifp); 1440 } 1441 1442 if (status & RTK_ISR_LINKCHG) { 1443 callout_stop(&sc->rtk_tick_ch); 1444 re_tick(sc); 1445 } 1446 } 1447 1448 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd)) 1449 re_start(ifp); 1450 1451 return handled; 1452 } 1453 1454 1455 1456 /* 1457 * Main transmit routine for C+ and gigE NICs. 1458 */ 1459 1460 static void 1461 re_start(struct ifnet *ifp) 1462 { 1463 struct rtk_softc *sc; 1464 struct mbuf *m; 1465 bus_dmamap_t map; 1466 struct re_txq *txq; 1467 struct re_desc *d; 1468 struct m_tag *mtag; 1469 uint32_t cmdstat, re_flags, vlanctl; 1470 int ofree, idx, error, nsegs, seg; 1471 int startdesc, curdesc, lastdesc; 1472 bool pad; 1473 1474 sc = ifp->if_softc; 1475 ofree = sc->re_ldata.re_txq_free; 1476 1477 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1478 1479 IFQ_POLL(&ifp->if_snd, m); 1480 if (m == NULL) 1481 break; 1482 1483 if (sc->re_ldata.re_txq_free == 0 || 1484 sc->re_ldata.re_tx_free == 0) { 1485 /* no more free slots left */ 1486 ifp->if_flags |= IFF_OACTIVE; 1487 break; 1488 } 1489 1490 /* 1491 * Set up checksum offload. Note: checksum offload bits must 1492 * appear in all descriptors of a multi-descriptor transmit 1493 * attempt. (This is according to testing done with an 8169 1494 * chip. I'm not sure if this is a requirement or a bug.) 1495 */ 1496 1497 vlanctl = 0; 1498 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1499 uint32_t segsz = m->m_pkthdr.segsz; 1500 1501 re_flags = RE_TDESC_CMD_LGSEND | 1502 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1503 } else { 1504 /* 1505 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1506 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1507 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1508 */ 1509 re_flags = 0; 1510 if ((m->m_pkthdr.csum_flags & 1511 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1512 != 0) { 1513 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1514 re_flags |= RE_TDESC_CMD_IPCSUM; 1515 if (m->m_pkthdr.csum_flags & 1516 M_CSUM_TCPv4) { 1517 re_flags |= 1518 RE_TDESC_CMD_TCPCSUM; 1519 } else if (m->m_pkthdr.csum_flags & 1520 M_CSUM_UDPv4) { 1521 re_flags |= 1522 RE_TDESC_CMD_UDPCSUM; 1523 } 1524 } else { 1525 vlanctl |= RE_TDESC_VLANCTL_IPCSUM; 1526 if (m->m_pkthdr.csum_flags & 1527 M_CSUM_TCPv4) { 1528 vlanctl |= 1529 RE_TDESC_VLANCTL_TCPCSUM; 1530 } else if (m->m_pkthdr.csum_flags & 1531 M_CSUM_UDPv4) { 1532 vlanctl |= 1533 RE_TDESC_VLANCTL_UDPCSUM; 1534 } 1535 } 1536 } 1537 } 1538 1539 txq = &sc->re_ldata.re_txq[idx]; 1540 map = txq->txq_dmamap; 1541 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1542 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1543 1544 if (__predict_false(error)) { 1545 /* XXX try to defrag if EFBIG? */ 1546 printf("%s: can't map mbuf (error %d)\n", 1547 device_xname(sc->sc_dev), error); 1548 1549 IFQ_DEQUEUE(&ifp->if_snd, m); 1550 m_freem(m); 1551 ifp->if_oerrors++; 1552 continue; 1553 } 1554 1555 nsegs = map->dm_nsegs; 1556 pad = false; 1557 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1558 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 && 1559 (sc->sc_quirk & RTKQ_DESCV2) == 0)) { 1560 pad = true; 1561 nsegs++; 1562 } 1563 1564 if (nsegs > sc->re_ldata.re_tx_free) { 1565 /* 1566 * Not enough free descriptors to transmit this packet. 1567 */ 1568 ifp->if_flags |= IFF_OACTIVE; 1569 bus_dmamap_unload(sc->sc_dmat, map); 1570 break; 1571 } 1572 1573 IFQ_DEQUEUE(&ifp->if_snd, m); 1574 1575 /* 1576 * Make sure that the caches are synchronized before we 1577 * ask the chip to start DMA for the packet data. 1578 */ 1579 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1580 BUS_DMASYNC_PREWRITE); 1581 1582 /* 1583 * Set up hardware VLAN tagging. Note: vlan tag info must 1584 * appear in all descriptors of a multi-descriptor 1585 * transmission attempt. 1586 */ 1587 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) 1588 vlanctl |= bswap16(VLAN_TAG_VALUE(mtag)) | 1589 RE_TDESC_VLANCTL_TAG; 1590 1591 /* 1592 * Map the segment array into descriptors. 1593 * Note that we set the start-of-frame and 1594 * end-of-frame markers for either TX or RX, 1595 * but they really only have meaning in the TX case. 1596 * (In the RX case, it's the chip that tells us 1597 * where packets begin and end.) 1598 * We also keep track of the end of the ring 1599 * and set the end-of-ring bits as needed, 1600 * and we set the ownership bits in all except 1601 * the very first descriptor. (The caller will 1602 * set this descriptor later when it start 1603 * transmission or reception.) 1604 */ 1605 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1606 lastdesc = -1; 1607 for (seg = 0; seg < map->dm_nsegs; 1608 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1609 d = &sc->re_ldata.re_tx_list[curdesc]; 1610 #ifdef DIAGNOSTIC 1611 RE_TXDESCSYNC(sc, curdesc, 1612 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1613 cmdstat = le32toh(d->re_cmdstat); 1614 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1615 if (cmdstat & RE_TDESC_STAT_OWN) { 1616 panic("%s: tried to map busy TX descriptor", 1617 device_xname(sc->sc_dev)); 1618 } 1619 #endif 1620 1621 d->re_vlanctl = htole32(vlanctl); 1622 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1623 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1624 if (seg == 0) 1625 cmdstat |= RE_TDESC_CMD_SOF; 1626 else 1627 cmdstat |= RE_TDESC_CMD_OWN; 1628 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1629 cmdstat |= RE_TDESC_CMD_EOR; 1630 if (seg == nsegs - 1) { 1631 cmdstat |= RE_TDESC_CMD_EOF; 1632 lastdesc = curdesc; 1633 } 1634 d->re_cmdstat = htole32(cmdstat); 1635 RE_TXDESCSYNC(sc, curdesc, 1636 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1637 } 1638 if (__predict_false(pad)) { 1639 bus_addr_t paddaddr; 1640 1641 d = &sc->re_ldata.re_tx_list[curdesc]; 1642 d->re_vlanctl = htole32(vlanctl); 1643 paddaddr = RE_TXPADDADDR(sc); 1644 re_set_bufaddr(d, paddaddr); 1645 cmdstat = re_flags | 1646 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1647 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1648 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1649 cmdstat |= RE_TDESC_CMD_EOR; 1650 d->re_cmdstat = htole32(cmdstat); 1651 RE_TXDESCSYNC(sc, curdesc, 1652 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1653 lastdesc = curdesc; 1654 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1655 } 1656 KASSERT(lastdesc != -1); 1657 1658 /* Transfer ownership of packet to the chip. */ 1659 1660 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1661 htole32(RE_TDESC_CMD_OWN); 1662 RE_TXDESCSYNC(sc, startdesc, 1663 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1664 1665 /* update info of TX queue and descriptors */ 1666 txq->txq_mbuf = m; 1667 txq->txq_descidx = lastdesc; 1668 txq->txq_nsegs = nsegs; 1669 1670 sc->re_ldata.re_txq_free--; 1671 sc->re_ldata.re_tx_free -= nsegs; 1672 sc->re_ldata.re_tx_nextfree = curdesc; 1673 1674 #if NBPFILTER > 0 1675 /* 1676 * If there's a BPF listener, bounce a copy of this frame 1677 * to him. 1678 */ 1679 if (ifp->if_bpf) 1680 bpf_mtap(ifp->if_bpf, m); 1681 #endif 1682 } 1683 1684 if (sc->re_ldata.re_txq_free < ofree) { 1685 /* 1686 * TX packets are enqueued. 1687 */ 1688 sc->re_ldata.re_txq_prodidx = idx; 1689 1690 /* 1691 * Start the transmitter to poll. 1692 * 1693 * RealTek put the TX poll request register in a different 1694 * location on the 8169 gigE chip. I don't know why. 1695 */ 1696 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1697 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1698 else 1699 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1700 1701 /* 1702 * Use the countdown timer for interrupt moderation. 1703 * 'TX done' interrupts are disabled. Instead, we reset the 1704 * countdown timer, which will begin counting until it hits 1705 * the value in the TIMERINT register, and then trigger an 1706 * interrupt. Each time we write to the TIMERCNT register, 1707 * the timer count is reset to 0. 1708 */ 1709 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1710 1711 /* 1712 * Set a timeout in case the chip goes out to lunch. 1713 */ 1714 ifp->if_timer = 5; 1715 } 1716 } 1717 1718 static int 1719 re_init(struct ifnet *ifp) 1720 { 1721 struct rtk_softc *sc = ifp->if_softc; 1722 const uint8_t *enaddr; 1723 uint32_t rxcfg = 0; 1724 uint32_t reg; 1725 uint16_t cfg; 1726 int error; 1727 1728 if ((error = re_enable(sc)) != 0) 1729 goto out; 1730 1731 /* 1732 * Cancel pending I/O and free all RX/TX buffers. 1733 */ 1734 re_stop(ifp, 0); 1735 1736 re_reset(sc); 1737 1738 /* 1739 * Enable C+ RX and TX mode, as well as VLAN stripping and 1740 * RX checksum offload. We must configure the C+ register 1741 * before all others. 1742 */ 1743 cfg = RE_CPLUSCMD_PCI_MRW; 1744 1745 /* 1746 * XXX: For old 8169 set bit 14. 1747 * For 8169S/8110S and above, do not set bit 14. 1748 */ 1749 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1750 cfg |= (0x1 << 14); 1751 1752 if ((ifp->if_capenable & ETHERCAP_VLAN_HWTAGGING) != 0) 1753 cfg |= RE_CPLUSCMD_VLANSTRIP; 1754 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx | 1755 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0) 1756 cfg |= RE_CPLUSCMD_RXCSUM_ENB; 1757 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) { 1758 cfg |= RE_CPLUSCMD_MACSTAT_DIS; 1759 cfg |= RE_CPLUSCMD_TXENB; 1760 } else 1761 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB; 1762 1763 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg); 1764 1765 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1766 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1767 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1768 1769 DELAY(10000); 1770 1771 /* 1772 * Init our MAC address. Even though the chipset 1773 * documentation doesn't mention it, we need to enter "Config 1774 * register write enable" mode to modify the ID registers. 1775 */ 1776 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1777 enaddr = CLLADDR(ifp->if_sadl); 1778 reg = enaddr[0] | (enaddr[1] << 8) | 1779 (enaddr[2] << 16) | (enaddr[3] << 24); 1780 CSR_WRITE_4(sc, RTK_IDR0, reg); 1781 reg = enaddr[4] | (enaddr[5] << 8); 1782 CSR_WRITE_4(sc, RTK_IDR4, reg); 1783 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1784 1785 /* 1786 * For C+ mode, initialize the RX descriptors and mbufs. 1787 */ 1788 re_rx_list_init(sc); 1789 re_tx_list_init(sc); 1790 1791 /* 1792 * Load the addresses of the RX and TX lists into the chip. 1793 */ 1794 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1795 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1796 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1797 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1798 1799 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1800 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1801 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1802 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1803 1804 /* 1805 * Enable transmit and receive. 1806 */ 1807 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1808 1809 /* 1810 * Set the initial TX and RX configuration. 1811 */ 1812 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1813 /* test mode is needed only for old 8169 */ 1814 CSR_WRITE_4(sc, RTK_TXCFG, 1815 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1816 } else 1817 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1818 1819 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1820 1821 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1822 1823 /* Set the individual bit to receive frames for this host only. */ 1824 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1825 rxcfg |= RTK_RXCFG_RX_INDIV; 1826 1827 /* If we want promiscuous mode, set the allframes bit. */ 1828 if (ifp->if_flags & IFF_PROMISC) 1829 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1830 else 1831 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1832 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1833 1834 /* 1835 * Set capture broadcast bit to capture broadcast frames. 1836 */ 1837 if (ifp->if_flags & IFF_BROADCAST) 1838 rxcfg |= RTK_RXCFG_RX_BROAD; 1839 else 1840 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1841 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1842 1843 /* 1844 * Program the multicast filter, if necessary. 1845 */ 1846 rtk_setmulti(sc); 1847 1848 /* 1849 * Enable interrupts. 1850 */ 1851 if (sc->re_testmode) 1852 CSR_WRITE_2(sc, RTK_IMR, 0); 1853 else 1854 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1855 1856 /* Start RX/TX process. */ 1857 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1858 #ifdef notdef 1859 /* Enable receiver and transmitter. */ 1860 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1861 #endif 1862 1863 /* 1864 * Initialize the timer interrupt register so that 1865 * a timer interrupt will be generated once the timer 1866 * reaches a certain number of ticks. The timer is 1867 * reloaded on each transmit. This gives us TX interrupt 1868 * moderation, which dramatically improves TX frame rate. 1869 */ 1870 1871 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1872 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1873 else { 1874 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1875 1876 /* 1877 * For 8169 gigE NICs, set the max allowed RX packet 1878 * size so we can receive jumbo frames. 1879 */ 1880 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1881 } 1882 1883 if (sc->re_testmode) 1884 return 0; 1885 1886 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 1887 1888 ifp->if_flags |= IFF_RUNNING; 1889 ifp->if_flags &= ~IFF_OACTIVE; 1890 1891 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1892 1893 out: 1894 if (error) { 1895 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1896 ifp->if_timer = 0; 1897 printf("%s: interface not running\n", 1898 device_xname(sc->sc_dev)); 1899 } 1900 1901 return error; 1902 } 1903 1904 static int 1905 re_ioctl(struct ifnet *ifp, u_long command, void *data) 1906 { 1907 struct rtk_softc *sc = ifp->if_softc; 1908 struct ifreq *ifr = data; 1909 int s, error = 0; 1910 1911 s = splnet(); 1912 1913 switch (command) { 1914 case SIOCSIFMTU: 1915 /* 1916 * Disable jumbo frames if it's not supported. 1917 */ 1918 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 && 1919 ifr->ifr_mtu > ETHERMTU) { 1920 error = EINVAL; 1921 break; 1922 } 1923 1924 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 1925 error = EINVAL; 1926 else if ((error = ifioctl_common(ifp, command, data)) == 1927 ENETRESET) 1928 error = 0; 1929 break; 1930 default: 1931 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1932 break; 1933 1934 error = 0; 1935 1936 if (command == SIOCSIFCAP) 1937 error = (*ifp->if_init)(ifp); 1938 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1939 ; 1940 else if (ifp->if_flags & IFF_RUNNING) 1941 rtk_setmulti(sc); 1942 break; 1943 } 1944 1945 splx(s); 1946 1947 return error; 1948 } 1949 1950 static void 1951 re_watchdog(struct ifnet *ifp) 1952 { 1953 struct rtk_softc *sc; 1954 int s; 1955 1956 sc = ifp->if_softc; 1957 s = splnet(); 1958 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1959 ifp->if_oerrors++; 1960 1961 re_txeof(sc); 1962 re_rxeof(sc); 1963 1964 re_init(ifp); 1965 1966 splx(s); 1967 } 1968 1969 /* 1970 * Stop the adapter and free any mbufs allocated to the 1971 * RX and TX lists. 1972 */ 1973 static void 1974 re_stop(struct ifnet *ifp, int disable) 1975 { 1976 int i; 1977 struct rtk_softc *sc = ifp->if_softc; 1978 1979 callout_stop(&sc->rtk_tick_ch); 1980 1981 mii_down(&sc->mii); 1982 1983 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0) 1984 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB | 1985 RTK_CMD_RX_ENB); 1986 else 1987 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1988 DELAY(1000); 1989 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1990 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 1991 1992 if (sc->re_head != NULL) { 1993 m_freem(sc->re_head); 1994 sc->re_head = sc->re_tail = NULL; 1995 } 1996 1997 /* Free the TX list buffers. */ 1998 for (i = 0; i < RE_TX_QLEN; i++) { 1999 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 2000 bus_dmamap_unload(sc->sc_dmat, 2001 sc->re_ldata.re_txq[i].txq_dmamap); 2002 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 2003 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 2004 } 2005 } 2006 2007 /* Free the RX list buffers. */ 2008 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2009 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 2010 bus_dmamap_unload(sc->sc_dmat, 2011 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 2012 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 2013 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 2014 } 2015 } 2016 2017 if (disable) 2018 re_disable(sc); 2019 2020 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2021 ifp->if_timer = 0; 2022 }
Cache object: 53c8546d6b1fc428d7bc8c013348b99f
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