FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/rtl8169.c
1 /* $NetBSD: rtl8169.c,v 1.175 2022/09/25 18:43:32 thorpej Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998-2003
5 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 #include <sys/cdefs.h>
36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.175 2022/09/25 18:43:32 thorpej Exp $");
37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */
38
39 /*
40 * RealTek 8139C+/8169/8169S/8168/8110S PCI NIC driver
41 *
42 * Written by Bill Paul <wpaul@windriver.com>
43 * Senior Networking Software Engineer
44 * Wind River Systems
45 */
46
47 /*
48 * This driver is designed to support RealTek's next generation of
49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
50 * six devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
51 * RTL8110S, the RTL8168 and the RTL8111.
52 *
53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
54 * with the older 8139 family, however it also supports a special
55 * C+ mode of operation that provides several new performance enhancing
56 * features. These include:
57 *
58 * o Descriptor based DMA mechanism. Each descriptor represents
59 * a single packet fragment. Data buffers may be aligned on
60 * any byte boundary.
61 *
62 * o 64-bit DMA
63 *
64 * o TCP/IP checksum offload for both RX and TX
65 *
66 * o High and normal priority transmit DMA rings
67 *
68 * o VLAN tag insertion and extraction
69 *
70 * o TCP large send (segmentation offload)
71 *
72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
73 * programming API is fairly straightforward. The RX filtering, EEPROM
74 * access and PHY access is the same as it is on the older 8139 series
75 * chips.
76 *
77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
78 * same programming API and feature set as the 8139C+ with the following
79 * differences and additions:
80 *
81 * o 1000Mbps mode
82 *
83 * o Jumbo frames
84 *
85 * o GMII and TBI ports/registers for interfacing with copper
86 * or fiber PHYs
87 *
88 * o RX and TX DMA rings can have up to 1024 descriptors
89 * (the 8139C+ allows a maximum of 64)
90 *
91 * o Slight differences in register layout from the 8139C+
92 *
93 * The TX start and timer interrupt registers are at different locations
94 * on the 8169 than they are on the 8139C+. Also, the status word in the
95 * RX descriptor has a slightly different bit layout. The 8169 does not
96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
97 * copper gigE PHY.
98 *
99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
100 * (the 'S' stands for 'single-chip'). These devices have the same
101 * programming API as the older 8169, but also have some vendor-specific
102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
104 *
105 * This driver takes advantage of the RX and TX checksum offload and
106 * VLAN tag insertion/extraction features. It also implements TX
107 * interrupt moderation using the timer interrupt registers, which
108 * significantly reduces TX interrupt load. There is also support
109 * for jumbo frames, however the 8169/8169S/8110S can not transmit
110 * jumbo frames larger than 7.5K, so the max MTU possible with this
111 * driver is 7500 bytes.
112 */
113
114
115 #include <sys/param.h>
116 #include <sys/endian.h>
117 #include <sys/systm.h>
118 #include <sys/sockio.h>
119 #include <sys/mbuf.h>
120 #include <sys/kernel.h>
121 #include <sys/socket.h>
122 #include <sys/device.h>
123
124 #include <net/if.h>
125 #include <net/if_arp.h>
126 #include <net/if_dl.h>
127 #include <net/if_ether.h>
128 #include <net/if_media.h>
129 #include <net/if_vlanvar.h>
130
131 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */
132 #include <netinet/in.h> /* XXX for IP_MAXPACKET */
133 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */
134
135 #include <net/bpf.h>
136 #include <sys/rndsource.h>
137
138 #include <sys/bus.h>
139
140 #include <dev/mii/mii.h>
141 #include <dev/mii/miivar.h>
142
143 #include <dev/ic/rtl81x9reg.h>
144 #include <dev/ic/rtl81x9var.h>
145
146 #include <dev/ic/rtl8169var.h>
147
148 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t);
149
150 static int re_newbuf(struct rtk_softc *, int, struct mbuf *);
151 static int re_rx_list_init(struct rtk_softc *);
152 static int re_tx_list_init(struct rtk_softc *);
153 static void re_rxeof(struct rtk_softc *);
154 static void re_txeof(struct rtk_softc *);
155 static void re_tick(void *);
156 static void re_start(struct ifnet *);
157 static int re_ioctl(struct ifnet *, u_long, void *);
158 static int re_init(struct ifnet *);
159 static void re_stop(struct ifnet *, int);
160 static void re_watchdog(struct ifnet *);
161
162 static int re_enable(struct rtk_softc *);
163 static void re_disable(struct rtk_softc *);
164
165 static int re_gmii_readreg(device_t, int, int, uint16_t *);
166 static int re_gmii_writereg(device_t, int, int, uint16_t);
167
168 static int re_miibus_readreg(device_t, int, int, uint16_t *);
169 static int re_miibus_writereg(device_t, int, int, uint16_t);
170 static void re_miibus_statchg(struct ifnet *);
171
172 static void re_reset(struct rtk_softc *);
173
174 static const struct re_revision {
175 uint32_t re_chipid;
176 const char *re_name;
177 } re_revisions[] = {
178 { RTK_HWREV_8100, "RTL8100" },
179 { RTK_HWREV_8100E, "RTL8100E" },
180 { RTK_HWREV_8100E_SPIN2, "RTL8100E 2" },
181 { RTK_HWREV_8101, "RTL8101" },
182 { RTK_HWREV_8101E, "RTL8101E" },
183 { RTK_HWREV_8102E, "RTL8102E" },
184 { RTK_HWREV_8106E, "RTL8106E" },
185 { RTK_HWREV_8401E, "RTL8401E" },
186 { RTK_HWREV_8402, "RTL8402" },
187 { RTK_HWREV_8411, "RTL8411" },
188 { RTK_HWREV_8411B, "RTL8411B" },
189 { RTK_HWREV_8102EL, "RTL8102EL" },
190 { RTK_HWREV_8102EL_SPIN1, "RTL8102EL 1" },
191 { RTK_HWREV_8103E, "RTL8103E" },
192 { RTK_HWREV_8110S, "RTL8110S" },
193 { RTK_HWREV_8139CPLUS, "RTL8139C+" },
194 { RTK_HWREV_8168B_SPIN1, "RTL8168 1" },
195 { RTK_HWREV_8168B_SPIN2, "RTL8168 2" },
196 { RTK_HWREV_8168B_SPIN3, "RTL8168 3" },
197 { RTK_HWREV_8168C, "RTL8168C/8111C" },
198 { RTK_HWREV_8168C_SPIN2, "RTL8168C/8111C" },
199 { RTK_HWREV_8168CP, "RTL8168CP/8111CP" },
200 { RTK_HWREV_8168F, "RTL8168F/8111F" },
201 { RTK_HWREV_8168G, "RTL8168G/8111G" },
202 { RTK_HWREV_8168GU, "RTL8168GU/8111GU" },
203 { RTK_HWREV_8168H, "RTL8168H/8111H" },
204 { RTK_HWREV_8105E, "RTL8105E" },
205 { RTK_HWREV_8105E_SPIN1, "RTL8105E" },
206 { RTK_HWREV_8168D, "RTL8168D/8111D" },
207 { RTK_HWREV_8168DP, "RTL8168DP/8111DP" },
208 { RTK_HWREV_8168E, "RTL8168E/8111E" },
209 { RTK_HWREV_8168E_VL, "RTL8168E/8111E-VL" },
210 { RTK_HWREV_8168EP, "RTL8168EP/8111EP" },
211 { RTK_HWREV_8168FP, "RTL8168FP/8117" },
212 { RTK_HWREV_8169, "RTL8169" },
213 { RTK_HWREV_8169_8110SB, "RTL8169/8110SB" },
214 { RTK_HWREV_8169_8110SBL, "RTL8169SBL" },
215 { RTK_HWREV_8169_8110SC, "RTL8169/8110SCd" },
216 { RTK_HWREV_8169_8110SCE, "RTL8169/8110SCe" },
217 { RTK_HWREV_8169S, "RTL8169S" },
218
219 { 0, NULL }
220 };
221
222 static inline void
223 re_set_bufaddr(struct re_desc *d, bus_addr_t addr)
224 {
225
226 d->re_bufaddr_lo = htole32(RE_ADDR_LO(addr));
227 d->re_bufaddr_hi = htole32(RE_ADDR_HI(addr));
228 }
229
230 static int
231 re_gmii_readreg(device_t dev, int phy, int reg, uint16_t *val)
232 {
233 struct rtk_softc *sc = device_private(dev);
234 uint32_t data;
235 int i;
236
237 if (phy != 7)
238 return -1;
239
240 /* Let the rgephy driver read the GMEDIASTAT register */
241
242 if (reg == RTK_GMEDIASTAT) {
243 *val = CSR_READ_1(sc, RTK_GMEDIASTAT);
244 return 0;
245 }
246
247 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16);
248 DELAY(1000);
249
250 for (i = 0; i < RTK_TIMEOUT; i++) {
251 data = CSR_READ_4(sc, RTK_PHYAR);
252 if (data & RTK_PHYAR_BUSY)
253 break;
254 DELAY(100);
255 }
256
257 if (i == RTK_TIMEOUT) {
258 printf("%s: PHY read failed\n", device_xname(sc->sc_dev));
259 return ETIMEDOUT;
260 }
261
262 *val = data & RTK_PHYAR_PHYDATA;
263 return 0;
264 }
265
266 static int
267 re_gmii_writereg(device_t dev, int phy, int reg, uint16_t val)
268 {
269 struct rtk_softc *sc = device_private(dev);
270 uint32_t data;
271 int i;
272
273 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) |
274 (val & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY);
275 DELAY(1000);
276
277 for (i = 0; i < RTK_TIMEOUT; i++) {
278 data = CSR_READ_4(sc, RTK_PHYAR);
279 if (!(data & RTK_PHYAR_BUSY))
280 break;
281 DELAY(100);
282 }
283
284 if (i == RTK_TIMEOUT) {
285 printf("%s: PHY write reg %x <- %hx failed\n",
286 device_xname(sc->sc_dev), reg, val);
287 return ETIMEDOUT;
288 }
289
290 return 0;
291 }
292
293 static int
294 re_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val)
295 {
296 struct rtk_softc *sc = device_private(dev);
297 uint16_t re8139_reg = 0;
298 int s, rv = 0;
299
300 s = splnet();
301
302 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
303 rv = re_gmii_readreg(dev, phy, reg, val);
304 splx(s);
305 return rv;
306 }
307
308 /* Pretend the internal PHY is only at address 0 */
309 if (phy) {
310 splx(s);
311 return -1;
312 }
313 switch (reg) {
314 case MII_BMCR:
315 re8139_reg = RTK_BMCR;
316 break;
317 case MII_BMSR:
318 re8139_reg = RTK_BMSR;
319 break;
320 case MII_ANAR:
321 re8139_reg = RTK_ANAR;
322 break;
323 case MII_ANER:
324 re8139_reg = RTK_ANER;
325 break;
326 case MII_ANLPAR:
327 re8139_reg = RTK_LPAR;
328 break;
329 case MII_PHYIDR1:
330 case MII_PHYIDR2:
331 *val = 0;
332 splx(s);
333 return 0;
334 /*
335 * Allow the rlphy driver to read the media status
336 * register. If we have a link partner which does not
337 * support NWAY, this is the register which will tell
338 * us the results of parallel detection.
339 */
340 case RTK_MEDIASTAT:
341 *val = CSR_READ_1(sc, RTK_MEDIASTAT);
342 splx(s);
343 return 0;
344 default:
345 printf("%s: bad phy register\n", device_xname(sc->sc_dev));
346 splx(s);
347 return -1;
348 }
349 *val = CSR_READ_2(sc, re8139_reg);
350 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) {
351 /* 8139C+ has different bit layout. */
352 *val &= ~(BMCR_LOOP | BMCR_ISO);
353 }
354 splx(s);
355 return 0;
356 }
357
358 static int
359 re_miibus_writereg(device_t dev, int phy, int reg, uint16_t val)
360 {
361 struct rtk_softc *sc = device_private(dev);
362 uint16_t re8139_reg = 0;
363 int s, rv;
364
365 s = splnet();
366
367 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
368 rv = re_gmii_writereg(dev, phy, reg, val);
369 splx(s);
370 return rv;
371 }
372
373 /* Pretend the internal PHY is only at address 0 */
374 if (phy) {
375 splx(s);
376 return -1;
377 }
378 switch (reg) {
379 case MII_BMCR:
380 re8139_reg = RTK_BMCR;
381 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) {
382 /* 8139C+ has different bit layout. */
383 val &= ~(BMCR_LOOP | BMCR_ISO);
384 }
385 break;
386 case MII_BMSR:
387 re8139_reg = RTK_BMSR;
388 break;
389 case MII_ANAR:
390 re8139_reg = RTK_ANAR;
391 break;
392 case MII_ANER:
393 re8139_reg = RTK_ANER;
394 break;
395 case MII_ANLPAR:
396 re8139_reg = RTK_LPAR;
397 break;
398 case MII_PHYIDR1:
399 case MII_PHYIDR2:
400 splx(s);
401 return 0;
402 break;
403 default:
404 printf("%s: bad phy register\n", device_xname(sc->sc_dev));
405 splx(s);
406 return -1;
407 }
408 CSR_WRITE_2(sc, re8139_reg, val);
409 splx(s);
410 return 0;
411 }
412
413 static void
414 re_miibus_statchg(struct ifnet *ifp)
415 {
416
417 return;
418 }
419
420 static void
421 re_reset(struct rtk_softc *sc)
422 {
423 int i;
424
425 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET);
426
427 for (i = 0; i < RTK_TIMEOUT; i++) {
428 DELAY(10);
429 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
430 break;
431 }
432 if (i == RTK_TIMEOUT)
433 printf("%s: reset never completed!\n",
434 device_xname(sc->sc_dev));
435
436 /*
437 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3,
438 * but also says "Rtl8169s sigle chip detected".
439 */
440 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0)
441 CSR_WRITE_1(sc, RTK_LDPS, 1);
442
443 }
444
445 /*
446 * The following routine is designed to test for a defect on some
447 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
448 * lines connected to the bus, however for a 32-bit only card, they
449 * should be pulled high. The result of this defect is that the
450 * NIC will not work right if you plug it into a 64-bit slot: DMA
451 * operations will be done with 64-bit transfers, which will fail
452 * because the 64-bit data lines aren't connected.
453 *
454 * There's no way to work around this (short of talking a soldering
455 * iron to the board), however we can detect it. The method we use
456 * here is to put the NIC into digital loopback mode, set the receiver
457 * to promiscuous mode, and then try to send a frame. We then compare
458 * the frame data we sent to what was received. If the data matches,
459 * then the NIC is working correctly, otherwise we know the user has
460 * a defective NIC which has been mistakenly plugged into a 64-bit PCI
461 * slot. In the latter case, there's no way the NIC can work correctly,
462 * so we print out a message on the console and abort the device attach.
463 */
464
465 int
466 re_diag(struct rtk_softc *sc)
467 {
468 struct ifnet *ifp = &sc->ethercom.ec_if;
469 struct mbuf *m0;
470 struct ether_header *eh;
471 struct re_rxsoft *rxs;
472 struct re_desc *cur_rx;
473 bus_dmamap_t dmamap;
474 uint16_t status;
475 uint32_t rxstat;
476 int total_len, i, s, error = 0;
477 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
478 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
479
480 /* Allocate a single mbuf */
481
482 MGETHDR(m0, M_DONTWAIT, MT_DATA);
483 if (m0 == NULL)
484 return ENOBUFS;
485
486 /*
487 * Initialize the NIC in test mode. This sets the chip up
488 * so that it can send and receive frames, but performs the
489 * following special functions:
490 * - Puts receiver in promiscuous mode
491 * - Enables digital loopback mode
492 * - Leaves interrupts turned off
493 */
494
495 ifp->if_flags |= IFF_PROMISC;
496 sc->re_testmode = 1;
497 re_init(ifp);
498 re_stop(ifp, 0);
499 DELAY(100000);
500 re_init(ifp);
501
502 /* Put some data in the mbuf */
503
504 eh = mtod(m0, struct ether_header *);
505 memcpy(eh->ether_dhost, &dst, ETHER_ADDR_LEN);
506 memcpy(eh->ether_shost, &src, ETHER_ADDR_LEN);
507 eh->ether_type = htons(ETHERTYPE_IP);
508 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
509
510 /*
511 * Queue the packet, start transmission.
512 */
513
514 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
515 s = splnet();
516 IF_ENQUEUE(&ifp->if_snd, m0);
517 re_start(ifp);
518 splx(s);
519 m0 = NULL;
520
521 /* Wait for it to propagate through the chip */
522
523 DELAY(100000);
524 for (i = 0; i < RTK_TIMEOUT; i++) {
525 status = CSR_READ_2(sc, RTK_ISR);
526 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) ==
527 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK))
528 break;
529 DELAY(10);
530 }
531 if (i == RTK_TIMEOUT) {
532 aprint_error_dev(sc->sc_dev,
533 "diagnostic failed, failed to receive packet "
534 "in loopback mode\n");
535 error = EIO;
536 goto done;
537 }
538
539 /*
540 * The packet should have been dumped into the first
541 * entry in the RX DMA ring. Grab it from there.
542 */
543
544 rxs = &sc->re_ldata.re_rxsoft[0];
545 dmamap = rxs->rxs_dmamap;
546 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
547 BUS_DMASYNC_POSTREAD);
548 bus_dmamap_unload(sc->sc_dmat, dmamap);
549
550 m0 = rxs->rxs_mbuf;
551 rxs->rxs_mbuf = NULL;
552 eh = mtod(m0, struct ether_header *);
553
554 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
555 cur_rx = &sc->re_ldata.re_rx_list[0];
556 rxstat = le32toh(cur_rx->re_cmdstat);
557 total_len = rxstat & sc->re_rxlenmask;
558
559 if (total_len != ETHER_MIN_LEN) {
560 aprint_error_dev(sc->sc_dev,
561 "diagnostic failed, received short packet\n");
562 error = EIO;
563 goto done;
564 }
565
566 /* Test that the received packet data matches what we sent. */
567
568 if (memcmp(&eh->ether_dhost, &dst, ETHER_ADDR_LEN) ||
569 memcmp(&eh->ether_shost, &src, ETHER_ADDR_LEN) ||
570 ntohs(eh->ether_type) != ETHERTYPE_IP) {
571 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n"
572 "expected TX data: %s/%s/0x%x\n"
573 "received RX data: %s/%s/0x%x\n"
574 "You may have a defective 32-bit NIC plugged "
575 "into a 64-bit PCI slot.\n"
576 "Please re-install the NIC in a 32-bit slot "
577 "for proper operation.\n"
578 "Read the re(4) man page for more details.\n" ,
579 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP,
580 ether_sprintf(eh->ether_dhost),
581 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type));
582 error = EIO;
583 }
584
585 done:
586 /* Turn interface off, release resources */
587
588 sc->re_testmode = 0;
589 ifp->if_flags &= ~IFF_PROMISC;
590 re_stop(ifp, 0);
591 if (m0 != NULL)
592 m_freem(m0);
593
594 return error;
595 }
596
597
598 /*
599 * Attach the interface. Allocate softc structures, do ifmedia
600 * setup and ethernet/BPF attach.
601 */
602 void
603 re_attach(struct rtk_softc *sc)
604 {
605 uint8_t eaddr[ETHER_ADDR_LEN];
606 struct ifnet *ifp;
607 struct mii_data *mii = &sc->mii;
608 int error = 0, i;
609 const struct re_revision *rr;
610 const char *re_name = NULL;
611
612 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
613 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */
614 sc->sc_hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV;
615
616 for (rr = re_revisions; rr->re_name != NULL; rr++) {
617 if (rr->re_chipid == sc->sc_hwrev)
618 re_name = rr->re_name;
619 }
620
621 if (re_name == NULL)
622 aprint_normal_dev(sc->sc_dev,
623 "unknown ASIC (0x%04x)\n", sc->sc_hwrev >> 16);
624 else
625 aprint_normal_dev(sc->sc_dev,
626 "%s (0x%04x)\n", re_name, sc->sc_hwrev >> 16);
627
628 switch (sc->sc_hwrev) {
629 case RTK_HWREV_8169:
630 sc->sc_quirk |= RTKQ_8169NONS;
631 break;
632 case RTK_HWREV_8169S:
633 case RTK_HWREV_8110S:
634 case RTK_HWREV_8169_8110SB:
635 case RTK_HWREV_8169_8110SBL:
636 case RTK_HWREV_8169_8110SC:
637 sc->sc_quirk |= RTKQ_MACLDPS;
638 break;
639 case RTK_HWREV_8168B_SPIN1:
640 case RTK_HWREV_8168B_SPIN2:
641 case RTK_HWREV_8168B_SPIN3:
642 sc->sc_quirk |= RTKQ_MACSTAT;
643 break;
644 case RTK_HWREV_8168C:
645 case RTK_HWREV_8168C_SPIN2:
646 case RTK_HWREV_8168CP:
647 case RTK_HWREV_8168D:
648 case RTK_HWREV_8168DP:
649 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
650 RTKQ_MACSTAT | RTKQ_CMDSTOP;
651 /*
652 * From FreeBSD driver:
653 *
654 * These (8168/8111) controllers support jumbo frame
655 * but it seems that enabling it requires touching
656 * additional magic registers. Depending on MAC
657 * revisions some controllers need to disable
658 * checksum offload. So disable jumbo frame until
659 * I have better idea what it really requires to
660 * make it support.
661 * RTL8168C/CP : supports up to 6KB jumbo frame.
662 * RTL8111C/CP : supports up to 9KB jumbo frame.
663 */
664 sc->sc_quirk |= RTKQ_NOJUMBO;
665 break;
666 case RTK_HWREV_8168E:
667 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
668 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM |
669 RTKQ_NOJUMBO;
670 break;
671 case RTK_HWREV_8168E_VL:
672 case RTK_HWREV_8168F:
673 case RTK_HWREV_8411:
674 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
675 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
676 break;
677 case RTK_HWREV_8168EP:
678 case RTK_HWREV_8168FP:
679 case RTK_HWREV_8168G:
680 case RTK_HWREV_8168GU:
681 case RTK_HWREV_8168H:
682 case RTK_HWREV_8411B:
683 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
684 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO |
685 RTKQ_RXDV_GATED | RTKQ_TXRXEN_LATER;
686 break;
687 case RTK_HWREV_8100E:
688 case RTK_HWREV_8100E_SPIN2:
689 case RTK_HWREV_8101E:
690 sc->sc_quirk |= RTKQ_NOJUMBO;
691 break;
692 case RTK_HWREV_8102E:
693 case RTK_HWREV_8102EL:
694 case RTK_HWREV_8102EL_SPIN1:
695 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
696 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO;
697 break;
698 case RTK_HWREV_8103E:
699 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD |
700 RTKQ_MACSTAT | RTKQ_CMDSTOP;
701 break;
702 case RTK_HWREV_8401E:
703 case RTK_HWREV_8105E:
704 case RTK_HWREV_8105E_SPIN1: /* XXX */
705 case RTK_HWREV_8106E:
706 sc->sc_quirk |= RTKQ_PHYWAKE_PM |
707 RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT |
708 RTKQ_CMDSTOP;
709 break;
710 case RTK_HWREV_8402:
711 sc->sc_quirk |= RTKQ_PHYWAKE_PM |
712 RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT |
713 RTKQ_CMDSTOP; /* CMDSTOP_WAIT_TXQ */
714 break;
715 default:
716 /* assume the latest features */
717 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD;
718 sc->sc_quirk |= RTKQ_NOJUMBO;
719 }
720
721 /* Set RX length mask */
722 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
723 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169;
724 } else {
725 sc->sc_quirk |= RTKQ_NOJUMBO;
726
727 /* Set RX length mask */
728 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
729 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139;
730 }
731
732 /* Reset the adapter. */
733 re_reset(sc);
734
735 /*
736 * RTL81x9 chips automatically read EEPROM to init MAC address,
737 * and some NAS override its MAC address per own configuration,
738 * so no need to explicitly read EEPROM and set ID registers.
739 */
740 #ifdef RE_USE_EECMD
741 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) {
742 /*
743 * Get station address from ID registers.
744 */
745 for (i = 0; i < ETHER_ADDR_LEN; i++)
746 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
747 } else {
748 uint16_t val;
749 int addr_len;
750
751 /*
752 * Get station address from the EEPROM.
753 */
754 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129)
755 addr_len = RTK_EEADDR_LEN1;
756 else
757 addr_len = RTK_EEADDR_LEN0;
758
759 /*
760 * Get station address from the EEPROM.
761 */
762 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
763 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len);
764 eaddr[(i * 2) + 0] = val & 0xff;
765 eaddr[(i * 2) + 1] = val >> 8;
766 }
767 }
768 #else
769 /*
770 * Get station address from ID registers.
771 */
772 for (i = 0; i < ETHER_ADDR_LEN; i++)
773 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i);
774 #endif
775
776 /* Take PHY out of power down mode. */
777 if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0)
778 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80);
779
780 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n",
781 ether_sprintf(eaddr));
782
783 if (sc->re_ldata.re_tx_desc_cnt >
784 PAGE_SIZE / sizeof(struct re_desc)) {
785 sc->re_ldata.re_tx_desc_cnt =
786 PAGE_SIZE / sizeof(struct re_desc);
787 }
788
789 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n",
790 sc->re_ldata.re_tx_desc_cnt);
791 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0);
792
793 /* Allocate DMA'able memory for the TX ring */
794 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc),
795 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1,
796 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) {
797 aprint_error_dev(sc->sc_dev,
798 "can't allocate tx listseg, error = %d\n", error);
799 goto fail_0;
800 }
801
802 /* Load the map for the TX ring. */
803 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg,
804 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc),
805 (void **)&sc->re_ldata.re_tx_list,
806 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
807 aprint_error_dev(sc->sc_dev,
808 "can't map tx list, error = %d\n", error);
809 goto fail_1;
810 }
811 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc));
812
813 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1,
814 RE_TX_LIST_SZ(sc), 0, 0,
815 &sc->re_ldata.re_tx_list_map)) != 0) {
816 aprint_error_dev(sc->sc_dev,
817 "can't create tx list map, error = %d\n", error);
818 goto fail_2;
819 }
820
821
822 if ((error = bus_dmamap_load(sc->sc_dmat,
823 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list,
824 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) {
825 aprint_error_dev(sc->sc_dev,
826 "can't load tx list, error = %d\n", error);
827 goto fail_3;
828 }
829
830 /* Create DMA maps for TX buffers */
831 for (i = 0; i < RE_TX_QLEN; i++) {
832 error = bus_dmamap_create(sc->sc_dmat,
833 round_page(IP_MAXPACKET),
834 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN,
835 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap);
836 if (error) {
837 aprint_error_dev(sc->sc_dev,
838 "can't create DMA map for TX\n");
839 goto fail_4;
840 }
841 }
842
843 /* Allocate DMA'able memory for the RX ring */
844 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */
845 if ((error = bus_dmamem_alloc(sc->sc_dmat,
846 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1,
847 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) {
848 aprint_error_dev(sc->sc_dev,
849 "can't allocate rx listseg, error = %d\n", error);
850 goto fail_4;
851 }
852
853 /* Load the map for the RX ring. */
854 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg,
855 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ,
856 (void **)&sc->re_ldata.re_rx_list,
857 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) {
858 aprint_error_dev(sc->sc_dev,
859 "can't map rx list, error = %d\n", error);
860 goto fail_5;
861 }
862 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ);
863
864 if ((error = bus_dmamap_create(sc->sc_dmat,
865 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0,
866 &sc->re_ldata.re_rx_list_map)) != 0) {
867 aprint_error_dev(sc->sc_dev,
868 "can't create rx list map, error = %d\n", error);
869 goto fail_6;
870 }
871
872 if ((error = bus_dmamap_load(sc->sc_dmat,
873 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list,
874 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) {
875 aprint_error_dev(sc->sc_dev,
876 "can't load rx list, error = %d\n", error);
877 goto fail_7;
878 }
879
880 /* Create DMA maps for RX buffers */
881 for (i = 0; i < RE_RX_DESC_CNT; i++) {
882 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES,
883 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap);
884 if (error) {
885 aprint_error_dev(sc->sc_dev,
886 "can't create DMA map for RX\n");
887 goto fail_8;
888 }
889 }
890
891 /*
892 * Record interface as attached. From here, we should not fail.
893 */
894 sc->sc_flags |= RTK_ATTACHED;
895
896 ifp = &sc->ethercom.ec_if;
897 ifp->if_softc = sc;
898 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
899 ifp->if_mtu = ETHERMTU;
900 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
901 ifp->if_ioctl = re_ioctl;
902 sc->ethercom.ec_capabilities |=
903 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING;
904 ifp->if_start = re_start;
905 ifp->if_stop = re_stop;
906
907 /*
908 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets,
909 * so we have a workaround to handle the bug by padding
910 * such packets manually.
911 */
912 ifp->if_capabilities |=
913 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
914 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
915 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
916 IFCAP_TSOv4;
917
918 ifp->if_watchdog = re_watchdog;
919 ifp->if_init = re_init;
920 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN;
921 ifp->if_capenable = ifp->if_capabilities;
922 IFQ_SET_READY(&ifp->if_snd);
923
924 callout_init(&sc->rtk_tick_ch, 0);
925 callout_setfunc(&sc->rtk_tick_ch, re_tick, sc);
926
927 /* Do MII setup */
928 mii->mii_ifp = ifp;
929 mii->mii_readreg = re_miibus_readreg;
930 mii->mii_writereg = re_miibus_writereg;
931 mii->mii_statchg = re_miibus_statchg;
932 sc->ethercom.ec_mii = mii;
933 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange,
934 ether_mediastatus);
935 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
936 MII_OFFSET_ANY, 0);
937 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
938
939 /*
940 * Call MI attach routine.
941 */
942 if_attach(ifp);
943 if_deferred_start_init(ifp, NULL);
944 ether_ifattach(ifp, eaddr);
945
946 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev),
947 RND_TYPE_NET, RND_FLAG_DEFAULT);
948
949 if (pmf_device_register(sc->sc_dev, NULL, NULL))
950 pmf_class_network_register(sc->sc_dev, ifp);
951 else
952 aprint_error_dev(sc->sc_dev,
953 "couldn't establish power handler\n");
954
955 return;
956
957 fail_8:
958 /* Destroy DMA maps for RX buffers. */
959 for (i = 0; i < RE_RX_DESC_CNT; i++)
960 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL)
961 bus_dmamap_destroy(sc->sc_dmat,
962 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
963
964 /* Free DMA'able memory for the RX ring. */
965 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
966 fail_7:
967 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
968 fail_6:
969 bus_dmamem_unmap(sc->sc_dmat,
970 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ);
971 fail_5:
972 bus_dmamem_free(sc->sc_dmat,
973 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg);
974
975 fail_4:
976 /* Destroy DMA maps for TX buffers. */
977 for (i = 0; i < RE_TX_QLEN; i++)
978 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL)
979 bus_dmamap_destroy(sc->sc_dmat,
980 sc->re_ldata.re_txq[i].txq_dmamap);
981
982 /* Free DMA'able memory for the TX ring. */
983 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
984 fail_3:
985 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
986 fail_2:
987 bus_dmamem_unmap(sc->sc_dmat,
988 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
989 fail_1:
990 bus_dmamem_free(sc->sc_dmat,
991 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg);
992 fail_0:
993 return;
994 }
995
996
997 /*
998 * re_activate:
999 * Handle device activation/deactivation requests.
1000 */
1001 int
1002 re_activate(device_t self, enum devact act)
1003 {
1004 struct rtk_softc *sc = device_private(self);
1005
1006 switch (act) {
1007 case DVACT_DEACTIVATE:
1008 if_deactivate(&sc->ethercom.ec_if);
1009 return 0;
1010 default:
1011 return EOPNOTSUPP;
1012 }
1013 }
1014
1015 /*
1016 * re_detach:
1017 * Detach a rtk interface.
1018 */
1019 int
1020 re_detach(struct rtk_softc *sc)
1021 {
1022 struct ifnet *ifp = &sc->ethercom.ec_if;
1023 int i;
1024
1025 /*
1026 * Succeed now if there isn't any work to do.
1027 */
1028 if ((sc->sc_flags & RTK_ATTACHED) == 0)
1029 return 0;
1030
1031 /* Unhook our tick handler. */
1032 callout_stop(&sc->rtk_tick_ch);
1033
1034 /* Detach all PHYs. */
1035 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY);
1036
1037 rnd_detach_source(&sc->rnd_source);
1038 ether_ifdetach(ifp);
1039 if_detach(ifp);
1040
1041 /* Delete all remaining media. */
1042 ifmedia_fini(&sc->mii.mii_media);
1043
1044 /* Destroy DMA maps for RX buffers. */
1045 for (i = 0; i < RE_RX_DESC_CNT; i++)
1046 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL)
1047 bus_dmamap_destroy(sc->sc_dmat,
1048 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
1049
1050 /* Free DMA'able memory for the RX ring. */
1051 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
1052 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map);
1053 bus_dmamem_unmap(sc->sc_dmat,
1054 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ);
1055 bus_dmamem_free(sc->sc_dmat,
1056 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg);
1057
1058 /* Destroy DMA maps for TX buffers. */
1059 for (i = 0; i < RE_TX_QLEN; i++)
1060 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL)
1061 bus_dmamap_destroy(sc->sc_dmat,
1062 sc->re_ldata.re_txq[i].txq_dmamap);
1063
1064 /* Free DMA'able memory for the TX ring. */
1065 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
1066 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map);
1067 bus_dmamem_unmap(sc->sc_dmat,
1068 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
1069 bus_dmamem_free(sc->sc_dmat,
1070 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg);
1071
1072 pmf_device_deregister(sc->sc_dev);
1073
1074 /* we don't want to run again */
1075 sc->sc_flags &= ~RTK_ATTACHED;
1076
1077 return 0;
1078 }
1079
1080 /*
1081 * re_enable:
1082 * Enable the RTL81X9 chip.
1083 */
1084 static int
1085 re_enable(struct rtk_softc *sc)
1086 {
1087
1088 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) {
1089 if ((*sc->sc_enable)(sc) != 0) {
1090 printf("%s: device enable failed\n",
1091 device_xname(sc->sc_dev));
1092 return EIO;
1093 }
1094 sc->sc_flags |= RTK_ENABLED;
1095 }
1096 return 0;
1097 }
1098
1099 /*
1100 * re_disable:
1101 * Disable the RTL81X9 chip.
1102 */
1103 static void
1104 re_disable(struct rtk_softc *sc)
1105 {
1106
1107 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) {
1108 (*sc->sc_disable)(sc);
1109 sc->sc_flags &= ~RTK_ENABLED;
1110 }
1111 }
1112
1113 static int
1114 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m)
1115 {
1116 struct mbuf *n = NULL;
1117 bus_dmamap_t map;
1118 struct re_desc *d;
1119 struct re_rxsoft *rxs;
1120 uint32_t cmdstat;
1121 int error;
1122
1123 if (m == NULL) {
1124 MGETHDR(n, M_DONTWAIT, MT_DATA);
1125 if (n == NULL)
1126 return ENOBUFS;
1127
1128 MCLAIM(n, &sc->ethercom.ec_rx_mowner);
1129 MCLGET(n, M_DONTWAIT);
1130 if ((n->m_flags & M_EXT) == 0) {
1131 m_freem(n);
1132 return ENOBUFS;
1133 }
1134 m = n;
1135 } else
1136 m->m_data = m->m_ext.ext_buf;
1137
1138 /*
1139 * Initialize mbuf length fields and fixup
1140 * alignment so that the frame payload is
1141 * longword aligned.
1142 */
1143 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN;
1144 m->m_data += RE_ETHER_ALIGN;
1145
1146 rxs = &sc->re_ldata.re_rxsoft[idx];
1147 map = rxs->rxs_dmamap;
1148 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
1149 BUS_DMA_READ|BUS_DMA_NOWAIT);
1150
1151 if (error)
1152 goto out;
1153
1154 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1155 BUS_DMASYNC_PREREAD);
1156
1157 d = &sc->re_ldata.re_rx_list[idx];
1158 #ifdef DIAGNOSTIC
1159 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1160 cmdstat = le32toh(d->re_cmdstat);
1161 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD);
1162 if (cmdstat & RE_RDESC_STAT_OWN) {
1163 panic("%s: tried to map busy RX descriptor",
1164 device_xname(sc->sc_dev));
1165 }
1166 #endif
1167
1168 rxs->rxs_mbuf = m;
1169
1170 d->re_vlanctl = 0;
1171 cmdstat = map->dm_segs[0].ds_len;
1172 if (idx == (RE_RX_DESC_CNT - 1))
1173 cmdstat |= RE_RDESC_CMD_EOR;
1174 re_set_bufaddr(d, map->dm_segs[0].ds_addr);
1175 d->re_cmdstat = htole32(cmdstat);
1176 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1177 cmdstat |= RE_RDESC_CMD_OWN;
1178 d->re_cmdstat = htole32(cmdstat);
1179 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1180
1181 return 0;
1182 out:
1183 if (n != NULL)
1184 m_freem(n);
1185 return ENOMEM;
1186 }
1187
1188 static int
1189 re_tx_list_init(struct rtk_softc *sc)
1190 {
1191 int i;
1192
1193 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc));
1194 for (i = 0; i < RE_TX_QLEN; i++) {
1195 sc->re_ldata.re_txq[i].txq_mbuf = NULL;
1196 }
1197
1198 bus_dmamap_sync(sc->sc_dmat,
1199 sc->re_ldata.re_tx_list_map, 0,
1200 sc->re_ldata.re_tx_list_map->dm_mapsize,
1201 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1202 sc->re_ldata.re_txq_prodidx = 0;
1203 sc->re_ldata.re_txq_considx = 0;
1204 sc->re_ldata.re_txq_free = RE_TX_QLEN;
1205 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc);
1206 sc->re_ldata.re_tx_nextfree = 0;
1207
1208 return 0;
1209 }
1210
1211 static int
1212 re_rx_list_init(struct rtk_softc *sc)
1213 {
1214 int i;
1215
1216 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ);
1217
1218 for (i = 0; i < RE_RX_DESC_CNT; i++) {
1219 if (re_newbuf(sc, i, NULL) == ENOBUFS)
1220 return ENOBUFS;
1221 }
1222
1223 sc->re_ldata.re_rx_prodidx = 0;
1224 sc->re_head = sc->re_tail = NULL;
1225
1226 return 0;
1227 }
1228
1229 /*
1230 * RX handler for C+ and 8169. For the gigE chips, we support
1231 * the reception of jumbo frames that have been fragmented
1232 * across multiple 2K mbuf cluster buffers.
1233 */
1234 static void
1235 re_rxeof(struct rtk_softc *sc)
1236 {
1237 struct mbuf *m;
1238 struct ifnet *ifp;
1239 int i, total_len;
1240 struct re_desc *cur_rx;
1241 struct re_rxsoft *rxs;
1242 uint32_t rxstat, rxvlan;
1243
1244 ifp = &sc->ethercom.ec_if;
1245
1246 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) {
1247 cur_rx = &sc->re_ldata.re_rx_list[i];
1248 RE_RXDESCSYNC(sc, i,
1249 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1250 rxstat = le32toh(cur_rx->re_cmdstat);
1251 rxvlan = le32toh(cur_rx->re_vlanctl);
1252 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD);
1253 if ((rxstat & RE_RDESC_STAT_OWN) != 0) {
1254 break;
1255 }
1256 total_len = rxstat & sc->re_rxlenmask;
1257 rxs = &sc->re_ldata.re_rxsoft[i];
1258 m = rxs->rxs_mbuf;
1259
1260 /* Invalidate the RX mbuf and unload its map */
1261
1262 bus_dmamap_sync(sc->sc_dmat,
1263 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize,
1264 BUS_DMASYNC_POSTREAD);
1265 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap);
1266
1267 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1268 m->m_len = MCLBYTES - RE_ETHER_ALIGN;
1269 if (sc->re_head == NULL)
1270 sc->re_head = sc->re_tail = m;
1271 else {
1272 m_remove_pkthdr(m);
1273 sc->re_tail->m_next = m;
1274 sc->re_tail = m;
1275 }
1276 re_newbuf(sc, i, NULL);
1277 continue;
1278 }
1279
1280 /*
1281 * NOTE: for the 8139C+, the frame length field
1282 * is always 12 bits in size, but for the gigE chips,
1283 * it is 13 bits (since the max RX frame length is 16K).
1284 * Unfortunately, all 32 bits in the status word
1285 * were already used, so to make room for the extra
1286 * length bit, RealTek took out the 'frame alignment
1287 * error' bit and shifted the other status bits
1288 * over one slot. The OWN, EOR, FS and LS bits are
1289 * still in the same places. We have already extracted
1290 * the frame length and checked the OWN bit, so rather
1291 * than using an alternate bit mapping, we shift the
1292 * status bits one space to the right so we can evaluate
1293 * them using the 8169 status as though it was in the
1294 * same format as that of the 8139C+.
1295 */
1296 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0)
1297 rxstat >>= 1;
1298
1299 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) {
1300 #ifdef RE_DEBUG
1301 printf("%s: RX error (rxstat = 0x%08x)",
1302 device_xname(sc->sc_dev), rxstat);
1303 if (rxstat & RE_RDESC_STAT_FRALIGN)
1304 printf(", frame alignment error");
1305 if (rxstat & RE_RDESC_STAT_BUFOFLOW)
1306 printf(", out of buffer space");
1307 if (rxstat & RE_RDESC_STAT_FIFOOFLOW)
1308 printf(", FIFO overrun");
1309 if (rxstat & RE_RDESC_STAT_GIANT)
1310 printf(", giant packet");
1311 if (rxstat & RE_RDESC_STAT_RUNT)
1312 printf(", runt packet");
1313 if (rxstat & RE_RDESC_STAT_CRCERR)
1314 printf(", CRC error");
1315 printf("\n");
1316 #endif
1317 if_statinc(ifp, if_ierrors);
1318 /*
1319 * If this is part of a multi-fragment packet,
1320 * discard all the pieces.
1321 */
1322 if (sc->re_head != NULL) {
1323 m_freem(sc->re_head);
1324 sc->re_head = sc->re_tail = NULL;
1325 }
1326 re_newbuf(sc, i, m);
1327 continue;
1328 }
1329
1330 /*
1331 * If allocating a replacement mbuf fails,
1332 * reload the current one.
1333 */
1334
1335 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) {
1336 if_statinc(ifp, if_ierrors);
1337 if (sc->re_head != NULL) {
1338 m_freem(sc->re_head);
1339 sc->re_head = sc->re_tail = NULL;
1340 }
1341 re_newbuf(sc, i, m);
1342 continue;
1343 }
1344
1345 if (sc->re_head != NULL) {
1346 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN);
1347 /*
1348 * Special case: if there's 4 bytes or less
1349 * in this buffer, the mbuf can be discarded:
1350 * the last 4 bytes is the CRC, which we don't
1351 * care about anyway.
1352 */
1353 if (m->m_len <= ETHER_CRC_LEN) {
1354 sc->re_tail->m_len -=
1355 (ETHER_CRC_LEN - m->m_len);
1356 m_freem(m);
1357 } else {
1358 m->m_len -= ETHER_CRC_LEN;
1359 m_remove_pkthdr(m);
1360 sc->re_tail->m_next = m;
1361 }
1362 m = sc->re_head;
1363 sc->re_head = sc->re_tail = NULL;
1364 m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
1365 } else
1366 m->m_pkthdr.len = m->m_len =
1367 (total_len - ETHER_CRC_LEN);
1368
1369 m_set_rcvif(m, ifp);
1370
1371 /* Do RX checksumming */
1372 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
1373 /* Check IP header checksum */
1374 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) {
1375 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1376 if (rxstat & RE_RDESC_STAT_IPSUMBAD)
1377 m->m_pkthdr.csum_flags |=
1378 M_CSUM_IPv4_BAD;
1379
1380 /* Check TCP/UDP checksum */
1381 if (RE_TCPPKT(rxstat)) {
1382 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1383 if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
1384 m->m_pkthdr.csum_flags |=
1385 M_CSUM_TCP_UDP_BAD;
1386 } else if (RE_UDPPKT(rxstat)) {
1387 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1388 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) {
1389 /*
1390 * XXX: 8139C+ thinks UDP csum
1391 * 0xFFFF is bad, force software
1392 * calculation.
1393 */
1394 if (sc->sc_quirk & RTKQ_8139CPLUS)
1395 m->m_pkthdr.csum_flags
1396 &= ~M_CSUM_UDPv4;
1397 else
1398 m->m_pkthdr.csum_flags
1399 |= M_CSUM_TCP_UDP_BAD;
1400 }
1401 }
1402 }
1403 } else {
1404 /* Check IPv4 header checksum */
1405 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) {
1406 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;
1407 if (rxstat & RE_RDESC_STAT_IPSUMBAD)
1408 m->m_pkthdr.csum_flags |=
1409 M_CSUM_IPv4_BAD;
1410
1411 /* Check TCPv4/UDPv4 checksum */
1412 if (RE_TCPPKT(rxstat)) {
1413 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4;
1414 if (rxstat & RE_RDESC_STAT_TCPSUMBAD)
1415 m->m_pkthdr.csum_flags |=
1416 M_CSUM_TCP_UDP_BAD;
1417 } else if (RE_UDPPKT(rxstat)) {
1418 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4;
1419 if (rxstat & RE_RDESC_STAT_UDPSUMBAD)
1420 m->m_pkthdr.csum_flags |=
1421 M_CSUM_TCP_UDP_BAD;
1422 }
1423 }
1424 /* XXX Check TCPv6/UDPv6 checksum? */
1425 }
1426
1427 if (rxvlan & RE_RDESC_VLANCTL_TAG) {
1428 vlan_set_tag(m,
1429 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA));
1430 }
1431 if_percpuq_enqueue(ifp->if_percpuq, m);
1432 }
1433
1434 sc->re_ldata.re_rx_prodidx = i;
1435 }
1436
1437 static void
1438 re_txeof(struct rtk_softc *sc)
1439 {
1440 struct ifnet *ifp;
1441 struct re_txq *txq;
1442 uint32_t txstat;
1443 int idx, descidx;
1444
1445 ifp = &sc->ethercom.ec_if;
1446
1447 for (idx = sc->re_ldata.re_txq_considx;
1448 sc->re_ldata.re_txq_free < RE_TX_QLEN;
1449 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) {
1450 txq = &sc->re_ldata.re_txq[idx];
1451 KASSERT(txq->txq_mbuf != NULL);
1452
1453 descidx = txq->txq_descidx;
1454 RE_TXDESCSYNC(sc, descidx,
1455 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1456 txstat =
1457 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat);
1458 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD);
1459 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0);
1460 if (txstat & RE_TDESC_CMD_OWN) {
1461 break;
1462 }
1463
1464 sc->re_ldata.re_tx_free += txq->txq_nsegs;
1465 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc));
1466 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap,
1467 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1468 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap);
1469 m_freem(txq->txq_mbuf);
1470 txq->txq_mbuf = NULL;
1471
1472 net_stat_ref_t nsr = IF_STAT_GETREF(ifp);
1473 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT))
1474 if_statinc_ref(nsr, if_collisions);
1475 if (txstat & RE_TDESC_STAT_TXERRSUM)
1476 if_statinc_ref(nsr, if_oerrors);
1477 else
1478 if_statinc_ref(nsr, if_opackets);
1479 IF_STAT_PUTREF(ifp);
1480 }
1481
1482 sc->re_ldata.re_txq_considx = idx;
1483
1484 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD)
1485 ifp->if_flags &= ~IFF_OACTIVE;
1486
1487 /*
1488 * If not all descriptors have been released reaped yet,
1489 * reload the timer so that we will eventually get another
1490 * interrupt that will cause us to re-enter this routine.
1491 * This is done in case the transmitter has gone idle.
1492 */
1493 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) {
1494 if ((sc->sc_quirk & RTKQ_IM_HW) == 0)
1495 CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
1496 if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
1497 /*
1498 * Some chips will ignore a second TX request
1499 * issued while an existing transmission is in
1500 * progress. If the transmitter goes idle but
1501 * there are still packets waiting to be sent,
1502 * we need to restart the channel here to flush
1503 * them out. This only seems to be required with
1504 * the PCIe devices.
1505 */
1506 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
1507 }
1508 } else
1509 ifp->if_timer = 0;
1510 }
1511
1512 static void
1513 re_tick(void *arg)
1514 {
1515 struct rtk_softc *sc = arg;
1516 int s;
1517
1518 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */
1519 s = splnet();
1520
1521 mii_tick(&sc->mii);
1522 splx(s);
1523
1524 callout_schedule(&sc->rtk_tick_ch, hz);
1525 }
1526
1527 int
1528 re_intr(void *arg)
1529 {
1530 struct rtk_softc *sc = arg;
1531 struct ifnet *ifp;
1532 uint16_t status, rndstatus = 0;
1533 int handled = 0;
1534
1535 if (!device_has_power(sc->sc_dev))
1536 return 0;
1537
1538 ifp = &sc->ethercom.ec_if;
1539
1540 if ((ifp->if_flags & IFF_UP) == 0)
1541 return 0;
1542
1543 const uint16_t status_mask = (sc->sc_quirk & RTKQ_IM_HW) ?
1544 RTK_INTRS_IM_HW : RTK_INTRS_CPLUS;
1545
1546 for (;;) {
1547
1548 status = CSR_READ_2(sc, RTK_ISR);
1549 /* If the card has gone away the read returns 0xffff. */
1550 if (status == 0xffff)
1551 break;
1552 if (status != 0) {
1553 handled = 1;
1554 CSR_WRITE_2(sc, RTK_ISR, status);
1555 rndstatus = status;
1556 }
1557
1558 if ((status & status_mask) == 0)
1559 break;
1560
1561 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR))
1562 re_rxeof(sc);
1563
1564 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR |
1565 RTK_ISR_TX_DESC_UNAVAIL | RTK_ISR_TX_OK))
1566 re_txeof(sc);
1567
1568 if (status & RTK_ISR_SYSTEM_ERR) {
1569 re_init(ifp);
1570 }
1571
1572 if (status & RTK_ISR_LINKCHG) {
1573 callout_stop(&sc->rtk_tick_ch);
1574 re_tick(sc);
1575 }
1576 }
1577
1578 if (handled)
1579 if_schedule_deferred_start(ifp);
1580
1581 rnd_add_uint32(&sc->rnd_source, rndstatus);
1582
1583 return handled;
1584 }
1585
1586
1587
1588 /*
1589 * Main transmit routine for C+ and gigE NICs.
1590 */
1591
1592 static void
1593 re_start(struct ifnet *ifp)
1594 {
1595 struct rtk_softc *sc;
1596 struct mbuf *m;
1597 bus_dmamap_t map;
1598 struct re_txq *txq;
1599 struct re_desc *d;
1600 uint32_t cmdstat, re_flags, vlanctl;
1601 int ofree, idx, error, nsegs, seg;
1602 int startdesc, curdesc, lastdesc;
1603 bool pad;
1604
1605 sc = ifp->if_softc;
1606 ofree = sc->re_ldata.re_txq_free;
1607
1608 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) {
1609
1610 IFQ_POLL(&ifp->if_snd, m);
1611 if (m == NULL)
1612 break;
1613
1614 if (sc->re_ldata.re_txq_free == 0 ||
1615 sc->re_ldata.re_tx_free == 0) {
1616 /* no more free slots left */
1617 ifp->if_flags |= IFF_OACTIVE;
1618 break;
1619 }
1620
1621 /*
1622 * Set up checksum offload. Note: checksum offload bits must
1623 * appear in all descriptors of a multi-descriptor transmit
1624 * attempt. (This is according to testing done with an 8169
1625 * chip. I'm not sure if this is a requirement or a bug.)
1626 */
1627
1628 vlanctl = 0;
1629 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) {
1630 uint32_t segsz = m->m_pkthdr.segsz;
1631
1632 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
1633 re_flags = RE_TDESC_CMD_LGSEND |
1634 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT);
1635 } else {
1636 re_flags = RE_TDESC_CMD_LGSEND_V4;
1637 vlanctl |=
1638 (segsz << RE_TDESC_VLANCTL_MSSVAL_SHIFT);
1639 }
1640 } else {
1641 /*
1642 * set RE_TDESC_CMD_IPCSUM if any checksum offloading
1643 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/
1644 * RE_TDESC_CMD_UDPCSUM doesn't make effects.
1645 */
1646 re_flags = 0;
1647 if ((m->m_pkthdr.csum_flags &
1648 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4))
1649 != 0) {
1650 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) {
1651 re_flags |= RE_TDESC_CMD_IPCSUM;
1652 if (m->m_pkthdr.csum_flags &
1653 M_CSUM_TCPv4) {
1654 re_flags |=
1655 RE_TDESC_CMD_TCPCSUM;
1656 } else if (m->m_pkthdr.csum_flags &
1657 M_CSUM_UDPv4) {
1658 re_flags |=
1659 RE_TDESC_CMD_UDPCSUM;
1660 }
1661 } else {
1662 vlanctl |= RE_TDESC_VLANCTL_IPCSUM;
1663 if (m->m_pkthdr.csum_flags &
1664 M_CSUM_TCPv4) {
1665 vlanctl |=
1666 RE_TDESC_VLANCTL_TCPCSUM;
1667 } else if (m->m_pkthdr.csum_flags &
1668 M_CSUM_UDPv4) {
1669 vlanctl |=
1670 RE_TDESC_VLANCTL_UDPCSUM;
1671 }
1672 }
1673 }
1674 }
1675
1676 txq = &sc->re_ldata.re_txq[idx];
1677 map = txq->txq_dmamap;
1678 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m,
1679 BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1680
1681 if (__predict_false(error)) {
1682 /* XXX try to defrag if EFBIG? */
1683 printf("%s: can't map mbuf (error %d)\n",
1684 device_xname(sc->sc_dev), error);
1685
1686 IFQ_DEQUEUE(&ifp->if_snd, m);
1687 m_freem(m);
1688 if_statinc(ifp, if_oerrors);
1689 continue;
1690 }
1691
1692 nsegs = map->dm_nsegs;
1693 pad = false;
1694 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN &&
1695 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 &&
1696 (sc->sc_quirk & RTKQ_DESCV2) == 0)) {
1697 pad = true;
1698 nsegs++;
1699 }
1700
1701 if (nsegs > sc->re_ldata.re_tx_free) {
1702 /*
1703 * Not enough free descriptors to transmit this packet.
1704 */
1705 ifp->if_flags |= IFF_OACTIVE;
1706 bus_dmamap_unload(sc->sc_dmat, map);
1707 break;
1708 }
1709
1710 IFQ_DEQUEUE(&ifp->if_snd, m);
1711
1712 /*
1713 * Make sure that the caches are synchronized before we
1714 * ask the chip to start DMA for the packet data.
1715 */
1716 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize,
1717 BUS_DMASYNC_PREWRITE);
1718
1719 /*
1720 * Set up hardware VLAN tagging. Note: vlan tag info must
1721 * appear in all descriptors of a multi-descriptor
1722 * transmission attempt.
1723 */
1724 if (vlan_has_tag(m))
1725 vlanctl |= bswap16(vlan_get_tag(m)) |
1726 RE_TDESC_VLANCTL_TAG;
1727
1728 /*
1729 * Map the segment array into descriptors.
1730 * Note that we set the start-of-frame and
1731 * end-of-frame markers for either TX or RX,
1732 * but they really only have meaning in the TX case.
1733 * (In the RX case, it's the chip that tells us
1734 * where packets begin and end.)
1735 * We also keep track of the end of the ring
1736 * and set the end-of-ring bits as needed,
1737 * and we set the ownership bits in all except
1738 * the very first descriptor. (The caller will
1739 * set this descriptor later when it start
1740 * transmission or reception.)
1741 */
1742 curdesc = startdesc = sc->re_ldata.re_tx_nextfree;
1743 lastdesc = -1;
1744 for (seg = 0; seg < map->dm_nsegs;
1745 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) {
1746 d = &sc->re_ldata.re_tx_list[curdesc];
1747 #ifdef DIAGNOSTIC
1748 RE_TXDESCSYNC(sc, curdesc,
1749 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1750 cmdstat = le32toh(d->re_cmdstat);
1751 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD);
1752 if (cmdstat & RE_TDESC_STAT_OWN) {
1753 panic("%s: tried to map busy TX descriptor",
1754 device_xname(sc->sc_dev));
1755 }
1756 #endif
1757
1758 d->re_vlanctl = htole32(vlanctl);
1759 re_set_bufaddr(d, map->dm_segs[seg].ds_addr);
1760 cmdstat = re_flags | map->dm_segs[seg].ds_len;
1761 if (seg == 0)
1762 cmdstat |= RE_TDESC_CMD_SOF;
1763 else
1764 cmdstat |= RE_TDESC_CMD_OWN;
1765 if (curdesc == (RE_TX_DESC_CNT(sc) - 1))
1766 cmdstat |= RE_TDESC_CMD_EOR;
1767 if (seg == nsegs - 1) {
1768 cmdstat |= RE_TDESC_CMD_EOF;
1769 lastdesc = curdesc;
1770 }
1771 d->re_cmdstat = htole32(cmdstat);
1772 RE_TXDESCSYNC(sc, curdesc,
1773 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1774 }
1775 if (__predict_false(pad)) {
1776 d = &sc->re_ldata.re_tx_list[curdesc];
1777 d->re_vlanctl = htole32(vlanctl);
1778 re_set_bufaddr(d, RE_TXPADDADDR(sc));
1779 cmdstat = re_flags |
1780 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF |
1781 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len);
1782 if (curdesc == (RE_TX_DESC_CNT(sc) - 1))
1783 cmdstat |= RE_TDESC_CMD_EOR;
1784 d->re_cmdstat = htole32(cmdstat);
1785 RE_TXDESCSYNC(sc, curdesc,
1786 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1787 lastdesc = curdesc;
1788 curdesc = RE_NEXT_TX_DESC(sc, curdesc);
1789 }
1790 KASSERT(lastdesc != -1);
1791
1792 /* Transfer ownership of packet to the chip. */
1793
1794 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |=
1795 htole32(RE_TDESC_CMD_OWN);
1796 RE_TXDESCSYNC(sc, startdesc,
1797 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1798
1799 /* update info of TX queue and descriptors */
1800 txq->txq_mbuf = m;
1801 txq->txq_descidx = lastdesc;
1802 txq->txq_nsegs = nsegs;
1803
1804 sc->re_ldata.re_txq_free--;
1805 sc->re_ldata.re_tx_free -= nsegs;
1806 sc->re_ldata.re_tx_nextfree = curdesc;
1807
1808 /*
1809 * If there's a BPF listener, bounce a copy of this frame
1810 * to him.
1811 */
1812 bpf_mtap(ifp, m, BPF_D_OUT);
1813 }
1814
1815 if (sc->re_ldata.re_txq_free < ofree) {
1816 /*
1817 * TX packets are enqueued.
1818 */
1819 sc->re_ldata.re_txq_prodidx = idx;
1820
1821 /*
1822 * Start the transmitter to poll.
1823 *
1824 * RealTek put the TX poll request register in a different
1825 * location on the 8169 gigE chip. I don't know why.
1826 */
1827 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0)
1828 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START);
1829 else
1830 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START);
1831
1832 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) {
1833 /*
1834 * Use the countdown timer for interrupt moderation.
1835 * 'TX done' interrupts are disabled. Instead, we reset
1836 * the countdown timer, which will begin counting until
1837 * it hits the value in the TIMERINT register, and then
1838 * trigger an interrupt. Each time we write to the
1839 * TIMERCNT register, the timer count is reset to 0.
1840 */
1841 CSR_WRITE_4(sc, RTK_TIMERCNT, 1);
1842 }
1843
1844 /*
1845 * Set a timeout in case the chip goes out to lunch.
1846 */
1847 ifp->if_timer = 5;
1848 }
1849 }
1850
1851 static int
1852 re_init(struct ifnet *ifp)
1853 {
1854 struct rtk_softc *sc = ifp->if_softc;
1855 uint32_t rxcfg = 0;
1856 uint16_t cfg;
1857 int error;
1858 #ifdef RE_USE_EECMD
1859 const uint8_t *enaddr;
1860 uint32_t reg;
1861 #endif
1862
1863 if ((error = re_enable(sc)) != 0)
1864 goto out;
1865
1866 /*
1867 * Cancel pending I/O and free all RX/TX buffers.
1868 */
1869 re_stop(ifp, 0);
1870
1871 re_reset(sc);
1872
1873 /*
1874 * Enable C+ RX and TX mode, as well as VLAN stripping and
1875 * RX checksum offload. We must configure the C+ register
1876 * before all others.
1877 */
1878 cfg = RE_CPLUSCMD_PCI_MRW;
1879
1880 /*
1881 * XXX: For old 8169 set bit 14.
1882 * For 8169S/8110S and above, do not set bit 14.
1883 */
1884 if ((sc->sc_quirk & RTKQ_8169NONS) != 0)
1885 cfg |= (0x1 << 14);
1886
1887 if ((sc->ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0)
1888 cfg |= RE_CPLUSCMD_VLANSTRIP;
1889 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx |
1890 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0)
1891 cfg |= RE_CPLUSCMD_RXCSUM_ENB;
1892 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) {
1893 cfg |= RE_CPLUSCMD_MACSTAT_DIS;
1894 cfg |= RE_CPLUSCMD_TXENB;
1895 } else
1896 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB;
1897
1898 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg);
1899
1900 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */
1901 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
1902 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) {
1903 CSR_WRITE_2(sc, RTK_IM, 0x0000);
1904 } else {
1905 CSR_WRITE_2(sc, RTK_IM, 0x5151);
1906 }
1907 }
1908
1909 DELAY(10000);
1910
1911 #ifdef RE_USE_EECMD
1912 /*
1913 * Init our MAC address. Even though the chipset
1914 * documentation doesn't mention it, we need to enter "Config
1915 * register write enable" mode to modify the ID registers.
1916 */
1917 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG);
1918 enaddr = CLLADDR(ifp->if_sadl);
1919 reg = enaddr[0] | (enaddr[1] << 8) |
1920 (enaddr[2] << 16) | (enaddr[3] << 24);
1921 CSR_WRITE_4(sc, RTK_IDR0, reg);
1922 reg = enaddr[4] | (enaddr[5] << 8);
1923 CSR_WRITE_4(sc, RTK_IDR4, reg);
1924 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF);
1925 #endif
1926
1927 /*
1928 * For C+ mode, initialize the RX descriptors and mbufs.
1929 */
1930 re_rx_list_init(sc);
1931 re_tx_list_init(sc);
1932
1933 /*
1934 * Load the addresses of the RX and TX lists into the chip.
1935 */
1936 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI,
1937 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr));
1938 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO,
1939 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr));
1940
1941 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI,
1942 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
1943 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO,
1944 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr));
1945
1946 if (sc->sc_quirk & RTKQ_RXDV_GATED) {
1947 CSR_WRITE_4(sc, RTK_MISC,
1948 CSR_READ_4(sc, RTK_MISC) & ~RTK_MISC_RXDV_GATED_EN);
1949 }
1950
1951 /*
1952 * Enable transmit and receive.
1953 */
1954 if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) == 0)
1955 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
1956
1957 /*
1958 * Set the initial TX and RX configuration.
1959 */
1960 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) {
1961 /* test mode is needed only for old 8169 */
1962 CSR_WRITE_4(sc, RTK_TXCFG,
1963 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON);
1964 } else
1965 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG);
1966
1967 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16);
1968
1969 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG);
1970
1971 /* Set the individual bit to receive frames for this host only. */
1972 rxcfg = CSR_READ_4(sc, RTK_RXCFG);
1973 rxcfg |= RTK_RXCFG_RX_INDIV;
1974
1975 /* If we want promiscuous mode, set the allframes bit. */
1976 if (ifp->if_flags & IFF_PROMISC)
1977 rxcfg |= RTK_RXCFG_RX_ALLPHYS;
1978 else
1979 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS;
1980 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1981
1982 /*
1983 * Set capture broadcast bit to capture broadcast frames.
1984 */
1985 if (ifp->if_flags & IFF_BROADCAST)
1986 rxcfg |= RTK_RXCFG_RX_BROAD;
1987 else
1988 rxcfg &= ~RTK_RXCFG_RX_BROAD;
1989 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1990
1991 /*
1992 * Program the multicast filter, if necessary.
1993 */
1994 rtk_setmulti(sc);
1995
1996 /*
1997 * some chips require to enable TX/RX *AFTER* TX/RX configuration
1998 */
1999 if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) != 0)
2000 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
2001
2002 /*
2003 * Enable interrupts.
2004 */
2005 if (sc->re_testmode)
2006 CSR_WRITE_2(sc, RTK_IMR, 0);
2007 else if ((sc->sc_quirk & RTKQ_IM_HW) != 0)
2008 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_IM_HW);
2009 else
2010 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS);
2011
2012 /* Start RX/TX process. */
2013 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0);
2014 #ifdef notdef
2015 /* Enable receiver and transmitter. */
2016 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB);
2017 #endif
2018
2019 /*
2020 * Initialize the timer interrupt register so that
2021 * a timer interrupt will be generated once the timer
2022 * reaches a certain number of ticks. The timer is
2023 * reloaded on each transmit. This gives us TX interrupt
2024 * moderation, which dramatically improves TX frame rate.
2025 */
2026
2027 unsigned defer; /* timer interval / ns */
2028 unsigned period; /* busclock period / ns */
2029
2030 /*
2031 * Maximum frame rate
2032 * 1500 byte PDU -> 81274 Hz
2033 * 46 byte PDU -> 1488096 Hz
2034 *
2035 * Deferring interrupts by up to 128us needs descriptors for
2036 * 1500 byte PDU -> 10.4 frames
2037 * 46 byte PDU -> 190.4 frames
2038 *
2039 */
2040 defer = 128000;
2041
2042 if ((sc->sc_quirk & RTKQ_IM_HW) != 0) {
2043 period = 1;
2044 defer = 0;
2045 } else if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
2046 period = 8;
2047 } else {
2048 switch (CSR_READ_1(sc, RTK_CFG2_BUSFREQ) & 0x7) {
2049 case RTK_BUSFREQ_33MHZ:
2050 period = 30;
2051 break;
2052 case RTK_BUSFREQ_66MHZ:
2053 period = 15;
2054 break;
2055 default:
2056 /* lowest possible clock */
2057 period = 60;
2058 break;
2059 }
2060 }
2061
2062 /* Timer Interrupt register address varies */
2063 uint16_t re8139_reg;
2064 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0)
2065 re8139_reg = RTK_TIMERINT;
2066 else
2067 re8139_reg = RTK_TIMERINT_8169;
2068 CSR_WRITE_4(sc, re8139_reg, defer / period);
2069
2070 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) {
2071 /*
2072 * For 8169 gigE NICs, set the max allowed RX packet
2073 * size so we can receive jumbo frames.
2074 */
2075 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383);
2076 }
2077
2078 if (sc->re_testmode)
2079 return 0;
2080
2081 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD);
2082
2083 ifp->if_flags |= IFF_RUNNING;
2084 ifp->if_flags &= ~IFF_OACTIVE;
2085
2086 callout_schedule(&sc->rtk_tick_ch, hz);
2087
2088 out:
2089 if (error) {
2090 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2091 ifp->if_timer = 0;
2092 printf("%s: interface not running\n",
2093 device_xname(sc->sc_dev));
2094 }
2095
2096 return error;
2097 }
2098
2099 static int
2100 re_ioctl(struct ifnet *ifp, u_long command, void *data)
2101 {
2102 struct rtk_softc *sc = ifp->if_softc;
2103 struct ifreq *ifr = data;
2104 int s, error = 0;
2105
2106 s = splnet();
2107
2108 switch (command) {
2109 case SIOCSIFMTU:
2110 /*
2111 * Disable jumbo frames if it's not supported.
2112 */
2113 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 &&
2114 ifr->ifr_mtu > ETHERMTU) {
2115 error = EINVAL;
2116 break;
2117 }
2118
2119 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO)
2120 error = EINVAL;
2121 else if ((error = ifioctl_common(ifp, command, data)) ==
2122 ENETRESET)
2123 error = 0;
2124 break;
2125 default:
2126 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET)
2127 break;
2128
2129 error = 0;
2130
2131 if (command == SIOCSIFCAP)
2132 error = if_init(ifp);
2133 else if (command != SIOCADDMULTI && command != SIOCDELMULTI)
2134 ;
2135 else if (ifp->if_flags & IFF_RUNNING)
2136 rtk_setmulti(sc);
2137 break;
2138 }
2139
2140 splx(s);
2141
2142 return error;
2143 }
2144
2145 static void
2146 re_watchdog(struct ifnet *ifp)
2147 {
2148 struct rtk_softc *sc;
2149 int s;
2150
2151 sc = ifp->if_softc;
2152 s = splnet();
2153 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
2154 if_statinc(ifp, if_oerrors);
2155
2156 re_txeof(sc);
2157 re_rxeof(sc);
2158
2159 re_init(ifp);
2160
2161 splx(s);
2162 }
2163
2164 /*
2165 * Stop the adapter and free any mbufs allocated to the
2166 * RX and TX lists.
2167 */
2168 static void
2169 re_stop(struct ifnet *ifp, int disable)
2170 {
2171 int i;
2172 struct rtk_softc *sc = ifp->if_softc;
2173
2174 callout_stop(&sc->rtk_tick_ch);
2175
2176 mii_down(&sc->mii);
2177
2178 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0)
2179 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB |
2180 RTK_CMD_RX_ENB);
2181 else
2182 CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
2183 DELAY(1000);
2184 CSR_WRITE_2(sc, RTK_IMR, 0x0000);
2185 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF);
2186
2187 if (sc->re_head != NULL) {
2188 m_freem(sc->re_head);
2189 sc->re_head = sc->re_tail = NULL;
2190 }
2191
2192 /* Free the TX list buffers. */
2193 for (i = 0; i < RE_TX_QLEN; i++) {
2194 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) {
2195 bus_dmamap_unload(sc->sc_dmat,
2196 sc->re_ldata.re_txq[i].txq_dmamap);
2197 m_freem(sc->re_ldata.re_txq[i].txq_mbuf);
2198 sc->re_ldata.re_txq[i].txq_mbuf = NULL;
2199 }
2200 }
2201
2202 /* Free the RX list buffers. */
2203 for (i = 0; i < RE_RX_DESC_CNT; i++) {
2204 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) {
2205 bus_dmamap_unload(sc->sc_dmat,
2206 sc->re_ldata.re_rxsoft[i].rxs_dmamap);
2207 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf);
2208 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL;
2209 }
2210 }
2211
2212 if (disable)
2213 re_disable(sc);
2214
2215 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2216 ifp->if_timer = 0;
2217 }
Cache object: 9657782588870a5c93b001290ab6d56b
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