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sys/dev/ic/rtl81x9.c
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1 /* $NetBSD: rtl81x9.c,v 1.45.4.1 2004/06/21 16:39:00 tron Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400MHz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include <sys/cdefs.h> 89 __KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.45.4.1 2004/06/21 16:39:00 tron Exp $"); 90 91 #include "bpfilter.h" 92 #include "rnd.h" 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/callout.h> 97 #include <sys/device.h> 98 #include <sys/sockio.h> 99 #include <sys/mbuf.h> 100 #include <sys/malloc.h> 101 #include <sys/kernel.h> 102 #include <sys/socket.h> 103 104 #include <uvm/uvm_extern.h> 105 106 #include <net/if.h> 107 #include <net/if_arp.h> 108 #include <net/if_ether.h> 109 #include <net/if_dl.h> 110 #include <net/if_media.h> 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #endif 115 #if NRND > 0 116 #include <sys/rnd.h> 117 #endif 118 119 #include <machine/bus.h> 120 #include <machine/endian.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/ic/rtl81x9reg.h> 126 #include <dev/ic/rtl81x9var.h> 127 128 #if defined(DEBUG) 129 #define STATIC 130 #else 131 #define STATIC static 132 #endif 133 134 STATIC void rtk_reset __P((struct rtk_softc *)); 135 STATIC void rtk_rxeof __P((struct rtk_softc *)); 136 STATIC void rtk_txeof __P((struct rtk_softc *)); 137 STATIC void rtk_start __P((struct ifnet *)); 138 STATIC int rtk_ioctl __P((struct ifnet *, u_long, caddr_t)); 139 STATIC int rtk_init __P((struct ifnet *)); 140 STATIC void rtk_stop __P((struct ifnet *, int)); 141 142 STATIC void rtk_watchdog __P((struct ifnet *)); 143 STATIC void rtk_shutdown __P((void *)); 144 STATIC int rtk_ifmedia_upd __P((struct ifnet *)); 145 STATIC void rtk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 146 147 STATIC void rtk_eeprom_putbyte __P((struct rtk_softc *, int, int)); 148 STATIC void rtk_mii_sync __P((struct rtk_softc *)); 149 STATIC void rtk_mii_send __P((struct rtk_softc *, u_int32_t, int)); 150 STATIC int rtk_mii_readreg __P((struct rtk_softc *, struct rtk_mii_frame *)); 151 STATIC int rtk_mii_writereg __P((struct rtk_softc *, struct rtk_mii_frame *)); 152 153 STATIC int rtk_phy_readreg __P((struct device *, int, int)); 154 STATIC void rtk_phy_writereg __P((struct device *, int, int, int)); 155 STATIC void rtk_phy_statchg __P((struct device *)); 156 STATIC void rtk_tick __P((void *)); 157 158 STATIC int rtk_enable __P((struct rtk_softc *)); 159 STATIC void rtk_disable __P((struct rtk_softc *)); 160 STATIC void rtk_power __P((int, void *)); 161 162 STATIC int rtk_list_tx_init __P((struct rtk_softc *)); 163 164 #define EE_SET(x) \ 165 CSR_WRITE_1(sc, RTK_EECMD, \ 166 CSR_READ_1(sc, RTK_EECMD) | (x)) 167 168 #define EE_CLR(x) \ 169 CSR_WRITE_1(sc, RTK_EECMD, \ 170 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 171 172 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 173 174 /* 175 * Send a read command and address to the EEPROM, check for ACK. 176 */ 177 STATIC void rtk_eeprom_putbyte(sc, addr, addr_len) 178 struct rtk_softc *sc; 179 int addr, addr_len; 180 { 181 int d, i; 182 183 d = (RTK_EECMD_READ << addr_len) | addr; 184 185 /* 186 * Feed in each bit and stobe the clock. 187 */ 188 for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) { 189 if (d & (1 << (i - 1))) { 190 EE_SET(RTK_EE_DATAIN); 191 } else { 192 EE_CLR(RTK_EE_DATAIN); 193 } 194 DELAY(4); 195 EE_SET(RTK_EE_CLK); 196 DELAY(4); 197 EE_CLR(RTK_EE_CLK); 198 DELAY(4); 199 } 200 } 201 202 /* 203 * Read a word of data stored in the EEPROM at address 'addr.' 204 */ 205 u_int16_t rtk_read_eeprom(sc, addr, addr_len) 206 struct rtk_softc *sc; 207 int addr, addr_len; 208 { 209 u_int16_t word = 0; 210 int i; 211 212 /* Enter EEPROM access mode. */ 213 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 214 215 /* 216 * Send address of word we want to read. 217 */ 218 rtk_eeprom_putbyte(sc, addr, addr_len); 219 220 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 221 222 /* 223 * Start reading bits from EEPROM. 224 */ 225 for (i = 16; i > 0; i--) { 226 EE_SET(RTK_EE_CLK); 227 DELAY(4); 228 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 229 word |= 1 << (i - 1); 230 EE_CLR(RTK_EE_CLK); 231 DELAY(4); 232 } 233 234 /* Turn off EEPROM access mode. */ 235 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 236 237 return (word); 238 } 239 240 /* 241 * MII access routines are provided for the 8129, which 242 * doesn't have a built-in PHY. For the 8139, we fake things 243 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 244 * direct access PHY registers. 245 */ 246 #define MII_SET(x) \ 247 CSR_WRITE_1(sc, RTK_MII, \ 248 CSR_READ_1(sc, RTK_MII) | (x)) 249 250 #define MII_CLR(x) \ 251 CSR_WRITE_1(sc, RTK_MII, \ 252 CSR_READ_1(sc, RTK_MII) & ~(x)) 253 254 /* 255 * Sync the PHYs by setting data bit and strobing the clock 32 times. 256 */ 257 STATIC void rtk_mii_sync(sc) 258 struct rtk_softc *sc; 259 { 260 int i; 261 262 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 263 264 for (i = 0; i < 32; i++) { 265 MII_SET(RTK_MII_CLK); 266 DELAY(1); 267 MII_CLR(RTK_MII_CLK); 268 DELAY(1); 269 } 270 } 271 272 /* 273 * Clock a series of bits through the MII. 274 */ 275 STATIC void rtk_mii_send(sc, bits, cnt) 276 struct rtk_softc *sc; 277 u_int32_t bits; 278 int cnt; 279 { 280 int i; 281 282 MII_CLR(RTK_MII_CLK); 283 284 for (i = cnt; i > 0; i--) { 285 if (bits & (1 << (i - 1))) { 286 MII_SET(RTK_MII_DATAOUT); 287 } else { 288 MII_CLR(RTK_MII_DATAOUT); 289 } 290 DELAY(1); 291 MII_CLR(RTK_MII_CLK); 292 DELAY(1); 293 MII_SET(RTK_MII_CLK); 294 } 295 } 296 297 /* 298 * Read an PHY register through the MII. 299 */ 300 STATIC int rtk_mii_readreg(sc, frame) 301 struct rtk_softc *sc; 302 struct rtk_mii_frame *frame; 303 { 304 int i, ack, s; 305 306 s = splnet(); 307 308 /* 309 * Set up frame for RX. 310 */ 311 frame->mii_stdelim = RTK_MII_STARTDELIM; 312 frame->mii_opcode = RTK_MII_READOP; 313 frame->mii_turnaround = 0; 314 frame->mii_data = 0; 315 316 CSR_WRITE_2(sc, RTK_MII, 0); 317 318 /* 319 * Turn on data xmit. 320 */ 321 MII_SET(RTK_MII_DIR); 322 323 rtk_mii_sync(sc); 324 325 /* 326 * Send command/address info. 327 */ 328 rtk_mii_send(sc, frame->mii_stdelim, 2); 329 rtk_mii_send(sc, frame->mii_opcode, 2); 330 rtk_mii_send(sc, frame->mii_phyaddr, 5); 331 rtk_mii_send(sc, frame->mii_regaddr, 5); 332 333 /* Idle bit */ 334 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 335 DELAY(1); 336 MII_SET(RTK_MII_CLK); 337 DELAY(1); 338 339 /* Turn off xmit. */ 340 MII_CLR(RTK_MII_DIR); 341 342 /* Check for ack */ 343 MII_CLR(RTK_MII_CLK); 344 DELAY(1); 345 MII_SET(RTK_MII_CLK); 346 DELAY(1); 347 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 348 349 /* 350 * Now try reading data bits. If the ack failed, we still 351 * need to clock through 16 cycles to keep the PHY(s) in sync. 352 */ 353 if (ack) { 354 for (i = 0; i < 16; i++) { 355 MII_CLR(RTK_MII_CLK); 356 DELAY(1); 357 MII_SET(RTK_MII_CLK); 358 DELAY(1); 359 } 360 goto fail; 361 } 362 363 for (i = 16; i > 0; i--) { 364 MII_CLR(RTK_MII_CLK); 365 DELAY(1); 366 if (!ack) { 367 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 368 frame->mii_data |= 1 << (i - 1); 369 DELAY(1); 370 } 371 MII_SET(RTK_MII_CLK); 372 DELAY(1); 373 } 374 375 fail: 376 MII_CLR(RTK_MII_CLK); 377 DELAY(1); 378 MII_SET(RTK_MII_CLK); 379 DELAY(1); 380 381 splx(s); 382 383 if (ack) 384 return (1); 385 return (0); 386 } 387 388 /* 389 * Write to a PHY register through the MII. 390 */ 391 STATIC int rtk_mii_writereg(sc, frame) 392 struct rtk_softc *sc; 393 struct rtk_mii_frame *frame; 394 { 395 int s; 396 397 s = splnet(); 398 /* 399 * Set up frame for TX. 400 */ 401 frame->mii_stdelim = RTK_MII_STARTDELIM; 402 frame->mii_opcode = RTK_MII_WRITEOP; 403 frame->mii_turnaround = RTK_MII_TURNAROUND; 404 405 /* 406 * Turn on data output. 407 */ 408 MII_SET(RTK_MII_DIR); 409 410 rtk_mii_sync(sc); 411 412 rtk_mii_send(sc, frame->mii_stdelim, 2); 413 rtk_mii_send(sc, frame->mii_opcode, 2); 414 rtk_mii_send(sc, frame->mii_phyaddr, 5); 415 rtk_mii_send(sc, frame->mii_regaddr, 5); 416 rtk_mii_send(sc, frame->mii_turnaround, 2); 417 rtk_mii_send(sc, frame->mii_data, 16); 418 419 /* Idle bit. */ 420 MII_SET(RTK_MII_CLK); 421 DELAY(1); 422 MII_CLR(RTK_MII_CLK); 423 DELAY(1); 424 425 /* 426 * Turn off xmit. 427 */ 428 MII_CLR(RTK_MII_DIR); 429 430 splx(s); 431 432 return (0); 433 } 434 435 STATIC int rtk_phy_readreg(self, phy, reg) 436 struct device *self; 437 int phy, reg; 438 { 439 struct rtk_softc *sc = (void *)self; 440 struct rtk_mii_frame frame; 441 int rval = 0; 442 int rtk8139_reg = 0; 443 444 if (sc->rtk_type == RTK_8139) { 445 if (phy != 7) 446 return (0); 447 448 switch(reg) { 449 case MII_BMCR: 450 rtk8139_reg = RTK_BMCR; 451 break; 452 case MII_BMSR: 453 rtk8139_reg = RTK_BMSR; 454 break; 455 case MII_ANAR: 456 rtk8139_reg = RTK_ANAR; 457 break; 458 case MII_ANER: 459 rtk8139_reg = RTK_ANER; 460 break; 461 case MII_ANLPAR: 462 rtk8139_reg = RTK_LPAR; 463 break; 464 default: 465 #if 0 466 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 467 #endif 468 return (0); 469 } 470 rval = CSR_READ_2(sc, rtk8139_reg); 471 return (rval); 472 } 473 474 memset((char *)&frame, 0, sizeof(frame)); 475 476 frame.mii_phyaddr = phy; 477 frame.mii_regaddr = reg; 478 rtk_mii_readreg(sc, &frame); 479 480 return (frame.mii_data); 481 } 482 483 STATIC void rtk_phy_writereg(self, phy, reg, data) 484 struct device *self; 485 int phy, reg; 486 int data; 487 { 488 struct rtk_softc *sc = (void *)self; 489 struct rtk_mii_frame frame; 490 int rtk8139_reg = 0; 491 492 if (sc->rtk_type == RTK_8139) { 493 if (phy != 7) 494 return; 495 496 switch(reg) { 497 case MII_BMCR: 498 rtk8139_reg = RTK_BMCR; 499 break; 500 case MII_BMSR: 501 rtk8139_reg = RTK_BMSR; 502 break; 503 case MII_ANAR: 504 rtk8139_reg = RTK_ANAR; 505 break; 506 case MII_ANER: 507 rtk8139_reg = RTK_ANER; 508 break; 509 case MII_ANLPAR: 510 rtk8139_reg = RTK_LPAR; 511 break; 512 default: 513 #if 0 514 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 515 #endif 516 return; 517 } 518 CSR_WRITE_2(sc, rtk8139_reg, data); 519 return; 520 } 521 522 memset((char *)&frame, 0, sizeof(frame)); 523 524 frame.mii_phyaddr = phy; 525 frame.mii_regaddr = reg; 526 frame.mii_data = data; 527 528 rtk_mii_writereg(sc, &frame); 529 } 530 531 STATIC void 532 rtk_phy_statchg(v) 533 struct device *v; 534 { 535 536 /* Nothing to do. */ 537 } 538 539 #define rtk_calchash(addr) \ 540 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 541 542 /* 543 * Program the 64-bit multicast hash filter. 544 */ 545 void rtk_setmulti(sc) 546 struct rtk_softc *sc; 547 { 548 struct ifnet *ifp; 549 int h = 0; 550 u_int32_t hashes[2] = { 0, 0 }; 551 u_int32_t rxfilt; 552 int mcnt = 0; 553 struct ether_multi *enm; 554 struct ether_multistep step; 555 556 ifp = &sc->ethercom.ec_if; 557 558 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 559 560 if (ifp->if_flags & IFF_PROMISC) { 561 allmulti: 562 ifp->if_flags |= IFF_ALLMULTI; 563 rxfilt |= RTK_RXCFG_RX_MULTI; 564 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 565 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 566 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 567 return; 568 } 569 570 /* first, zot all the existing hash bits */ 571 CSR_WRITE_4(sc, RTK_MAR0, 0); 572 CSR_WRITE_4(sc, RTK_MAR4, 0); 573 574 /* now program new ones */ 575 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 576 while (enm != NULL) { 577 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 578 ETHER_ADDR_LEN) != 0) 579 goto allmulti; 580 581 h = rtk_calchash(enm->enm_addrlo); 582 if (h < 32) 583 hashes[0] |= (1 << h); 584 else 585 hashes[1] |= (1 << (h - 32)); 586 mcnt++; 587 ETHER_NEXT_MULTI(step, enm); 588 } 589 590 ifp->if_flags &= ~IFF_ALLMULTI; 591 592 if (mcnt) 593 rxfilt |= RTK_RXCFG_RX_MULTI; 594 else 595 rxfilt &= ~RTK_RXCFG_RX_MULTI; 596 597 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 598 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 599 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 600 } 601 602 void rtk_reset(sc) 603 struct rtk_softc *sc; 604 { 605 int i; 606 607 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 608 609 for (i = 0; i < RTK_TIMEOUT; i++) { 610 DELAY(10); 611 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 612 break; 613 } 614 if (i == RTK_TIMEOUT) 615 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 616 } 617 618 /* 619 * Attach the interface. Allocate softc structures, do ifmedia 620 * setup and ethernet/BPF attach. 621 */ 622 void 623 rtk_attach(sc) 624 struct rtk_softc *sc; 625 { 626 struct ifnet *ifp; 627 struct rtk_tx_desc *txd; 628 u_int16_t val; 629 u_int8_t eaddr[ETHER_ADDR_LEN]; 630 int error; 631 int i, addr_len; 632 633 callout_init(&sc->rtk_tick_ch); 634 635 /* 636 * Check EEPROM type 9346 or 9356. 637 */ 638 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 639 addr_len = RTK_EEADDR_LEN1; 640 else 641 addr_len = RTK_EEADDR_LEN0; 642 643 /* 644 * Get station address. 645 */ 646 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 647 eaddr[0] = val & 0xff; 648 eaddr[1] = val >> 8; 649 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 650 eaddr[2] = val & 0xff; 651 eaddr[3] = val >> 8; 652 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 653 eaddr[4] = val & 0xff; 654 eaddr[5] = val >> 8; 655 656 if ((error = bus_dmamem_alloc(sc->sc_dmat, 657 RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 658 BUS_DMA_NOWAIT)) != 0) { 659 printf("%s: can't allocate recv buffer, error = %d\n", 660 sc->sc_dev.dv_xname, error); 661 goto fail_0; 662 } 663 664 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 665 RTK_RXBUFLEN + 16, (caddr_t *)&sc->rtk_rx_buf, 666 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 667 printf("%s: can't map recv buffer, error = %d\n", 668 sc->sc_dev.dv_xname, error); 669 goto fail_1; 670 } 671 672 if ((error = bus_dmamap_create(sc->sc_dmat, 673 RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT, 674 &sc->recv_dmamap)) != 0) { 675 printf("%s: can't create recv buffer DMA map, error = %d\n", 676 sc->sc_dev.dv_xname, error); 677 goto fail_2; 678 } 679 680 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 681 sc->rtk_rx_buf, RTK_RXBUFLEN + 16, 682 NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 683 printf("%s: can't load recv buffer DMA map, error = %d\n", 684 sc->sc_dev.dv_xname, error); 685 goto fail_3; 686 } 687 688 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 689 txd = &sc->rtk_tx_descs[i]; 690 if ((error = bus_dmamap_create(sc->sc_dmat, 691 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 692 &txd->txd_dmamap)) != 0) { 693 printf("%s: can't create snd buffer DMA map," 694 " error = %d\n", sc->sc_dev.dv_xname, error); 695 goto fail_4; 696 } 697 txd->txd_txaddr = RTK_TXADDR0 + (i * 4); 698 txd->txd_txstat = RTK_TXSTAT0 + (i * 4); 699 } 700 SIMPLEQ_INIT(&sc->rtk_tx_free); 701 SIMPLEQ_INIT(&sc->rtk_tx_dirty); 702 703 /* 704 * From this point forward, the attachment cannot fail. A failure 705 * before this releases all resources thar may have been 706 * allocated. 707 */ 708 sc->sc_flags |= RTK_ATTACHED; 709 710 /* Init Early TX threshold. */ 711 sc->sc_txthresh = TXTH_256; 712 713 /* Reset the adapter. */ 714 rtk_reset(sc); 715 716 printf("%s: Ethernet address %s\n", 717 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 718 719 ifp = &sc->ethercom.ec_if; 720 ifp->if_softc = sc; 721 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 722 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 723 ifp->if_ioctl = rtk_ioctl; 724 ifp->if_start = rtk_start; 725 ifp->if_watchdog = rtk_watchdog; 726 ifp->if_init = rtk_init; 727 ifp->if_stop = rtk_stop; 728 IFQ_SET_READY(&ifp->if_snd); 729 730 /* 731 * Do ifmedia setup. 732 */ 733 sc->mii.mii_ifp = ifp; 734 sc->mii.mii_readreg = rtk_phy_readreg; 735 sc->mii.mii_writereg = rtk_phy_writereg; 736 sc->mii.mii_statchg = rtk_phy_statchg; 737 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, rtk_ifmedia_upd, rtk_ifmedia_sts); 738 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 739 MII_PHY_ANY, MII_OFFSET_ANY, 0); 740 741 /* Choose a default media. */ 742 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 743 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 744 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 745 } else { 746 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 747 } 748 749 /* 750 * Call MI attach routines. 751 */ 752 if_attach(ifp); 753 ether_ifattach(ifp, eaddr); 754 755 /* 756 * Make sure the interface is shutdown during reboot. 757 */ 758 sc->sc_sdhook = shutdownhook_establish(rtk_shutdown, sc); 759 if (sc->sc_sdhook == NULL) 760 printf("%s: WARNING: unable to establish shutdown hook\n", 761 sc->sc_dev.dv_xname); 762 /* 763 * Add a suspend hook to make sure we come back up after a 764 * resume. 765 */ 766 sc->sc_powerhook = powerhook_establish(rtk_power, sc); 767 if (sc->sc_powerhook == NULL) 768 printf("%s: WARNING: unable to establish power hook\n", 769 sc->sc_dev.dv_xname); 770 771 return; 772 fail_4: 773 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 774 txd = &sc->rtk_tx_descs[i]; 775 if (txd->txd_dmamap != NULL) 776 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 777 } 778 fail_3: 779 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 780 fail_2: 781 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 782 RTK_RXBUFLEN + 16); 783 fail_1: 784 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 785 fail_0: 786 return; 787 } 788 789 /* 790 * Initialize the transmit descriptors. 791 */ 792 STATIC int rtk_list_tx_init(sc) 793 struct rtk_softc *sc; 794 { 795 struct rtk_tx_desc *txd; 796 int i; 797 798 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) 799 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 800 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) 801 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 802 803 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 804 txd = &sc->rtk_tx_descs[i]; 805 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 806 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 807 } 808 809 return (0); 810 } 811 812 /* 813 * rtk_activate: 814 * Handle device activation/deactivation requests. 815 */ 816 int 817 rtk_activate(self, act) 818 struct device *self; 819 enum devact act; 820 { 821 struct rtk_softc *sc = (void *) self; 822 int s, error = 0; 823 824 s = splnet(); 825 switch (act) { 826 case DVACT_ACTIVATE: 827 error = EOPNOTSUPP; 828 break; 829 case DVACT_DEACTIVATE: 830 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 831 if_deactivate(&sc->ethercom.ec_if); 832 break; 833 } 834 splx(s); 835 836 return (error); 837 } 838 839 /* 840 * rtk_detach: 841 * Detach a rtk interface. 842 */ 843 int 844 rtk_detach(sc) 845 struct rtk_softc *sc; 846 { 847 struct ifnet *ifp = &sc->ethercom.ec_if; 848 struct rtk_tx_desc *txd; 849 int i; 850 851 /* 852 * Succeed now if there isn't any work to do. 853 */ 854 if ((sc->sc_flags & RTK_ATTACHED) == 0) 855 return (0); 856 857 /* Unhook our tick handler. */ 858 callout_stop(&sc->rtk_tick_ch); 859 860 /* Detach all PHYs. */ 861 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 862 863 /* Delete all remaining media. */ 864 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 865 866 ether_ifdetach(ifp); 867 if_detach(ifp); 868 869 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 870 txd = &sc->rtk_tx_descs[i]; 871 if (txd->txd_dmamap != NULL) 872 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 873 } 874 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 875 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 876 RTK_RXBUFLEN + 16); 877 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 878 879 shutdownhook_disestablish(sc->sc_sdhook); 880 powerhook_disestablish(sc->sc_powerhook); 881 882 return (0); 883 } 884 885 /* 886 * rtk_enable: 887 * Enable the RTL81X9 chip. 888 */ 889 int 890 rtk_enable(sc) 891 struct rtk_softc *sc; 892 { 893 894 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 895 if ((*sc->sc_enable)(sc) != 0) { 896 printf("%s: device enable failed\n", 897 sc->sc_dev.dv_xname); 898 return (EIO); 899 } 900 sc->sc_flags |= RTK_ENABLED; 901 } 902 return (0); 903 } 904 905 /* 906 * rtk_disable: 907 * Disable the RTL81X9 chip. 908 */ 909 void 910 rtk_disable(sc) 911 struct rtk_softc *sc; 912 { 913 914 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 915 (*sc->sc_disable)(sc); 916 sc->sc_flags &= ~RTK_ENABLED; 917 } 918 } 919 920 /* 921 * rtk_power: 922 * Power management (suspend/resume) hook. 923 */ 924 void 925 rtk_power(why, arg) 926 int why; 927 void *arg; 928 { 929 struct rtk_softc *sc = (void *) arg; 930 struct ifnet *ifp = &sc->ethercom.ec_if; 931 int s; 932 933 s = splnet(); 934 switch (why) { 935 case PWR_SUSPEND: 936 case PWR_STANDBY: 937 rtk_stop(ifp, 0); 938 if (sc->sc_power != NULL) 939 (*sc->sc_power)(sc, why); 940 break; 941 case PWR_RESUME: 942 if (ifp->if_flags & IFF_UP) { 943 if (sc->sc_power != NULL) 944 (*sc->sc_power)(sc, why); 945 rtk_init(ifp); 946 } 947 break; 948 case PWR_SOFTSUSPEND: 949 case PWR_SOFTSTANDBY: 950 case PWR_SOFTRESUME: 951 break; 952 } 953 splx(s); 954 } 955 956 /* 957 * A frame has been uploaded: pass the resulting mbuf chain up to 958 * the higher level protocols. 959 * 960 * You know there's something wrong with a PCI bus-master chip design. 961 * 962 * The receive operation is badly documented in the datasheet, so I'll 963 * attempt to document it here. The driver provides a buffer area and 964 * places its base address in the RX buffer start address register. 965 * The chip then begins copying frames into the RX buffer. Each frame 966 * is preceded by a 32-bit RX status word which specifies the length 967 * of the frame and certain other status bits. Each frame (starting with 968 * the status word) is also 32-bit aligned. The frame length is in the 969 * first 16 bits of the status word; the lower 15 bits correspond with 970 * the 'rx status register' mentioned in the datasheet. 971 * 972 * Note: to make the Alpha happy, the frame payload needs to be aligned 973 * on a 32-bit boundary. To achieve this, we copy the data to mbuf 974 * shifted forward 2 bytes. 975 */ 976 STATIC void rtk_rxeof(sc) 977 struct rtk_softc *sc; 978 { 979 struct mbuf *m; 980 struct ifnet *ifp; 981 caddr_t rxbufpos, dst; 982 u_int total_len, wrap = 0; 983 u_int32_t rxstat; 984 u_int16_t cur_rx, new_rx; 985 u_int16_t limit; 986 u_int16_t rx_bytes = 0, max_bytes; 987 988 ifp = &sc->ethercom.ec_if; 989 990 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 991 992 /* Do not try to read past this point. */ 993 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 994 995 if (limit < cur_rx) 996 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 997 else 998 max_bytes = limit - cur_rx; 999 1000 while((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 1001 rxbufpos = sc->rtk_rx_buf + cur_rx; 1002 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1003 RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD); 1004 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1005 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1006 RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD); 1007 1008 /* 1009 * Here's a totally undocumented fact for you. When the 1010 * RealTek chip is in the process of copying a packet into 1011 * RAM for you, the length will be 0xfff0. If you spot a 1012 * packet header with this value, you need to stop. The 1013 * datasheet makes absolutely no mention of this and 1014 * RealTek should be shot for this. 1015 */ 1016 total_len = rxstat >> 16; 1017 if (total_len == RTK_RXSTAT_UNFINISHED) 1018 break; 1019 1020 if ((rxstat & RTK_RXSTAT_RXOK) == 0 || 1021 total_len > ETHER_MAX_LEN) { 1022 ifp->if_ierrors++; 1023 1024 /* 1025 * submitted by:[netbsd-pcmcia:00484] 1026 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp> 1027 * obtain from: 1028 * FreeBSD if_rl.c rev 1.24->1.25 1029 * 1030 */ 1031 #if 0 1032 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1033 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1034 RTK_RXSTAT_ALIGNERR)) { 1035 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 1036 CSR_WRITE_2(sc, RTK_COMMAND, 1037 RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1038 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1039 CSR_WRITE_4(sc, RTK_RXADDR, 1040 sc->recv_dmamap->dm_segs[0].ds_addr); 1041 cur_rx = 0; 1042 } 1043 break; 1044 #else 1045 rtk_init(ifp); 1046 return; 1047 #endif 1048 } 1049 1050 /* No errors; receive the packet. */ 1051 rx_bytes += total_len + RTK_RXSTAT_LEN; 1052 1053 /* 1054 * Avoid trying to read more bytes than we know 1055 * the chip has prepared for us. 1056 */ 1057 if (rx_bytes > max_bytes) 1058 break; 1059 1060 /* 1061 * Skip the status word, wrapping around to the beginning 1062 * of the Rx area, if necessary. 1063 */ 1064 cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN; 1065 rxbufpos = sc->rtk_rx_buf + cur_rx; 1066 1067 /* 1068 * Compute the number of bytes at which the packet 1069 * will wrap to the beginning of the ring buffer. 1070 */ 1071 wrap = RTK_RXBUFLEN - cur_rx; 1072 1073 /* 1074 * Compute where the next pending packet is. 1075 */ 1076 if (total_len > wrap) 1077 new_rx = total_len - wrap; 1078 else 1079 new_rx = cur_rx + total_len; 1080 /* Round up to 32-bit boundary. */ 1081 new_rx = (new_rx + 3) & ~3; 1082 1083 /* 1084 * Now allocate an mbuf (and possibly a cluster) to hold 1085 * the packet. Note we offset the packet 2 bytes so that 1086 * data after the Ethernet header will be 4-byte aligned. 1087 */ 1088 MGETHDR(m, M_DONTWAIT, MT_DATA); 1089 if (m == NULL) { 1090 printf("%s: unable to allocate Rx mbuf\n", 1091 sc->sc_dev.dv_xname); 1092 ifp->if_ierrors++; 1093 goto next_packet; 1094 } 1095 if (total_len > (MHLEN - RTK_ETHER_ALIGN)) { 1096 MCLGET(m, M_DONTWAIT); 1097 if ((m->m_flags & M_EXT) == 0) { 1098 printf("%s: unable to allocate Rx cluster\n", 1099 sc->sc_dev.dv_xname); 1100 ifp->if_ierrors++; 1101 m_freem(m); 1102 m = NULL; 1103 goto next_packet; 1104 } 1105 } 1106 m->m_data += RTK_ETHER_ALIGN; /* for alignment */ 1107 m->m_pkthdr.rcvif = ifp; 1108 m->m_pkthdr.len = m->m_len = total_len; 1109 dst = mtod(m, caddr_t); 1110 1111 /* 1112 * If the packet wraps, copy up to the wrapping point. 1113 */ 1114 if (total_len > wrap) { 1115 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1116 cur_rx, wrap, BUS_DMASYNC_POSTREAD); 1117 memcpy(dst, rxbufpos, wrap); 1118 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1119 cur_rx, wrap, BUS_DMASYNC_PREREAD); 1120 cur_rx = 0; 1121 rxbufpos = sc->rtk_rx_buf; 1122 total_len -= wrap; 1123 dst += wrap; 1124 } 1125 1126 /* 1127 * ...and now the rest. 1128 */ 1129 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1130 cur_rx, total_len, BUS_DMASYNC_POSTREAD); 1131 memcpy(dst, rxbufpos, total_len); 1132 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1133 cur_rx, total_len, BUS_DMASYNC_PREREAD); 1134 1135 next_packet: 1136 CSR_WRITE_2(sc, RTK_CURRXADDR, new_rx - 16); 1137 cur_rx = new_rx; 1138 1139 if (m == NULL) 1140 continue; 1141 1142 /* 1143 * The RealTek chip includes the CRC with every 1144 * incoming packet. 1145 */ 1146 m->m_flags |= M_HASFCS; 1147 1148 ifp->if_ipackets++; 1149 1150 #if NBPFILTER > 0 1151 if (ifp->if_bpf) 1152 bpf_mtap(ifp->if_bpf, m); 1153 #endif 1154 /* pass it on. */ 1155 (*ifp->if_input)(ifp, m); 1156 } 1157 } 1158 1159 /* 1160 * A frame was downloaded to the chip. It's safe for us to clean up 1161 * the list buffers. 1162 */ 1163 STATIC void rtk_txeof(sc) 1164 struct rtk_softc *sc; 1165 { 1166 struct ifnet *ifp; 1167 struct rtk_tx_desc *txd; 1168 u_int32_t txstat; 1169 1170 ifp = &sc->ethercom.ec_if; 1171 1172 /* Clear the timeout timer. */ 1173 ifp->if_timer = 0; 1174 1175 /* 1176 * Go through our tx list and free mbufs for those 1177 * frames that have been uploaded. 1178 */ 1179 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1180 txstat = CSR_READ_4(sc, txd->txd_txstat); 1181 if ((txstat & (RTK_TXSTAT_TX_OK| 1182 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0) 1183 break; 1184 1185 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1186 1187 bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0, 1188 txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1189 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1190 m_freem(txd->txd_mbuf); 1191 txd->txd_mbuf = NULL; 1192 1193 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1194 1195 if (txstat & RTK_TXSTAT_TX_OK) 1196 ifp->if_opackets++; 1197 else { 1198 ifp->if_oerrors++; 1199 1200 /* 1201 * Increase Early TX threshold if underrun occurred. 1202 * Increase step 64 bytes. 1203 */ 1204 if (txstat & RTK_TXSTAT_TX_UNDERRUN) { 1205 printf("%s: transmit underrun;", 1206 sc->sc_dev.dv_xname); 1207 if (sc->sc_txthresh < TXTH_MAX) { 1208 sc->sc_txthresh += 2; 1209 printf(" new threshold: %d bytes", 1210 sc->sc_txthresh * 32); 1211 } 1212 printf("\n"); 1213 } 1214 if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN)) 1215 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1216 } 1217 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 1218 ifp->if_flags &= ~IFF_OACTIVE; 1219 } 1220 } 1221 1222 int rtk_intr(arg) 1223 void *arg; 1224 { 1225 struct rtk_softc *sc; 1226 struct ifnet *ifp; 1227 u_int16_t status; 1228 int handled = 0; 1229 1230 sc = arg; 1231 ifp = &sc->ethercom.ec_if; 1232 1233 /* Disable interrupts. */ 1234 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1235 1236 for (;;) { 1237 1238 status = CSR_READ_2(sc, RTK_ISR); 1239 if (status) 1240 CSR_WRITE_2(sc, RTK_ISR, status); 1241 1242 handled = 1; 1243 1244 if ((status & RTK_INTRS) == 0) 1245 break; 1246 1247 if (status & RTK_ISR_RX_OK) 1248 rtk_rxeof(sc); 1249 1250 if (status & RTK_ISR_RX_ERR) 1251 rtk_rxeof(sc); 1252 1253 if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR)) 1254 rtk_txeof(sc); 1255 1256 if (status & RTK_ISR_SYSTEM_ERR) { 1257 rtk_reset(sc); 1258 rtk_init(ifp); 1259 } 1260 } 1261 1262 /* Re-enable interrupts. */ 1263 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1264 1265 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1266 rtk_start(ifp); 1267 1268 return (handled); 1269 } 1270 1271 /* 1272 * Main transmit routine. 1273 */ 1274 1275 STATIC void rtk_start(ifp) 1276 struct ifnet *ifp; 1277 { 1278 struct rtk_softc *sc; 1279 struct rtk_tx_desc *txd; 1280 struct mbuf *m_head = NULL, *m_new; 1281 int error, len; 1282 1283 sc = ifp->if_softc; 1284 1285 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) { 1286 IFQ_POLL(&ifp->if_snd, m_head); 1287 if (m_head == NULL) 1288 break; 1289 m_new = NULL; 1290 1291 /* 1292 * Load the DMA map. If this fails, the packet didn't 1293 * fit in one DMA segment, and we need to copy. Note, 1294 * the packet must also be aligned. 1295 * if the packet is too small, copy it too, so we're sure 1296 * so have enouth room for the pad buffer. 1297 */ 1298 if ((mtod(m_head, uintptr_t) & 3) != 0 || 1299 m_head->m_pkthdr.len < ETHER_PAD_LEN || 1300 bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap, 1301 m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1302 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1303 if (m_new == NULL) { 1304 printf("%s: unable to allocate Tx mbuf\n", 1305 sc->sc_dev.dv_xname); 1306 break; 1307 } 1308 if (m_head->m_pkthdr.len > MHLEN) { 1309 MCLGET(m_new, M_DONTWAIT); 1310 if ((m_new->m_flags & M_EXT) == 0) { 1311 printf("%s: unable to allocate Tx " 1312 "cluster\n", sc->sc_dev.dv_xname); 1313 m_freem(m_new); 1314 break; 1315 } 1316 } 1317 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1318 mtod(m_new, caddr_t)); 1319 m_new->m_pkthdr.len = m_new->m_len = 1320 m_head->m_pkthdr.len; 1321 if (m_head->m_pkthdr.len < ETHER_PAD_LEN) { 1322 memset( 1323 mtod(m_new, caddr_t) + m_head->m_pkthdr.len, 1324 0, ETHER_PAD_LEN - m_head->m_pkthdr.len); 1325 m_new->m_pkthdr.len = m_new->m_len = 1326 ETHER_PAD_LEN; 1327 } 1328 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1329 txd->txd_dmamap, m_new, 1330 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1331 if (error) { 1332 printf("%s: unable to load Tx buffer, " 1333 "error = %d\n", sc->sc_dev.dv_xname, error); 1334 break; 1335 } 1336 } 1337 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1338 #if NBPFILTER > 0 1339 /* 1340 * If there's a BPF listener, bounce a copy of this frame 1341 * to him. 1342 */ 1343 if (ifp->if_bpf) 1344 bpf_mtap(ifp->if_bpf, m_head); 1345 #endif 1346 if (m_new != NULL) { 1347 m_freem(m_head); 1348 m_head = m_new; 1349 } 1350 txd->txd_mbuf = m_head; 1351 1352 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 1353 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q); 1354 1355 /* 1356 * Transmit the frame. 1357 */ 1358 bus_dmamap_sync(sc->sc_dmat, 1359 txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize, 1360 BUS_DMASYNC_PREWRITE); 1361 1362 len = txd->txd_dmamap->dm_segs[0].ds_len; 1363 1364 CSR_WRITE_4(sc, txd->txd_txaddr, 1365 txd->txd_dmamap->dm_segs[0].ds_addr); 1366 CSR_WRITE_4(sc, txd->txd_txstat, RTK_TX_THRESH(sc) | len); 1367 } 1368 1369 /* 1370 * We broke out of the loop because all our TX slots are 1371 * full. Mark the NIC as busy until it drains some of the 1372 * packets from the queue. 1373 */ 1374 if (SIMPLEQ_EMPTY(&sc->rtk_tx_free)) 1375 ifp->if_flags |= IFF_OACTIVE; 1376 1377 /* 1378 * Set a timeout in case the chip goes out to lunch. 1379 */ 1380 ifp->if_timer = 5; 1381 } 1382 1383 STATIC int rtk_init(ifp) 1384 struct ifnet *ifp; 1385 { 1386 struct rtk_softc *sc = ifp->if_softc; 1387 int error = 0, i; 1388 u_int32_t rxcfg; 1389 1390 if ((error = rtk_enable(sc)) != 0) 1391 goto out; 1392 1393 /* 1394 * Cancel pending I/O. 1395 */ 1396 rtk_stop(ifp, 0); 1397 1398 /* Init our MAC address */ 1399 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1400 CSR_WRITE_1(sc, RTK_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1401 } 1402 1403 /* Init the RX buffer pointer register. */ 1404 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1405 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1406 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1407 1408 /* Init TX descriptors. */ 1409 rtk_list_tx_init(sc); 1410 1411 /* Init Early TX threshold. */ 1412 sc->sc_txthresh = TXTH_256; 1413 /* 1414 * Enable transmit and receive. 1415 */ 1416 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1417 1418 /* 1419 * Set the initial TX and RX configuration. 1420 */ 1421 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1422 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1423 1424 /* Set the individual bit to receive frames for this host only. */ 1425 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1426 rxcfg |= RTK_RXCFG_RX_INDIV; 1427 1428 /* If we want promiscuous mode, set the allframes bit. */ 1429 if (ifp->if_flags & IFF_PROMISC) { 1430 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1431 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1432 } else { 1433 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1434 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1435 } 1436 1437 /* 1438 * Set capture broadcast bit to capture broadcast frames. 1439 */ 1440 if (ifp->if_flags & IFF_BROADCAST) { 1441 rxcfg |= RTK_RXCFG_RX_BROAD; 1442 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1443 } else { 1444 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1445 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1446 } 1447 1448 /* 1449 * Program the multicast filter, if necessary. 1450 */ 1451 rtk_setmulti(sc); 1452 1453 /* 1454 * Enable interrupts. 1455 */ 1456 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1457 1458 /* Start RX/TX process. */ 1459 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1460 1461 /* Enable receiver and transmitter. */ 1462 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1463 1464 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1465 1466 /* 1467 * Set current media. 1468 */ 1469 mii_mediachg(&sc->mii); 1470 1471 ifp->if_flags |= IFF_RUNNING; 1472 ifp->if_flags &= ~IFF_OACTIVE; 1473 1474 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1475 1476 out: 1477 if (error) { 1478 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1479 ifp->if_timer = 0; 1480 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1481 } 1482 return (error); 1483 } 1484 1485 /* 1486 * Set media options. 1487 */ 1488 STATIC int rtk_ifmedia_upd(ifp) 1489 struct ifnet *ifp; 1490 { 1491 struct rtk_softc *sc; 1492 1493 sc = ifp->if_softc; 1494 1495 return (mii_mediachg(&sc->mii)); 1496 } 1497 1498 /* 1499 * Report current media status. 1500 */ 1501 STATIC void rtk_ifmedia_sts(ifp, ifmr) 1502 struct ifnet *ifp; 1503 struct ifmediareq *ifmr; 1504 { 1505 struct rtk_softc *sc; 1506 1507 sc = ifp->if_softc; 1508 1509 mii_pollstat(&sc->mii); 1510 ifmr->ifm_status = sc->mii.mii_media_status; 1511 ifmr->ifm_active = sc->mii.mii_media_active; 1512 } 1513 1514 STATIC int rtk_ioctl(ifp, command, data) 1515 struct ifnet *ifp; 1516 u_long command; 1517 caddr_t data; 1518 { 1519 struct rtk_softc *sc = ifp->if_softc; 1520 struct ifreq *ifr = (struct ifreq *) data; 1521 int s, error = 0; 1522 1523 s = splnet(); 1524 1525 switch (command) { 1526 case SIOCGIFMEDIA: 1527 case SIOCSIFMEDIA: 1528 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1529 break; 1530 1531 default: 1532 error = ether_ioctl(ifp, command, data); 1533 if (error == ENETRESET) { 1534 if (RTK_IS_ENABLED(sc)) { 1535 /* 1536 * Multicast list has changed. Set the 1537 * hardware filter accordingly. 1538 */ 1539 rtk_setmulti(sc); 1540 } 1541 error = 0; 1542 } 1543 break; 1544 } 1545 1546 splx(s); 1547 1548 return (error); 1549 } 1550 1551 STATIC void rtk_watchdog(ifp) 1552 struct ifnet *ifp; 1553 { 1554 struct rtk_softc *sc; 1555 1556 sc = ifp->if_softc; 1557 1558 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1559 ifp->if_oerrors++; 1560 rtk_txeof(sc); 1561 rtk_rxeof(sc); 1562 rtk_init(ifp); 1563 } 1564 1565 /* 1566 * Stop the adapter and free any mbufs allocated to the 1567 * RX and TX lists. 1568 */ 1569 STATIC void rtk_stop(ifp, disable) 1570 struct ifnet *ifp; 1571 int disable; 1572 { 1573 struct rtk_softc *sc = ifp->if_softc; 1574 struct rtk_tx_desc *txd; 1575 1576 callout_stop(&sc->rtk_tick_ch); 1577 1578 mii_down(&sc->mii); 1579 1580 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1581 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1582 1583 /* 1584 * Free the TX list buffers. 1585 */ 1586 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1587 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1588 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1589 m_freem(txd->txd_mbuf); 1590 txd->txd_mbuf = NULL; 1591 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 1592 } 1593 1594 if (disable) 1595 rtk_disable(sc); 1596 1597 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1598 ifp->if_timer = 0; 1599 } 1600 1601 /* 1602 * Stop all chip I/O so that the kernel's probe routines don't 1603 * get confused by errant DMAs when rebooting. 1604 */ 1605 STATIC void rtk_shutdown(vsc) 1606 void *vsc; 1607 { 1608 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1609 1610 rtk_stop(&sc->ethercom.ec_if, 0); 1611 } 1612 1613 STATIC void 1614 rtk_tick(arg) 1615 void *arg; 1616 { 1617 struct rtk_softc *sc = arg; 1618 int s = splnet(); 1619 1620 mii_tick(&sc->mii); 1621 splx(s); 1622 1623 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1624 }
Cache object: 40847d65382b2c3435854c9d441fc0ca
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