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sys/dev/ic/rtl81x9.c
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1 /* $NetBSD: rtl81x9.c,v 1.51.2.2 2007/10/04 18:50:23 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400MHz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include <sys/cdefs.h> 89 __KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.51.2.2 2007/10/04 18:50:23 bouyer Exp $"); 90 91 #include "bpfilter.h" 92 #include "rnd.h" 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/callout.h> 97 #include <sys/device.h> 98 #include <sys/sockio.h> 99 #include <sys/mbuf.h> 100 #include <sys/malloc.h> 101 #include <sys/kernel.h> 102 #include <sys/socket.h> 103 104 #include <uvm/uvm_extern.h> 105 106 #include <net/if.h> 107 #include <net/if_arp.h> 108 #include <net/if_ether.h> 109 #include <net/if_dl.h> 110 #include <net/if_media.h> 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #endif 115 #if NRND > 0 116 #include <sys/rnd.h> 117 #endif 118 119 #include <machine/bus.h> 120 #include <machine/endian.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/ic/rtl81x9reg.h> 126 #include <dev/ic/rtl81x9var.h> 127 128 #if defined(DEBUG) 129 #define STATIC 130 #else 131 #define STATIC static 132 #endif 133 134 STATIC void rtk_reset(struct rtk_softc *); 135 STATIC void rtk_rxeof(struct rtk_softc *); 136 STATIC void rtk_txeof(struct rtk_softc *); 137 STATIC void rtk_start(struct ifnet *); 138 STATIC int rtk_ioctl(struct ifnet *, u_long, caddr_t); 139 STATIC int rtk_init(struct ifnet *); 140 STATIC void rtk_stop(struct ifnet *, int); 141 142 STATIC void rtk_watchdog(struct ifnet *); 143 STATIC void rtk_shutdown(void *); 144 STATIC int rtk_ifmedia_upd(struct ifnet *); 145 STATIC void rtk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 146 147 STATIC void rtk_eeprom_putbyte(struct rtk_softc *, int, int); 148 STATIC void rtk_mii_sync(struct rtk_softc *); 149 STATIC void rtk_mii_send(struct rtk_softc *, uint32_t, int); 150 STATIC int rtk_mii_readreg(struct rtk_softc *, struct rtk_mii_frame *); 151 STATIC int rtk_mii_writereg(struct rtk_softc *, struct rtk_mii_frame *); 152 153 STATIC int rtk_phy_readreg(struct device *, int, int); 154 STATIC void rtk_phy_writereg(struct device *, int, int, int); 155 STATIC void rtk_phy_statchg(struct device *); 156 STATIC void rtk_tick(void *); 157 158 STATIC int rtk_enable(struct rtk_softc *); 159 STATIC void rtk_disable(struct rtk_softc *); 160 STATIC void rtk_power(int, void *); 161 162 STATIC int rtk_list_tx_init(struct rtk_softc *); 163 164 #define EE_SET(x) \ 165 CSR_WRITE_1(sc, RTK_EECMD, \ 166 CSR_READ_1(sc, RTK_EECMD) | (x)) 167 168 #define EE_CLR(x) \ 169 CSR_WRITE_1(sc, RTK_EECMD, \ 170 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 171 172 #define EE_DELAY() DELAY(100) 173 174 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 175 176 /* 177 * Send a read command and address to the EEPROM, check for ACK. 178 */ 179 STATIC void 180 rtk_eeprom_putbyte(struct rtk_softc *sc, int addr, int addr_len) 181 { 182 int d, i; 183 184 d = (RTK_EECMD_READ << addr_len) | addr; 185 186 /* 187 * Feed in each bit and stobe the clock. 188 */ 189 for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) { 190 if (d & (1 << (i - 1))) { 191 EE_SET(RTK_EE_DATAIN); 192 } else { 193 EE_CLR(RTK_EE_DATAIN); 194 } 195 EE_DELAY(); 196 EE_SET(RTK_EE_CLK); 197 EE_DELAY(); 198 EE_CLR(RTK_EE_CLK); 199 EE_DELAY(); 200 } 201 } 202 203 /* 204 * Read a word of data stored in the EEPROM at address 'addr.' 205 */ 206 uint16_t 207 rtk_read_eeprom(struct rtk_softc *sc, int addr, int addr_len) 208 { 209 uint16_t word; 210 int i; 211 212 /* Enter EEPROM access mode. */ 213 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM); 214 EE_DELAY(); 215 EE_SET(RTK_EE_SEL); 216 217 /* 218 * Send address of word we want to read. 219 */ 220 rtk_eeprom_putbyte(sc, addr, addr_len); 221 222 /* 223 * Start reading bits from EEPROM. 224 */ 225 word = 0; 226 for (i = 16; i > 0; i--) { 227 EE_SET(RTK_EE_CLK); 228 EE_DELAY(); 229 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 230 word |= 1 << (i - 1); 231 EE_CLR(RTK_EE_CLK); 232 EE_DELAY(); 233 } 234 235 /* Turn off EEPROM access mode. */ 236 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 237 238 return word; 239 } 240 241 /* 242 * MII access routines are provided for the 8129, which 243 * doesn't have a built-in PHY. For the 8139, we fake things 244 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 245 * direct access PHY registers. 246 */ 247 #define MII_SET(x) \ 248 CSR_WRITE_1(sc, RTK_MII, \ 249 CSR_READ_1(sc, RTK_MII) | (x)) 250 251 #define MII_CLR(x) \ 252 CSR_WRITE_1(sc, RTK_MII, \ 253 CSR_READ_1(sc, RTK_MII) & ~(x)) 254 255 /* 256 * Sync the PHYs by setting data bit and strobing the clock 32 times. 257 */ 258 STATIC void 259 rtk_mii_sync(struct rtk_softc *sc) 260 { 261 int i; 262 263 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 264 265 for (i = 0; i < 32; i++) { 266 MII_SET(RTK_MII_CLK); 267 DELAY(1); 268 MII_CLR(RTK_MII_CLK); 269 DELAY(1); 270 } 271 } 272 273 /* 274 * Clock a series of bits through the MII. 275 */ 276 STATIC void 277 rtk_mii_send(struct rtk_softc *sc, uint32_t bits, int cnt) 278 { 279 int i; 280 281 MII_CLR(RTK_MII_CLK); 282 283 for (i = cnt; i > 0; i--) { 284 if (bits & (1 << (i - 1))) { 285 MII_SET(RTK_MII_DATAOUT); 286 } else { 287 MII_CLR(RTK_MII_DATAOUT); 288 } 289 DELAY(1); 290 MII_CLR(RTK_MII_CLK); 291 DELAY(1); 292 MII_SET(RTK_MII_CLK); 293 } 294 } 295 296 /* 297 * Read an PHY register through the MII. 298 */ 299 STATIC int 300 rtk_mii_readreg(struct rtk_softc *sc, struct rtk_mii_frame *frame) 301 { 302 int i, ack, s; 303 304 s = splnet(); 305 306 /* 307 * Set up frame for RX. 308 */ 309 frame->mii_stdelim = RTK_MII_STARTDELIM; 310 frame->mii_opcode = RTK_MII_READOP; 311 frame->mii_turnaround = 0; 312 frame->mii_data = 0; 313 314 CSR_WRITE_2(sc, RTK_MII, 0); 315 316 /* 317 * Turn on data xmit. 318 */ 319 MII_SET(RTK_MII_DIR); 320 321 rtk_mii_sync(sc); 322 323 /* 324 * Send command/address info. 325 */ 326 rtk_mii_send(sc, frame->mii_stdelim, 2); 327 rtk_mii_send(sc, frame->mii_opcode, 2); 328 rtk_mii_send(sc, frame->mii_phyaddr, 5); 329 rtk_mii_send(sc, frame->mii_regaddr, 5); 330 331 /* Idle bit */ 332 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 333 DELAY(1); 334 MII_SET(RTK_MII_CLK); 335 DELAY(1); 336 337 /* Turn off xmit. */ 338 MII_CLR(RTK_MII_DIR); 339 340 /* Check for ack */ 341 MII_CLR(RTK_MII_CLK); 342 DELAY(1); 343 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 344 MII_SET(RTK_MII_CLK); 345 DELAY(1); 346 347 /* 348 * Now try reading data bits. If the ack failed, we still 349 * need to clock through 16 cycles to keep the PHY(s) in sync. 350 */ 351 if (ack) { 352 for (i = 0; i < 16; i++) { 353 MII_CLR(RTK_MII_CLK); 354 DELAY(1); 355 MII_SET(RTK_MII_CLK); 356 DELAY(1); 357 } 358 goto fail; 359 } 360 361 for (i = 16; i > 0; i--) { 362 MII_CLR(RTK_MII_CLK); 363 DELAY(1); 364 if (!ack) { 365 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 366 frame->mii_data |= 1 << (i - 1); 367 DELAY(1); 368 } 369 MII_SET(RTK_MII_CLK); 370 DELAY(1); 371 } 372 373 fail: 374 MII_CLR(RTK_MII_CLK); 375 DELAY(1); 376 MII_SET(RTK_MII_CLK); 377 DELAY(1); 378 379 splx(s); 380 381 if (ack) 382 return 1; 383 return 0; 384 } 385 386 /* 387 * Write to a PHY register through the MII. 388 */ 389 STATIC int 390 rtk_mii_writereg(struct rtk_softc *sc, struct rtk_mii_frame *frame) 391 { 392 int s; 393 394 s = splnet(); 395 /* 396 * Set up frame for TX. 397 */ 398 frame->mii_stdelim = RTK_MII_STARTDELIM; 399 frame->mii_opcode = RTK_MII_WRITEOP; 400 frame->mii_turnaround = RTK_MII_TURNAROUND; 401 402 /* 403 * Turn on data output. 404 */ 405 MII_SET(RTK_MII_DIR); 406 407 rtk_mii_sync(sc); 408 409 rtk_mii_send(sc, frame->mii_stdelim, 2); 410 rtk_mii_send(sc, frame->mii_opcode, 2); 411 rtk_mii_send(sc, frame->mii_phyaddr, 5); 412 rtk_mii_send(sc, frame->mii_regaddr, 5); 413 rtk_mii_send(sc, frame->mii_turnaround, 2); 414 rtk_mii_send(sc, frame->mii_data, 16); 415 416 /* Idle bit. */ 417 MII_SET(RTK_MII_CLK); 418 DELAY(1); 419 MII_CLR(RTK_MII_CLK); 420 DELAY(1); 421 422 /* 423 * Turn off xmit. 424 */ 425 MII_CLR(RTK_MII_DIR); 426 427 splx(s); 428 429 return 0; 430 } 431 432 STATIC int 433 rtk_phy_readreg(struct device *self, int phy, int reg) 434 { 435 struct rtk_softc *sc = (void *)self; 436 struct rtk_mii_frame frame; 437 int rval; 438 int rtk8139_reg; 439 440 if ((sc->sc_quirk & RTKQ_8129) == 0) { 441 if (phy != 7) 442 return 0; 443 444 switch (reg) { 445 case MII_BMCR: 446 rtk8139_reg = RTK_BMCR; 447 break; 448 case MII_BMSR: 449 rtk8139_reg = RTK_BMSR; 450 break; 451 case MII_ANAR: 452 rtk8139_reg = RTK_ANAR; 453 break; 454 case MII_ANER: 455 rtk8139_reg = RTK_ANER; 456 break; 457 case MII_ANLPAR: 458 rtk8139_reg = RTK_LPAR; 459 break; 460 default: 461 #if 0 462 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 463 #endif 464 return 0; 465 } 466 rval = CSR_READ_2(sc, rtk8139_reg); 467 return rval; 468 } 469 470 memset((char *)&frame, 0, sizeof(frame)); 471 472 frame.mii_phyaddr = phy; 473 frame.mii_regaddr = reg; 474 rtk_mii_readreg(sc, &frame); 475 476 return frame.mii_data; 477 } 478 479 STATIC void rtk_phy_writereg(struct device *self, int phy, int reg, int data) 480 { 481 struct rtk_softc *sc = (void *)self; 482 struct rtk_mii_frame frame; 483 int rtk8139_reg; 484 485 if ((sc->sc_quirk & RTKQ_8129) == 0) { 486 if (phy != 7) 487 return; 488 489 switch (reg) { 490 case MII_BMCR: 491 rtk8139_reg = RTK_BMCR; 492 break; 493 case MII_BMSR: 494 rtk8139_reg = RTK_BMSR; 495 break; 496 case MII_ANAR: 497 rtk8139_reg = RTK_ANAR; 498 break; 499 case MII_ANER: 500 rtk8139_reg = RTK_ANER; 501 break; 502 case MII_ANLPAR: 503 rtk8139_reg = RTK_LPAR; 504 break; 505 default: 506 #if 0 507 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 508 #endif 509 return; 510 } 511 CSR_WRITE_2(sc, rtk8139_reg, data); 512 return; 513 } 514 515 memset((char *)&frame, 0, sizeof(frame)); 516 517 frame.mii_phyaddr = phy; 518 frame.mii_regaddr = reg; 519 frame.mii_data = data; 520 521 rtk_mii_writereg(sc, &frame); 522 } 523 524 STATIC void 525 rtk_phy_statchg(struct device *v) 526 { 527 528 /* Nothing to do. */ 529 } 530 531 #define rtk_calchash(addr) \ 532 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 533 534 /* 535 * Program the 64-bit multicast hash filter. 536 */ 537 void 538 rtk_setmulti(struct rtk_softc *sc) 539 { 540 struct ifnet *ifp; 541 uint32_t hashes[2] = { 0, 0 }; 542 uint32_t rxfilt; 543 struct ether_multi *enm; 544 struct ether_multistep step; 545 int h, mcnt; 546 547 ifp = &sc->ethercom.ec_if; 548 549 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 550 551 if (ifp->if_flags & IFF_PROMISC) { 552 allmulti: 553 ifp->if_flags |= IFF_ALLMULTI; 554 rxfilt |= RTK_RXCFG_RX_MULTI; 555 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 556 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 557 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 558 return; 559 } 560 561 /* first, zot all the existing hash bits */ 562 CSR_WRITE_4(sc, RTK_MAR0, 0); 563 CSR_WRITE_4(sc, RTK_MAR4, 0); 564 565 /* now program new ones */ 566 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 567 mcnt = 0; 568 while (enm != NULL) { 569 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 570 ETHER_ADDR_LEN) != 0) 571 goto allmulti; 572 573 h = rtk_calchash(enm->enm_addrlo); 574 if (h < 32) 575 hashes[0] |= (1 << h); 576 else 577 hashes[1] |= (1 << (h - 32)); 578 mcnt++; 579 ETHER_NEXT_MULTI(step, enm); 580 } 581 582 ifp->if_flags &= ~IFF_ALLMULTI; 583 584 if (mcnt) 585 rxfilt |= RTK_RXCFG_RX_MULTI; 586 else 587 rxfilt &= ~RTK_RXCFG_RX_MULTI; 588 589 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 590 591 /* 592 * For some unfathomable reason, RealTek decided to reverse 593 * the order of the multicast hash registers in the PCI Express 594 * parts. This means we have to write the hash pattern in reverse 595 * order for those devices. 596 */ 597 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 598 CSR_WRITE_4(sc, RTK_MAR0, bswap32(hashes[1])); 599 CSR_WRITE_4(sc, RTK_MAR4, bswap32(hashes[0])); 600 } else { 601 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 602 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 603 } 604 } 605 606 void 607 rtk_reset(struct rtk_softc *sc) 608 { 609 int i; 610 611 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 612 613 for (i = 0; i < RTK_TIMEOUT; i++) { 614 DELAY(10); 615 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 616 break; 617 } 618 if (i == RTK_TIMEOUT) 619 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 620 } 621 622 /* 623 * Attach the interface. Allocate softc structures, do ifmedia 624 * setup and ethernet/BPF attach. 625 */ 626 void 627 rtk_attach(struct rtk_softc *sc) 628 { 629 struct ifnet *ifp; 630 struct rtk_tx_desc *txd; 631 uint16_t val; 632 uint8_t eaddr[ETHER_ADDR_LEN]; 633 int error; 634 int i, addr_len; 635 636 callout_init(&sc->rtk_tick_ch); 637 638 /* 639 * Check EEPROM type 9346 or 9356. 640 */ 641 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 642 addr_len = RTK_EEADDR_LEN1; 643 else 644 addr_len = RTK_EEADDR_LEN0; 645 646 /* 647 * Get station address. 648 */ 649 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 650 eaddr[0] = val & 0xff; 651 eaddr[1] = val >> 8; 652 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 653 eaddr[2] = val & 0xff; 654 eaddr[3] = val >> 8; 655 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 656 eaddr[4] = val & 0xff; 657 eaddr[5] = val >> 8; 658 659 if ((error = bus_dmamem_alloc(sc->sc_dmat, 660 RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 661 BUS_DMA_NOWAIT)) != 0) { 662 printf("%s: can't allocate recv buffer, error = %d\n", 663 sc->sc_dev.dv_xname, error); 664 goto fail_0; 665 } 666 667 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 668 RTK_RXBUFLEN + 16, (caddr_t *)&sc->rtk_rx_buf, 669 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 670 printf("%s: can't map recv buffer, error = %d\n", 671 sc->sc_dev.dv_xname, error); 672 goto fail_1; 673 } 674 675 if ((error = bus_dmamap_create(sc->sc_dmat, 676 RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT, 677 &sc->recv_dmamap)) != 0) { 678 printf("%s: can't create recv buffer DMA map, error = %d\n", 679 sc->sc_dev.dv_xname, error); 680 goto fail_2; 681 } 682 683 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 684 sc->rtk_rx_buf, RTK_RXBUFLEN + 16, 685 NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 686 printf("%s: can't load recv buffer DMA map, error = %d\n", 687 sc->sc_dev.dv_xname, error); 688 goto fail_3; 689 } 690 691 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 692 txd = &sc->rtk_tx_descs[i]; 693 if ((error = bus_dmamap_create(sc->sc_dmat, 694 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 695 &txd->txd_dmamap)) != 0) { 696 printf("%s: can't create snd buffer DMA map," 697 " error = %d\n", sc->sc_dev.dv_xname, error); 698 goto fail_4; 699 } 700 txd->txd_txaddr = RTK_TXADDR0 + (i * 4); 701 txd->txd_txstat = RTK_TXSTAT0 + (i * 4); 702 } 703 SIMPLEQ_INIT(&sc->rtk_tx_free); 704 SIMPLEQ_INIT(&sc->rtk_tx_dirty); 705 706 /* 707 * From this point forward, the attachment cannot fail. A failure 708 * before this releases all resources thar may have been 709 * allocated. 710 */ 711 sc->sc_flags |= RTK_ATTACHED; 712 713 /* Reset the adapter. */ 714 rtk_reset(sc); 715 716 printf("%s: Ethernet address %s\n", 717 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 718 719 ifp = &sc->ethercom.ec_if; 720 ifp->if_softc = sc; 721 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 722 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 723 ifp->if_ioctl = rtk_ioctl; 724 ifp->if_start = rtk_start; 725 ifp->if_watchdog = rtk_watchdog; 726 ifp->if_init = rtk_init; 727 ifp->if_stop = rtk_stop; 728 IFQ_SET_READY(&ifp->if_snd); 729 730 /* 731 * Do ifmedia setup. 732 */ 733 sc->mii.mii_ifp = ifp; 734 sc->mii.mii_readreg = rtk_phy_readreg; 735 sc->mii.mii_writereg = rtk_phy_writereg; 736 sc->mii.mii_statchg = rtk_phy_statchg; 737 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, rtk_ifmedia_upd, 738 rtk_ifmedia_sts); 739 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 740 MII_PHY_ANY, MII_OFFSET_ANY, 0); 741 742 /* Choose a default media. */ 743 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 744 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 745 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 746 } else { 747 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 748 } 749 750 /* 751 * Call MI attach routines. 752 */ 753 if_attach(ifp); 754 ether_ifattach(ifp, eaddr); 755 756 /* 757 * Make sure the interface is shutdown during reboot. 758 */ 759 sc->sc_sdhook = shutdownhook_establish(rtk_shutdown, sc); 760 if (sc->sc_sdhook == NULL) 761 printf("%s: WARNING: unable to establish shutdown hook\n", 762 sc->sc_dev.dv_xname); 763 /* 764 * Add a suspend hook to make sure we come back up after a 765 * resume. 766 */ 767 sc->sc_powerhook = powerhook_establish(rtk_power, sc); 768 if (sc->sc_powerhook == NULL) 769 printf("%s: WARNING: unable to establish power hook\n", 770 sc->sc_dev.dv_xname); 771 772 773 #if NRND > 0 774 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 775 RND_TYPE_NET, 0); 776 #endif 777 778 return; 779 fail_4: 780 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 781 txd = &sc->rtk_tx_descs[i]; 782 if (txd->txd_dmamap != NULL) 783 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 784 } 785 fail_3: 786 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 787 fail_2: 788 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 789 RTK_RXBUFLEN + 16); 790 fail_1: 791 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 792 fail_0: 793 return; 794 } 795 796 /* 797 * Initialize the transmit descriptors. 798 */ 799 STATIC int 800 rtk_list_tx_init(struct rtk_softc *sc) 801 { 802 struct rtk_tx_desc *txd; 803 int i; 804 805 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) 806 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 807 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) 808 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 809 810 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 811 txd = &sc->rtk_tx_descs[i]; 812 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 813 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 814 } 815 816 return 0; 817 } 818 819 /* 820 * rtk_activate: 821 * Handle device activation/deactivation requests. 822 */ 823 int 824 rtk_activate(struct device *self, enum devact act) 825 { 826 struct rtk_softc *sc = (void *)self; 827 int s, error; 828 829 error = 0; 830 s = splnet(); 831 switch (act) { 832 case DVACT_ACTIVATE: 833 error = EOPNOTSUPP; 834 break; 835 case DVACT_DEACTIVATE: 836 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 837 if_deactivate(&sc->ethercom.ec_if); 838 break; 839 } 840 splx(s); 841 842 return error; 843 } 844 845 /* 846 * rtk_detach: 847 * Detach a rtk interface. 848 */ 849 int 850 rtk_detach(struct rtk_softc *sc) 851 { 852 struct ifnet *ifp = &sc->ethercom.ec_if; 853 struct rtk_tx_desc *txd; 854 int i; 855 856 /* 857 * Succeed now if there isn't any work to do. 858 */ 859 if ((sc->sc_flags & RTK_ATTACHED) == 0) 860 return 0; 861 862 /* Unhook our tick handler. */ 863 callout_stop(&sc->rtk_tick_ch); 864 865 /* Detach all PHYs. */ 866 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 867 868 /* Delete all remaining media. */ 869 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 870 871 #if NRND > 0 872 rnd_detach_source(&sc->rnd_source); 873 #endif 874 875 ether_ifdetach(ifp); 876 if_detach(ifp); 877 878 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 879 txd = &sc->rtk_tx_descs[i]; 880 if (txd->txd_dmamap != NULL) 881 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 882 } 883 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 884 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 885 RTK_RXBUFLEN + 16); 886 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 887 888 shutdownhook_disestablish(sc->sc_sdhook); 889 powerhook_disestablish(sc->sc_powerhook); 890 891 return 0; 892 } 893 894 /* 895 * rtk_enable: 896 * Enable the RTL81X9 chip. 897 */ 898 int 899 rtk_enable(struct rtk_softc *sc) 900 { 901 902 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 903 if ((*sc->sc_enable)(sc) != 0) { 904 printf("%s: device enable failed\n", 905 sc->sc_dev.dv_xname); 906 return EIO; 907 } 908 sc->sc_flags |= RTK_ENABLED; 909 } 910 return 0; 911 } 912 913 /* 914 * rtk_disable: 915 * Disable the RTL81X9 chip. 916 */ 917 void 918 rtk_disable(struct rtk_softc *sc) 919 { 920 921 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 922 (*sc->sc_disable)(sc); 923 sc->sc_flags &= ~RTK_ENABLED; 924 } 925 } 926 927 /* 928 * rtk_power: 929 * Power management (suspend/resume) hook. 930 */ 931 void 932 rtk_power(int why, void *arg) 933 { 934 struct rtk_softc *sc = (void *)arg; 935 struct ifnet *ifp = &sc->ethercom.ec_if; 936 int s; 937 938 s = splnet(); 939 switch (why) { 940 case PWR_SUSPEND: 941 case PWR_STANDBY: 942 rtk_stop(ifp, 0); 943 if (sc->sc_power != NULL) 944 (*sc->sc_power)(sc, why); 945 break; 946 case PWR_RESUME: 947 if (ifp->if_flags & IFF_UP) { 948 if (sc->sc_power != NULL) 949 (*sc->sc_power)(sc, why); 950 rtk_init(ifp); 951 } 952 break; 953 case PWR_SOFTSUSPEND: 954 case PWR_SOFTSTANDBY: 955 case PWR_SOFTRESUME: 956 break; 957 } 958 splx(s); 959 } 960 961 /* 962 * A frame has been uploaded: pass the resulting mbuf chain up to 963 * the higher level protocols. 964 * 965 * You know there's something wrong with a PCI bus-master chip design. 966 * 967 * The receive operation is badly documented in the datasheet, so I'll 968 * attempt to document it here. The driver provides a buffer area and 969 * places its base address in the RX buffer start address register. 970 * The chip then begins copying frames into the RX buffer. Each frame 971 * is preceded by a 32-bit RX status word which specifies the length 972 * of the frame and certain other status bits. Each frame (starting with 973 * the status word) is also 32-bit aligned. The frame length is in the 974 * first 16 bits of the status word; the lower 15 bits correspond with 975 * the 'rx status register' mentioned in the datasheet. 976 * 977 * Note: to make the Alpha happy, the frame payload needs to be aligned 978 * on a 32-bit boundary. To achieve this, we copy the data to mbuf 979 * shifted forward 2 bytes. 980 */ 981 STATIC void 982 rtk_rxeof(struct rtk_softc *sc) 983 { 984 struct mbuf *m; 985 struct ifnet *ifp; 986 caddr_t rxbufpos, dst; 987 u_int total_len, wrap; 988 uint32_t rxstat; 989 uint16_t cur_rx, new_rx; 990 uint16_t limit; 991 uint16_t rx_bytes, max_bytes; 992 993 ifp = &sc->ethercom.ec_if; 994 995 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 996 997 /* Do not try to read past this point. */ 998 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 999 1000 if (limit < cur_rx) 1001 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 1002 else 1003 max_bytes = limit - cur_rx; 1004 rx_bytes = 0; 1005 1006 while ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 1007 rxbufpos = sc->rtk_rx_buf + cur_rx; 1008 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1009 RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD); 1010 rxstat = le32toh(*(uint32_t *)rxbufpos); 1011 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1012 RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD); 1013 1014 /* 1015 * Here's a totally undocumented fact for you. When the 1016 * RealTek chip is in the process of copying a packet into 1017 * RAM for you, the length will be 0xfff0. If you spot a 1018 * packet header with this value, you need to stop. The 1019 * datasheet makes absolutely no mention of this and 1020 * RealTek should be shot for this. 1021 */ 1022 total_len = rxstat >> 16; 1023 if (total_len == RTK_RXSTAT_UNFINISHED) 1024 break; 1025 1026 if ((rxstat & RTK_RXSTAT_RXOK) == 0 || 1027 total_len < ETHER_MIN_LEN || 1028 total_len > (MCLBYTES - RTK_ETHER_ALIGN)) { 1029 ifp->if_ierrors++; 1030 1031 /* 1032 * submitted by:[netbsd-pcmcia:00484] 1033 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp> 1034 * obtain from: 1035 * FreeBSD if_rl.c rev 1.24->1.25 1036 * 1037 */ 1038 #if 0 1039 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1040 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1041 RTK_RXSTAT_ALIGNERR)) { 1042 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 1043 CSR_WRITE_2(sc, RTK_COMMAND, 1044 RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1045 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1046 CSR_WRITE_4(sc, RTK_RXADDR, 1047 sc->recv_dmamap->dm_segs[0].ds_addr); 1048 cur_rx = 0; 1049 } 1050 break; 1051 #else 1052 rtk_init(ifp); 1053 return; 1054 #endif 1055 } 1056 1057 /* No errors; receive the packet. */ 1058 rx_bytes += total_len + RTK_RXSTAT_LEN; 1059 1060 /* 1061 * Avoid trying to read more bytes than we know 1062 * the chip has prepared for us. 1063 */ 1064 if (rx_bytes > max_bytes) 1065 break; 1066 1067 /* 1068 * Skip the status word, wrapping around to the beginning 1069 * of the Rx area, if necessary. 1070 */ 1071 cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN; 1072 rxbufpos = sc->rtk_rx_buf + cur_rx; 1073 1074 /* 1075 * Compute the number of bytes at which the packet 1076 * will wrap to the beginning of the ring buffer. 1077 */ 1078 wrap = RTK_RXBUFLEN - cur_rx; 1079 1080 /* 1081 * Compute where the next pending packet is. 1082 */ 1083 if (total_len > wrap) 1084 new_rx = total_len - wrap; 1085 else 1086 new_rx = cur_rx + total_len; 1087 /* Round up to 32-bit boundary. */ 1088 new_rx = ((new_rx + 3) & ~3) % RTK_RXBUFLEN; 1089 1090 /* 1091 * The RealTek chip includes the CRC with every 1092 * incoming packet; trim it off here. 1093 */ 1094 total_len -= ETHER_CRC_LEN; 1095 1096 /* 1097 * Now allocate an mbuf (and possibly a cluster) to hold 1098 * the packet. Note we offset the packet 2 bytes so that 1099 * data after the Ethernet header will be 4-byte aligned. 1100 */ 1101 MGETHDR(m, M_DONTWAIT, MT_DATA); 1102 if (m == NULL) { 1103 printf("%s: unable to allocate Rx mbuf\n", 1104 sc->sc_dev.dv_xname); 1105 ifp->if_ierrors++; 1106 goto next_packet; 1107 } 1108 if (total_len > (MHLEN - RTK_ETHER_ALIGN)) { 1109 MCLGET(m, M_DONTWAIT); 1110 if ((m->m_flags & M_EXT) == 0) { 1111 printf("%s: unable to allocate Rx cluster\n", 1112 sc->sc_dev.dv_xname); 1113 ifp->if_ierrors++; 1114 m_freem(m); 1115 m = NULL; 1116 goto next_packet; 1117 } 1118 } 1119 m->m_data += RTK_ETHER_ALIGN; /* for alignment */ 1120 m->m_pkthdr.rcvif = ifp; 1121 m->m_pkthdr.len = m->m_len = total_len; 1122 dst = mtod(m, caddr_t); 1123 1124 /* 1125 * If the packet wraps, copy up to the wrapping point. 1126 */ 1127 if (total_len > wrap) { 1128 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1129 cur_rx, wrap, BUS_DMASYNC_POSTREAD); 1130 memcpy(dst, rxbufpos, wrap); 1131 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1132 cur_rx, wrap, BUS_DMASYNC_PREREAD); 1133 cur_rx = 0; 1134 rxbufpos = sc->rtk_rx_buf; 1135 total_len -= wrap; 1136 dst += wrap; 1137 } 1138 1139 /* 1140 * ...and now the rest. 1141 */ 1142 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1143 cur_rx, total_len, BUS_DMASYNC_POSTREAD); 1144 memcpy(dst, rxbufpos, total_len); 1145 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1146 cur_rx, total_len, BUS_DMASYNC_PREREAD); 1147 1148 next_packet: 1149 CSR_WRITE_2(sc, RTK_CURRXADDR, (new_rx - 16) % RTK_RXBUFLEN); 1150 cur_rx = new_rx; 1151 1152 if (m == NULL) 1153 continue; 1154 1155 ifp->if_ipackets++; 1156 1157 #if NBPFILTER > 0 1158 if (ifp->if_bpf) 1159 bpf_mtap(ifp->if_bpf, m); 1160 #endif 1161 /* pass it on. */ 1162 (*ifp->if_input)(ifp, m); 1163 } 1164 } 1165 1166 /* 1167 * A frame was downloaded to the chip. It's safe for us to clean up 1168 * the list buffers. 1169 */ 1170 STATIC void 1171 rtk_txeof(struct rtk_softc *sc) 1172 { 1173 struct ifnet *ifp; 1174 struct rtk_tx_desc *txd; 1175 uint32_t txstat; 1176 1177 ifp = &sc->ethercom.ec_if; 1178 1179 /* 1180 * Go through our tx list and free mbufs for those 1181 * frames that have been uploaded. 1182 */ 1183 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1184 txstat = CSR_READ_4(sc, txd->txd_txstat); 1185 if ((txstat & (RTK_TXSTAT_TX_OK| 1186 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0) 1187 break; 1188 1189 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1190 1191 bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0, 1192 txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1193 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1194 m_freem(txd->txd_mbuf); 1195 txd->txd_mbuf = NULL; 1196 1197 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1198 1199 if (txstat & RTK_TXSTAT_TX_OK) 1200 ifp->if_opackets++; 1201 else { 1202 ifp->if_oerrors++; 1203 1204 /* 1205 * Increase Early TX threshold if underrun occurred. 1206 * Increase step 64 bytes. 1207 */ 1208 if (txstat & RTK_TXSTAT_TX_UNDERRUN) { 1209 #ifdef DEBUG 1210 printf("%s: transmit underrun;", 1211 sc->sc_dev.dv_xname); 1212 #endif 1213 if (sc->sc_txthresh < RTK_TXTH_MAX) { 1214 sc->sc_txthresh += 2; 1215 #ifdef DEBUG 1216 printf(" new threshold: %d bytes", 1217 sc->sc_txthresh * 32); 1218 #endif 1219 } 1220 printf("\n"); 1221 } 1222 if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN)) 1223 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1224 } 1225 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 1226 ifp->if_flags &= ~IFF_OACTIVE; 1227 } 1228 1229 /* Clear the timeout timer if there is no pending packet. */ 1230 if (SIMPLEQ_EMPTY(&sc->rtk_tx_dirty)) 1231 ifp->if_timer = 0; 1232 1233 } 1234 1235 int 1236 rtk_intr(void *arg) 1237 { 1238 struct rtk_softc *sc; 1239 struct ifnet *ifp; 1240 uint16_t status; 1241 int handled; 1242 1243 sc = arg; 1244 ifp = &sc->ethercom.ec_if; 1245 1246 /* Disable interrupts. */ 1247 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1248 1249 handled = 0; 1250 for (;;) { 1251 1252 status = CSR_READ_2(sc, RTK_ISR); 1253 if (status) 1254 CSR_WRITE_2(sc, RTK_ISR, status); 1255 1256 if ((status & RTK_INTRS) == 0) 1257 break; 1258 1259 handled = 1; 1260 1261 if (status & RTK_ISR_RX_OK) 1262 rtk_rxeof(sc); 1263 1264 if (status & RTK_ISR_RX_ERR) 1265 rtk_rxeof(sc); 1266 1267 if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR)) 1268 rtk_txeof(sc); 1269 1270 if (status & RTK_ISR_SYSTEM_ERR) { 1271 rtk_reset(sc); 1272 rtk_init(ifp); 1273 } 1274 } 1275 1276 /* Re-enable interrupts. */ 1277 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1278 1279 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1280 rtk_start(ifp); 1281 1282 #if NRND > 0 1283 if (RND_ENABLED(&sc->rnd_source)) 1284 rnd_add_uint32(&sc->rnd_source, status); 1285 #endif 1286 1287 return handled; 1288 } 1289 1290 /* 1291 * Main transmit routine. 1292 */ 1293 1294 STATIC void 1295 rtk_start(struct ifnet *ifp) 1296 { 1297 struct rtk_softc *sc; 1298 struct rtk_tx_desc *txd; 1299 struct mbuf *m_head, *m_new; 1300 int error, len; 1301 1302 sc = ifp->if_softc; 1303 1304 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) { 1305 IFQ_POLL(&ifp->if_snd, m_head); 1306 if (m_head == NULL) 1307 break; 1308 m_new = NULL; 1309 1310 /* 1311 * Load the DMA map. If this fails, the packet didn't 1312 * fit in one DMA segment, and we need to copy. Note, 1313 * the packet must also be aligned. 1314 * if the packet is too small, copy it too, so we're sure 1315 * so have enouth room for the pad buffer. 1316 */ 1317 if ((mtod(m_head, uintptr_t) & 3) != 0 || 1318 m_head->m_pkthdr.len < ETHER_PAD_LEN || 1319 bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap, 1320 m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1321 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1322 if (m_new == NULL) { 1323 printf("%s: unable to allocate Tx mbuf\n", 1324 sc->sc_dev.dv_xname); 1325 break; 1326 } 1327 if (m_head->m_pkthdr.len > MHLEN) { 1328 MCLGET(m_new, M_DONTWAIT); 1329 if ((m_new->m_flags & M_EXT) == 0) { 1330 printf("%s: unable to allocate Tx " 1331 "cluster\n", sc->sc_dev.dv_xname); 1332 m_freem(m_new); 1333 break; 1334 } 1335 } 1336 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1337 mtod(m_new, caddr_t)); 1338 m_new->m_pkthdr.len = m_new->m_len = 1339 m_head->m_pkthdr.len; 1340 if (m_head->m_pkthdr.len < ETHER_PAD_LEN) { 1341 memset( 1342 mtod(m_new, caddr_t) + m_head->m_pkthdr.len, 1343 0, ETHER_PAD_LEN - m_head->m_pkthdr.len); 1344 m_new->m_pkthdr.len = m_new->m_len = 1345 ETHER_PAD_LEN; 1346 } 1347 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1348 txd->txd_dmamap, m_new, 1349 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1350 if (error) { 1351 printf("%s: unable to load Tx buffer, " 1352 "error = %d\n", sc->sc_dev.dv_xname, error); 1353 break; 1354 } 1355 } 1356 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1357 #if NBPFILTER > 0 1358 /* 1359 * If there's a BPF listener, bounce a copy of this frame 1360 * to him. 1361 */ 1362 if (ifp->if_bpf) 1363 bpf_mtap(ifp->if_bpf, m_head); 1364 #endif 1365 if (m_new != NULL) { 1366 m_freem(m_head); 1367 m_head = m_new; 1368 } 1369 txd->txd_mbuf = m_head; 1370 1371 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 1372 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q); 1373 1374 /* 1375 * Transmit the frame. 1376 */ 1377 bus_dmamap_sync(sc->sc_dmat, 1378 txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize, 1379 BUS_DMASYNC_PREWRITE); 1380 1381 len = txd->txd_dmamap->dm_segs[0].ds_len; 1382 1383 CSR_WRITE_4(sc, txd->txd_txaddr, 1384 txd->txd_dmamap->dm_segs[0].ds_addr); 1385 CSR_WRITE_4(sc, txd->txd_txstat, 1386 RTK_TXSTAT_THRESH(sc->sc_txthresh) | len); 1387 1388 /* 1389 * Set a timeout in case the chip goes out to lunch. 1390 */ 1391 ifp->if_timer = 5; 1392 } 1393 1394 /* 1395 * We broke out of the loop because all our TX slots are 1396 * full. Mark the NIC as busy until it drains some of the 1397 * packets from the queue. 1398 */ 1399 if (SIMPLEQ_EMPTY(&sc->rtk_tx_free)) 1400 ifp->if_flags |= IFF_OACTIVE; 1401 } 1402 1403 STATIC int 1404 rtk_init(struct ifnet *ifp) 1405 { 1406 struct rtk_softc *sc = ifp->if_softc; 1407 int error, i; 1408 uint32_t rxcfg; 1409 1410 if ((error = rtk_enable(sc)) != 0) 1411 goto out; 1412 1413 /* 1414 * Cancel pending I/O. 1415 */ 1416 rtk_stop(ifp, 0); 1417 1418 /* Init our MAC address */ 1419 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1420 CSR_WRITE_1(sc, RTK_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1421 } 1422 1423 /* Init the RX buffer pointer register. */ 1424 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1425 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1426 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1427 1428 /* Init TX descriptors. */ 1429 rtk_list_tx_init(sc); 1430 1431 /* Init Early TX threshold. */ 1432 sc->sc_txthresh = RTK_TXTH_256; 1433 /* 1434 * Enable transmit and receive. 1435 */ 1436 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1437 1438 /* 1439 * Set the initial TX and RX configuration. 1440 */ 1441 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1442 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1443 1444 /* Set the individual bit to receive frames for this host only. */ 1445 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1446 rxcfg |= RTK_RXCFG_RX_INDIV; 1447 1448 /* If we want promiscuous mode, set the allframes bit. */ 1449 if (ifp->if_flags & IFF_PROMISC) { 1450 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1451 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1452 } else { 1453 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1454 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1455 } 1456 1457 /* 1458 * Set capture broadcast bit to capture broadcast frames. 1459 */ 1460 if (ifp->if_flags & IFF_BROADCAST) { 1461 rxcfg |= RTK_RXCFG_RX_BROAD; 1462 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1463 } else { 1464 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1465 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1466 } 1467 1468 /* 1469 * Program the multicast filter, if necessary. 1470 */ 1471 rtk_setmulti(sc); 1472 1473 /* 1474 * Enable interrupts. 1475 */ 1476 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1477 1478 /* Start RX/TX process. */ 1479 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1480 1481 /* Enable receiver and transmitter. */ 1482 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1483 1484 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1485 1486 /* 1487 * Set current media. 1488 */ 1489 mii_mediachg(&sc->mii); 1490 1491 ifp->if_flags |= IFF_RUNNING; 1492 ifp->if_flags &= ~IFF_OACTIVE; 1493 1494 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1495 1496 out: 1497 if (error) { 1498 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1499 ifp->if_timer = 0; 1500 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1501 } 1502 return error; 1503 } 1504 1505 /* 1506 * Set media options. 1507 */ 1508 STATIC int 1509 rtk_ifmedia_upd(struct ifnet *ifp) 1510 { 1511 struct rtk_softc *sc; 1512 1513 sc = ifp->if_softc; 1514 1515 return mii_mediachg(&sc->mii); 1516 } 1517 1518 /* 1519 * Report current media status. 1520 */ 1521 STATIC void 1522 rtk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1523 { 1524 struct rtk_softc *sc; 1525 1526 sc = ifp->if_softc; 1527 1528 mii_pollstat(&sc->mii); 1529 ifmr->ifm_status = sc->mii.mii_media_status; 1530 ifmr->ifm_active = sc->mii.mii_media_active; 1531 } 1532 1533 STATIC int 1534 rtk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1535 { 1536 struct rtk_softc *sc = ifp->if_softc; 1537 struct ifreq *ifr = (struct ifreq *)data; 1538 int s, error; 1539 1540 s = splnet(); 1541 1542 switch (command) { 1543 case SIOCGIFMEDIA: 1544 case SIOCSIFMEDIA: 1545 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1546 break; 1547 1548 default: 1549 error = ether_ioctl(ifp, command, data); 1550 if (error == ENETRESET) { 1551 if (ifp->if_flags & IFF_RUNNING) { 1552 /* 1553 * Multicast list has changed. Set the 1554 * hardware filter accordingly. 1555 */ 1556 rtk_setmulti(sc); 1557 } 1558 error = 0; 1559 } 1560 break; 1561 } 1562 1563 splx(s); 1564 1565 return error; 1566 } 1567 1568 STATIC void 1569 rtk_watchdog(struct ifnet *ifp) 1570 { 1571 struct rtk_softc *sc; 1572 1573 sc = ifp->if_softc; 1574 1575 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1576 ifp->if_oerrors++; 1577 rtk_txeof(sc); 1578 rtk_rxeof(sc); 1579 rtk_init(ifp); 1580 } 1581 1582 /* 1583 * Stop the adapter and free any mbufs allocated to the 1584 * RX and TX lists. 1585 */ 1586 STATIC void 1587 rtk_stop(struct ifnet *ifp, int disable) 1588 { 1589 struct rtk_softc *sc = ifp->if_softc; 1590 struct rtk_tx_desc *txd; 1591 1592 callout_stop(&sc->rtk_tick_ch); 1593 1594 mii_down(&sc->mii); 1595 1596 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1597 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1598 1599 /* 1600 * Free the TX list buffers. 1601 */ 1602 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1603 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1604 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1605 m_freem(txd->txd_mbuf); 1606 txd->txd_mbuf = NULL; 1607 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 1608 } 1609 1610 if (disable) 1611 rtk_disable(sc); 1612 1613 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1614 ifp->if_timer = 0; 1615 } 1616 1617 /* 1618 * Stop all chip I/O so that the kernel's probe routines don't 1619 * get confused by errant DMAs when rebooting. 1620 */ 1621 STATIC void 1622 rtk_shutdown(void *arg) 1623 { 1624 struct rtk_softc *sc = (struct rtk_softc *)arg; 1625 1626 rtk_stop(&sc->ethercom.ec_if, 0); 1627 } 1628 1629 STATIC void 1630 rtk_tick(void *arg) 1631 { 1632 struct rtk_softc *sc = arg; 1633 int s; 1634 1635 s = splnet(); 1636 mii_tick(&sc->mii); 1637 splx(s); 1638 1639 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1640 }
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