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sys/dev/ic/rtl81x9.c
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1 /* $NetBSD: rtl81x9.c,v 1.66.2.6 2007/05/24 00:03:15 riz Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400MHz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include <sys/cdefs.h> 89 __KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.66.2.6 2007/05/24 00:03:15 riz Exp $"); 90 91 #include "bpfilter.h" 92 #include "rnd.h" 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/callout.h> 97 #include <sys/device.h> 98 #include <sys/sockio.h> 99 #include <sys/mbuf.h> 100 #include <sys/malloc.h> 101 #include <sys/kernel.h> 102 #include <sys/socket.h> 103 104 #include <uvm/uvm_extern.h> 105 106 #include <net/if.h> 107 #include <net/if_arp.h> 108 #include <net/if_ether.h> 109 #include <net/if_dl.h> 110 #include <net/if_media.h> 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #endif 115 #if NRND > 0 116 #include <sys/rnd.h> 117 #endif 118 119 #include <machine/bus.h> 120 #include <machine/endian.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/ic/rtl81x9reg.h> 126 #include <dev/ic/rtl81x9var.h> 127 128 #if defined(DEBUG) 129 #define STATIC 130 #else 131 #define STATIC static 132 #endif 133 134 STATIC void rtk_reset(struct rtk_softc *); 135 STATIC void rtk_rxeof(struct rtk_softc *); 136 STATIC void rtk_txeof(struct rtk_softc *); 137 STATIC void rtk_start(struct ifnet *); 138 STATIC int rtk_ioctl(struct ifnet *, u_long, caddr_t); 139 STATIC int rtk_init(struct ifnet *); 140 STATIC void rtk_stop(struct ifnet *, int); 141 142 STATIC void rtk_watchdog(struct ifnet *); 143 STATIC void rtk_shutdown(void *); 144 STATIC int rtk_ifmedia_upd(struct ifnet *); 145 STATIC void rtk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 146 147 STATIC void rtk_eeprom_putbyte(struct rtk_softc *, int, int); 148 STATIC void rtk_mii_sync(struct rtk_softc *); 149 STATIC void rtk_mii_send(struct rtk_softc *, uint32_t, int); 150 STATIC int rtk_mii_readreg(struct rtk_softc *, struct rtk_mii_frame *); 151 STATIC int rtk_mii_writereg(struct rtk_softc *, struct rtk_mii_frame *); 152 153 STATIC int rtk_phy_readreg(struct device *, int, int); 154 STATIC void rtk_phy_writereg(struct device *, int, int, int); 155 STATIC void rtk_phy_statchg(struct device *); 156 STATIC void rtk_tick(void *); 157 158 STATIC int rtk_enable(struct rtk_softc *); 159 STATIC void rtk_disable(struct rtk_softc *); 160 STATIC void rtk_power(int, void *); 161 162 STATIC int rtk_list_tx_init(struct rtk_softc *); 163 164 #define EE_SET(x) \ 165 CSR_WRITE_1(sc, RTK_EECMD, \ 166 CSR_READ_1(sc, RTK_EECMD) | (x)) 167 168 #define EE_CLR(x) \ 169 CSR_WRITE_1(sc, RTK_EECMD, \ 170 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 171 172 #define EE_DELAY() DELAY(100) 173 174 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 175 176 /* 177 * Send a read command and address to the EEPROM, check for ACK. 178 */ 179 STATIC void 180 rtk_eeprom_putbyte(struct rtk_softc *sc, int addr, int addr_len) 181 { 182 int d, i; 183 184 d = (RTK_EECMD_READ << addr_len) | addr; 185 186 /* 187 * Feed in each bit and stobe the clock. 188 */ 189 for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) { 190 if (d & (1 << (i - 1))) { 191 EE_SET(RTK_EE_DATAIN); 192 } else { 193 EE_CLR(RTK_EE_DATAIN); 194 } 195 EE_DELAY(); 196 EE_SET(RTK_EE_CLK); 197 EE_DELAY(); 198 EE_CLR(RTK_EE_CLK); 199 EE_DELAY(); 200 } 201 } 202 203 /* 204 * Read a word of data stored in the EEPROM at address 'addr.' 205 */ 206 uint16_t 207 rtk_read_eeprom(struct rtk_softc *sc, int addr, int addr_len) 208 { 209 uint16_t word; 210 int i; 211 212 /* Enter EEPROM access mode. */ 213 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM); 214 EE_DELAY(); 215 EE_SET(RTK_EE_SEL); 216 217 /* 218 * Send address of word we want to read. 219 */ 220 rtk_eeprom_putbyte(sc, addr, addr_len); 221 222 /* 223 * Start reading bits from EEPROM. 224 */ 225 word = 0; 226 for (i = 16; i > 0; i--) { 227 EE_SET(RTK_EE_CLK); 228 EE_DELAY(); 229 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 230 word |= 1 << (i - 1); 231 EE_CLR(RTK_EE_CLK); 232 EE_DELAY(); 233 } 234 235 /* Turn off EEPROM access mode. */ 236 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 237 238 return word; 239 } 240 241 /* 242 * MII access routines are provided for the 8129, which 243 * doesn't have a built-in PHY. For the 8139, we fake things 244 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 245 * direct access PHY registers. 246 */ 247 #define MII_SET(x) \ 248 CSR_WRITE_1(sc, RTK_MII, \ 249 CSR_READ_1(sc, RTK_MII) | (x)) 250 251 #define MII_CLR(x) \ 252 CSR_WRITE_1(sc, RTK_MII, \ 253 CSR_READ_1(sc, RTK_MII) & ~(x)) 254 255 /* 256 * Sync the PHYs by setting data bit and strobing the clock 32 times. 257 */ 258 STATIC void 259 rtk_mii_sync(struct rtk_softc *sc) 260 { 261 int i; 262 263 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 264 265 for (i = 0; i < 32; i++) { 266 MII_SET(RTK_MII_CLK); 267 DELAY(1); 268 MII_CLR(RTK_MII_CLK); 269 DELAY(1); 270 } 271 } 272 273 /* 274 * Clock a series of bits through the MII. 275 */ 276 STATIC void 277 rtk_mii_send(struct rtk_softc *sc, uint32_t bits, int cnt) 278 { 279 int i; 280 281 MII_CLR(RTK_MII_CLK); 282 283 for (i = cnt; i > 0; i--) { 284 if (bits & (1 << (i - 1))) { 285 MII_SET(RTK_MII_DATAOUT); 286 } else { 287 MII_CLR(RTK_MII_DATAOUT); 288 } 289 DELAY(1); 290 MII_CLR(RTK_MII_CLK); 291 DELAY(1); 292 MII_SET(RTK_MII_CLK); 293 } 294 } 295 296 /* 297 * Read an PHY register through the MII. 298 */ 299 STATIC int 300 rtk_mii_readreg(struct rtk_softc *sc, struct rtk_mii_frame *frame) 301 { 302 int i, ack, s; 303 304 s = splnet(); 305 306 /* 307 * Set up frame for RX. 308 */ 309 frame->mii_stdelim = RTK_MII_STARTDELIM; 310 frame->mii_opcode = RTK_MII_READOP; 311 frame->mii_turnaround = 0; 312 frame->mii_data = 0; 313 314 CSR_WRITE_2(sc, RTK_MII, 0); 315 316 /* 317 * Turn on data xmit. 318 */ 319 MII_SET(RTK_MII_DIR); 320 321 rtk_mii_sync(sc); 322 323 /* 324 * Send command/address info. 325 */ 326 rtk_mii_send(sc, frame->mii_stdelim, 2); 327 rtk_mii_send(sc, frame->mii_opcode, 2); 328 rtk_mii_send(sc, frame->mii_phyaddr, 5); 329 rtk_mii_send(sc, frame->mii_regaddr, 5); 330 331 /* Idle bit */ 332 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 333 DELAY(1); 334 MII_SET(RTK_MII_CLK); 335 DELAY(1); 336 337 /* Turn off xmit. */ 338 MII_CLR(RTK_MII_DIR); 339 340 /* Check for ack */ 341 MII_CLR(RTK_MII_CLK); 342 DELAY(1); 343 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 344 MII_SET(RTK_MII_CLK); 345 DELAY(1); 346 347 /* 348 * Now try reading data bits. If the ack failed, we still 349 * need to clock through 16 cycles to keep the PHY(s) in sync. 350 */ 351 if (ack) { 352 for (i = 0; i < 16; i++) { 353 MII_CLR(RTK_MII_CLK); 354 DELAY(1); 355 MII_SET(RTK_MII_CLK); 356 DELAY(1); 357 } 358 goto fail; 359 } 360 361 for (i = 16; i > 0; i--) { 362 MII_CLR(RTK_MII_CLK); 363 DELAY(1); 364 if (!ack) { 365 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 366 frame->mii_data |= 1 << (i - 1); 367 DELAY(1); 368 } 369 MII_SET(RTK_MII_CLK); 370 DELAY(1); 371 } 372 373 fail: 374 MII_CLR(RTK_MII_CLK); 375 DELAY(1); 376 MII_SET(RTK_MII_CLK); 377 DELAY(1); 378 379 splx(s); 380 381 if (ack) 382 return 1; 383 return 0; 384 } 385 386 /* 387 * Write to a PHY register through the MII. 388 */ 389 STATIC int 390 rtk_mii_writereg(struct rtk_softc *sc, struct rtk_mii_frame *frame) 391 { 392 int s; 393 394 s = splnet(); 395 /* 396 * Set up frame for TX. 397 */ 398 frame->mii_stdelim = RTK_MII_STARTDELIM; 399 frame->mii_opcode = RTK_MII_WRITEOP; 400 frame->mii_turnaround = RTK_MII_TURNAROUND; 401 402 /* 403 * Turn on data output. 404 */ 405 MII_SET(RTK_MII_DIR); 406 407 rtk_mii_sync(sc); 408 409 rtk_mii_send(sc, frame->mii_stdelim, 2); 410 rtk_mii_send(sc, frame->mii_opcode, 2); 411 rtk_mii_send(sc, frame->mii_phyaddr, 5); 412 rtk_mii_send(sc, frame->mii_regaddr, 5); 413 rtk_mii_send(sc, frame->mii_turnaround, 2); 414 rtk_mii_send(sc, frame->mii_data, 16); 415 416 /* Idle bit. */ 417 MII_SET(RTK_MII_CLK); 418 DELAY(1); 419 MII_CLR(RTK_MII_CLK); 420 DELAY(1); 421 422 /* 423 * Turn off xmit. 424 */ 425 MII_CLR(RTK_MII_DIR); 426 427 splx(s); 428 429 return 0; 430 } 431 432 STATIC int 433 rtk_phy_readreg(struct device *self, int phy, int reg) 434 { 435 struct rtk_softc *sc = (void *)self; 436 struct rtk_mii_frame frame; 437 int rval; 438 int rtk8139_reg; 439 440 if ((sc->sc_quirk & RTKQ_8129) == 0) { 441 if (phy != 7) 442 return 0; 443 444 switch (reg) { 445 case MII_BMCR: 446 rtk8139_reg = RTK_BMCR; 447 break; 448 case MII_BMSR: 449 rtk8139_reg = RTK_BMSR; 450 break; 451 case MII_ANAR: 452 rtk8139_reg = RTK_ANAR; 453 break; 454 case MII_ANER: 455 rtk8139_reg = RTK_ANER; 456 break; 457 case MII_ANLPAR: 458 rtk8139_reg = RTK_LPAR; 459 break; 460 default: 461 #if 0 462 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 463 #endif 464 return 0; 465 } 466 rval = CSR_READ_2(sc, rtk8139_reg); 467 return rval; 468 } 469 470 memset((char *)&frame, 0, sizeof(frame)); 471 472 frame.mii_phyaddr = phy; 473 frame.mii_regaddr = reg; 474 rtk_mii_readreg(sc, &frame); 475 476 return frame.mii_data; 477 } 478 479 STATIC void rtk_phy_writereg(struct device *self, int phy, int reg, int data) 480 { 481 struct rtk_softc *sc = (void *)self; 482 struct rtk_mii_frame frame; 483 int rtk8139_reg; 484 485 if ((sc->sc_quirk & RTKQ_8129) == 0) { 486 if (phy != 7) 487 return; 488 489 switch (reg) { 490 case MII_BMCR: 491 rtk8139_reg = RTK_BMCR; 492 break; 493 case MII_BMSR: 494 rtk8139_reg = RTK_BMSR; 495 break; 496 case MII_ANAR: 497 rtk8139_reg = RTK_ANAR; 498 break; 499 case MII_ANER: 500 rtk8139_reg = RTK_ANER; 501 break; 502 case MII_ANLPAR: 503 rtk8139_reg = RTK_LPAR; 504 break; 505 default: 506 #if 0 507 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 508 #endif 509 return; 510 } 511 CSR_WRITE_2(sc, rtk8139_reg, data); 512 return; 513 } 514 515 memset((char *)&frame, 0, sizeof(frame)); 516 517 frame.mii_phyaddr = phy; 518 frame.mii_regaddr = reg; 519 frame.mii_data = data; 520 521 rtk_mii_writereg(sc, &frame); 522 } 523 524 STATIC void 525 rtk_phy_statchg(struct device *v) 526 { 527 528 /* Nothing to do. */ 529 } 530 531 #define rtk_calchash(addr) \ 532 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 533 534 /* 535 * Program the 64-bit multicast hash filter. 536 */ 537 void 538 rtk_setmulti(struct rtk_softc *sc) 539 { 540 struct ifnet *ifp; 541 uint32_t hashes[2] = { 0, 0 }; 542 uint32_t rxfilt; 543 struct ether_multi *enm; 544 struct ether_multistep step; 545 int h, mcnt; 546 547 ifp = &sc->ethercom.ec_if; 548 549 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 550 551 if (ifp->if_flags & IFF_PROMISC) { 552 allmulti: 553 ifp->if_flags |= IFF_ALLMULTI; 554 rxfilt |= RTK_RXCFG_RX_MULTI; 555 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 556 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 557 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 558 return; 559 } 560 561 /* first, zot all the existing hash bits */ 562 CSR_WRITE_4(sc, RTK_MAR0, 0); 563 CSR_WRITE_4(sc, RTK_MAR4, 0); 564 565 /* now program new ones */ 566 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 567 mcnt = 0; 568 while (enm != NULL) { 569 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 570 ETHER_ADDR_LEN) != 0) 571 goto allmulti; 572 573 h = rtk_calchash(enm->enm_addrlo); 574 if (h < 32) 575 hashes[0] |= (1 << h); 576 else 577 hashes[1] |= (1 << (h - 32)); 578 mcnt++; 579 ETHER_NEXT_MULTI(step, enm); 580 } 581 582 ifp->if_flags &= ~IFF_ALLMULTI; 583 584 if (mcnt) 585 rxfilt |= RTK_RXCFG_RX_MULTI; 586 else 587 rxfilt &= ~RTK_RXCFG_RX_MULTI; 588 589 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 590 591 /* 592 * For some unfathomable reason, RealTek decided to reverse 593 * the order of the multicast hash registers in the PCI Express 594 * parts. This means we have to write the hash pattern in reverse 595 * order for those devices. 596 */ 597 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 598 CSR_WRITE_4(sc, RTK_MAR0, bswap32(hashes[1])); 599 CSR_WRITE_4(sc, RTK_MAR4, bswap32(hashes[0])); 600 } else { 601 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 602 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 603 } 604 } 605 606 void 607 rtk_reset(struct rtk_softc *sc) 608 { 609 int i; 610 611 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 612 613 for (i = 0; i < RTK_TIMEOUT; i++) { 614 DELAY(10); 615 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 616 break; 617 } 618 if (i == RTK_TIMEOUT) 619 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 620 } 621 622 /* 623 * Attach the interface. Allocate softc structures, do ifmedia 624 * setup and ethernet/BPF attach. 625 */ 626 void 627 rtk_attach(struct rtk_softc *sc) 628 { 629 struct ifnet *ifp; 630 struct rtk_tx_desc *txd; 631 uint16_t val; 632 uint8_t eaddr[ETHER_ADDR_LEN]; 633 int error; 634 int i, addr_len; 635 636 callout_init(&sc->rtk_tick_ch); 637 638 /* 639 * Check EEPROM type 9346 or 9356. 640 */ 641 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 642 addr_len = RTK_EEADDR_LEN1; 643 else 644 addr_len = RTK_EEADDR_LEN0; 645 646 /* 647 * Get station address. 648 */ 649 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 650 eaddr[0] = val & 0xff; 651 eaddr[1] = val >> 8; 652 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 653 eaddr[2] = val & 0xff; 654 eaddr[3] = val >> 8; 655 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 656 eaddr[4] = val & 0xff; 657 eaddr[5] = val >> 8; 658 659 if ((error = bus_dmamem_alloc(sc->sc_dmat, 660 RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 661 BUS_DMA_NOWAIT)) != 0) { 662 printf("%s: can't allocate recv buffer, error = %d\n", 663 sc->sc_dev.dv_xname, error); 664 goto fail_0; 665 } 666 667 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 668 RTK_RXBUFLEN + 16, (caddr_t *)&sc->rtk_rx_buf, 669 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 670 printf("%s: can't map recv buffer, error = %d\n", 671 sc->sc_dev.dv_xname, error); 672 goto fail_1; 673 } 674 675 if ((error = bus_dmamap_create(sc->sc_dmat, 676 RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT, 677 &sc->recv_dmamap)) != 0) { 678 printf("%s: can't create recv buffer DMA map, error = %d\n", 679 sc->sc_dev.dv_xname, error); 680 goto fail_2; 681 } 682 683 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 684 sc->rtk_rx_buf, RTK_RXBUFLEN + 16, 685 NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 686 printf("%s: can't load recv buffer DMA map, error = %d\n", 687 sc->sc_dev.dv_xname, error); 688 goto fail_3; 689 } 690 691 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 692 txd = &sc->rtk_tx_descs[i]; 693 if ((error = bus_dmamap_create(sc->sc_dmat, 694 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 695 &txd->txd_dmamap)) != 0) { 696 printf("%s: can't create snd buffer DMA map," 697 " error = %d\n", sc->sc_dev.dv_xname, error); 698 goto fail_4; 699 } 700 txd->txd_txaddr = RTK_TXADDR0 + (i * 4); 701 txd->txd_txstat = RTK_TXSTAT0 + (i * 4); 702 } 703 SIMPLEQ_INIT(&sc->rtk_tx_free); 704 SIMPLEQ_INIT(&sc->rtk_tx_dirty); 705 706 /* 707 * From this point forward, the attachment cannot fail. A failure 708 * before this releases all resources thar may have been 709 * allocated. 710 */ 711 sc->sc_flags |= RTK_ATTACHED; 712 713 /* Reset the adapter. */ 714 rtk_reset(sc); 715 716 printf("%s: Ethernet address %s\n", 717 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 718 719 ifp = &sc->ethercom.ec_if; 720 ifp->if_softc = sc; 721 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 722 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 723 ifp->if_ioctl = rtk_ioctl; 724 ifp->if_start = rtk_start; 725 ifp->if_watchdog = rtk_watchdog; 726 ifp->if_init = rtk_init; 727 ifp->if_stop = rtk_stop; 728 IFQ_SET_READY(&ifp->if_snd); 729 730 /* 731 * Do ifmedia setup. 732 */ 733 sc->mii.mii_ifp = ifp; 734 sc->mii.mii_readreg = rtk_phy_readreg; 735 sc->mii.mii_writereg = rtk_phy_writereg; 736 sc->mii.mii_statchg = rtk_phy_statchg; 737 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, rtk_ifmedia_upd, 738 rtk_ifmedia_sts); 739 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 740 MII_PHY_ANY, MII_OFFSET_ANY, 0); 741 742 /* Choose a default media. */ 743 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 744 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 745 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 746 } else { 747 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 748 } 749 750 /* 751 * Call MI attach routines. 752 */ 753 if_attach(ifp); 754 ether_ifattach(ifp, eaddr); 755 756 /* 757 * Make sure the interface is shutdown during reboot. 758 */ 759 sc->sc_sdhook = shutdownhook_establish(rtk_shutdown, sc); 760 if (sc->sc_sdhook == NULL) 761 printf("%s: WARNING: unable to establish shutdown hook\n", 762 sc->sc_dev.dv_xname); 763 /* 764 * Add a suspend hook to make sure we come back up after a 765 * resume. 766 */ 767 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 768 rtk_power, sc); 769 if (sc->sc_powerhook == NULL) 770 printf("%s: WARNING: unable to establish power hook\n", 771 sc->sc_dev.dv_xname); 772 773 774 #if NRND > 0 775 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 776 RND_TYPE_NET, 0); 777 #endif 778 779 return; 780 fail_4: 781 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 782 txd = &sc->rtk_tx_descs[i]; 783 if (txd->txd_dmamap != NULL) 784 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 785 } 786 fail_3: 787 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 788 fail_2: 789 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 790 RTK_RXBUFLEN + 16); 791 fail_1: 792 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 793 fail_0: 794 return; 795 } 796 797 /* 798 * Initialize the transmit descriptors. 799 */ 800 STATIC int 801 rtk_list_tx_init(struct rtk_softc *sc) 802 { 803 struct rtk_tx_desc *txd; 804 int i; 805 806 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) 807 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 808 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) 809 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 810 811 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 812 txd = &sc->rtk_tx_descs[i]; 813 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 814 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 815 } 816 817 return 0; 818 } 819 820 /* 821 * rtk_activate: 822 * Handle device activation/deactivation requests. 823 */ 824 int 825 rtk_activate(struct device *self, enum devact act) 826 { 827 struct rtk_softc *sc = (void *)self; 828 int s, error; 829 830 error = 0; 831 s = splnet(); 832 switch (act) { 833 case DVACT_ACTIVATE: 834 error = EOPNOTSUPP; 835 break; 836 case DVACT_DEACTIVATE: 837 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 838 if_deactivate(&sc->ethercom.ec_if); 839 break; 840 } 841 splx(s); 842 843 return error; 844 } 845 846 /* 847 * rtk_detach: 848 * Detach a rtk interface. 849 */ 850 int 851 rtk_detach(struct rtk_softc *sc) 852 { 853 struct ifnet *ifp = &sc->ethercom.ec_if; 854 struct rtk_tx_desc *txd; 855 int i; 856 857 /* 858 * Succeed now if there isn't any work to do. 859 */ 860 if ((sc->sc_flags & RTK_ATTACHED) == 0) 861 return 0; 862 863 /* Unhook our tick handler. */ 864 callout_stop(&sc->rtk_tick_ch); 865 866 /* Detach all PHYs. */ 867 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 868 869 /* Delete all remaining media. */ 870 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 871 872 #if NRND > 0 873 rnd_detach_source(&sc->rnd_source); 874 #endif 875 876 ether_ifdetach(ifp); 877 if_detach(ifp); 878 879 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 880 txd = &sc->rtk_tx_descs[i]; 881 if (txd->txd_dmamap != NULL) 882 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 883 } 884 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 885 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 886 RTK_RXBUFLEN + 16); 887 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 888 889 shutdownhook_disestablish(sc->sc_sdhook); 890 powerhook_disestablish(sc->sc_powerhook); 891 892 return 0; 893 } 894 895 /* 896 * rtk_enable: 897 * Enable the RTL81X9 chip. 898 */ 899 int 900 rtk_enable(struct rtk_softc *sc) 901 { 902 903 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 904 if ((*sc->sc_enable)(sc) != 0) { 905 printf("%s: device enable failed\n", 906 sc->sc_dev.dv_xname); 907 return EIO; 908 } 909 sc->sc_flags |= RTK_ENABLED; 910 } 911 return 0; 912 } 913 914 /* 915 * rtk_disable: 916 * Disable the RTL81X9 chip. 917 */ 918 void 919 rtk_disable(struct rtk_softc *sc) 920 { 921 922 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 923 (*sc->sc_disable)(sc); 924 sc->sc_flags &= ~RTK_ENABLED; 925 } 926 } 927 928 /* 929 * rtk_power: 930 * Power management (suspend/resume) hook. 931 */ 932 void 933 rtk_power(int why, void *arg) 934 { 935 struct rtk_softc *sc = (void *)arg; 936 struct ifnet *ifp = &sc->ethercom.ec_if; 937 int s; 938 939 s = splnet(); 940 switch (why) { 941 case PWR_SUSPEND: 942 case PWR_STANDBY: 943 rtk_stop(ifp, 0); 944 if (sc->sc_power != NULL) 945 (*sc->sc_power)(sc, why); 946 break; 947 case PWR_RESUME: 948 if (ifp->if_flags & IFF_UP) { 949 if (sc->sc_power != NULL) 950 (*sc->sc_power)(sc, why); 951 rtk_init(ifp); 952 } 953 break; 954 case PWR_SOFTSUSPEND: 955 case PWR_SOFTSTANDBY: 956 case PWR_SOFTRESUME: 957 break; 958 } 959 splx(s); 960 } 961 962 /* 963 * A frame has been uploaded: pass the resulting mbuf chain up to 964 * the higher level protocols. 965 * 966 * You know there's something wrong with a PCI bus-master chip design. 967 * 968 * The receive operation is badly documented in the datasheet, so I'll 969 * attempt to document it here. The driver provides a buffer area and 970 * places its base address in the RX buffer start address register. 971 * The chip then begins copying frames into the RX buffer. Each frame 972 * is preceded by a 32-bit RX status word which specifies the length 973 * of the frame and certain other status bits. Each frame (starting with 974 * the status word) is also 32-bit aligned. The frame length is in the 975 * first 16 bits of the status word; the lower 15 bits correspond with 976 * the 'rx status register' mentioned in the datasheet. 977 * 978 * Note: to make the Alpha happy, the frame payload needs to be aligned 979 * on a 32-bit boundary. To achieve this, we copy the data to mbuf 980 * shifted forward 2 bytes. 981 */ 982 STATIC void 983 rtk_rxeof(struct rtk_softc *sc) 984 { 985 struct mbuf *m; 986 struct ifnet *ifp; 987 caddr_t rxbufpos, dst; 988 u_int total_len, wrap; 989 uint32_t rxstat; 990 uint16_t cur_rx, new_rx; 991 uint16_t limit; 992 uint16_t rx_bytes, max_bytes; 993 994 ifp = &sc->ethercom.ec_if; 995 996 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 997 998 /* Do not try to read past this point. */ 999 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 1000 1001 if (limit < cur_rx) 1002 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 1003 else 1004 max_bytes = limit - cur_rx; 1005 rx_bytes = 0; 1006 1007 while ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 1008 rxbufpos = sc->rtk_rx_buf + cur_rx; 1009 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1010 RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD); 1011 rxstat = le32toh(*(uint32_t *)rxbufpos); 1012 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1013 RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD); 1014 1015 /* 1016 * Here's a totally undocumented fact for you. When the 1017 * RealTek chip is in the process of copying a packet into 1018 * RAM for you, the length will be 0xfff0. If you spot a 1019 * packet header with this value, you need to stop. The 1020 * datasheet makes absolutely no mention of this and 1021 * RealTek should be shot for this. 1022 */ 1023 total_len = rxstat >> 16; 1024 if (total_len == RTK_RXSTAT_UNFINISHED) 1025 break; 1026 1027 if ((rxstat & RTK_RXSTAT_RXOK) == 0 || 1028 total_len < ETHER_MIN_LEN || 1029 total_len > (MCLBYTES - RTK_ETHER_ALIGN)) { 1030 ifp->if_ierrors++; 1031 1032 /* 1033 * submitted by:[netbsd-pcmcia:00484] 1034 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp> 1035 * obtain from: 1036 * FreeBSD if_rl.c rev 1.24->1.25 1037 * 1038 */ 1039 #if 0 1040 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1041 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1042 RTK_RXSTAT_ALIGNERR)) { 1043 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 1044 CSR_WRITE_2(sc, RTK_COMMAND, 1045 RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1046 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1047 CSR_WRITE_4(sc, RTK_RXADDR, 1048 sc->recv_dmamap->dm_segs[0].ds_addr); 1049 cur_rx = 0; 1050 } 1051 break; 1052 #else 1053 rtk_init(ifp); 1054 return; 1055 #endif 1056 } 1057 1058 /* No errors; receive the packet. */ 1059 rx_bytes += total_len + RTK_RXSTAT_LEN; 1060 1061 /* 1062 * Avoid trying to read more bytes than we know 1063 * the chip has prepared for us. 1064 */ 1065 if (rx_bytes > max_bytes) 1066 break; 1067 1068 /* 1069 * Skip the status word, wrapping around to the beginning 1070 * of the Rx area, if necessary. 1071 */ 1072 cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN; 1073 rxbufpos = sc->rtk_rx_buf + cur_rx; 1074 1075 /* 1076 * Compute the number of bytes at which the packet 1077 * will wrap to the beginning of the ring buffer. 1078 */ 1079 wrap = RTK_RXBUFLEN - cur_rx; 1080 1081 /* 1082 * Compute where the next pending packet is. 1083 */ 1084 if (total_len > wrap) 1085 new_rx = total_len - wrap; 1086 else 1087 new_rx = cur_rx + total_len; 1088 /* Round up to 32-bit boundary. */ 1089 new_rx = ((new_rx + 3) & ~3) % RTK_RXBUFLEN; 1090 1091 /* 1092 * The RealTek chip includes the CRC with every 1093 * incoming packet; trim it off here. 1094 */ 1095 total_len -= ETHER_CRC_LEN; 1096 1097 /* 1098 * Now allocate an mbuf (and possibly a cluster) to hold 1099 * the packet. Note we offset the packet 2 bytes so that 1100 * data after the Ethernet header will be 4-byte aligned. 1101 */ 1102 MGETHDR(m, M_DONTWAIT, MT_DATA); 1103 if (m == NULL) { 1104 printf("%s: unable to allocate Rx mbuf\n", 1105 sc->sc_dev.dv_xname); 1106 ifp->if_ierrors++; 1107 goto next_packet; 1108 } 1109 if (total_len > (MHLEN - RTK_ETHER_ALIGN)) { 1110 MCLGET(m, M_DONTWAIT); 1111 if ((m->m_flags & M_EXT) == 0) { 1112 printf("%s: unable to allocate Rx cluster\n", 1113 sc->sc_dev.dv_xname); 1114 ifp->if_ierrors++; 1115 m_freem(m); 1116 m = NULL; 1117 goto next_packet; 1118 } 1119 } 1120 m->m_data += RTK_ETHER_ALIGN; /* for alignment */ 1121 m->m_pkthdr.rcvif = ifp; 1122 m->m_pkthdr.len = m->m_len = total_len; 1123 dst = mtod(m, caddr_t); 1124 1125 /* 1126 * If the packet wraps, copy up to the wrapping point. 1127 */ 1128 if (total_len > wrap) { 1129 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1130 cur_rx, wrap, BUS_DMASYNC_POSTREAD); 1131 memcpy(dst, rxbufpos, wrap); 1132 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1133 cur_rx, wrap, BUS_DMASYNC_PREREAD); 1134 cur_rx = 0; 1135 rxbufpos = sc->rtk_rx_buf; 1136 total_len -= wrap; 1137 dst += wrap; 1138 } 1139 1140 /* 1141 * ...and now the rest. 1142 */ 1143 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1144 cur_rx, total_len, BUS_DMASYNC_POSTREAD); 1145 memcpy(dst, rxbufpos, total_len); 1146 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1147 cur_rx, total_len, BUS_DMASYNC_PREREAD); 1148 1149 next_packet: 1150 CSR_WRITE_2(sc, RTK_CURRXADDR, (new_rx - 16) % RTK_RXBUFLEN); 1151 cur_rx = new_rx; 1152 1153 if (m == NULL) 1154 continue; 1155 1156 ifp->if_ipackets++; 1157 1158 #if NBPFILTER > 0 1159 if (ifp->if_bpf) 1160 bpf_mtap(ifp->if_bpf, m); 1161 #endif 1162 /* pass it on. */ 1163 (*ifp->if_input)(ifp, m); 1164 } 1165 } 1166 1167 /* 1168 * A frame was downloaded to the chip. It's safe for us to clean up 1169 * the list buffers. 1170 */ 1171 STATIC void 1172 rtk_txeof(struct rtk_softc *sc) 1173 { 1174 struct ifnet *ifp; 1175 struct rtk_tx_desc *txd; 1176 uint32_t txstat; 1177 1178 ifp = &sc->ethercom.ec_if; 1179 1180 /* 1181 * Go through our tx list and free mbufs for those 1182 * frames that have been uploaded. 1183 */ 1184 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1185 txstat = CSR_READ_4(sc, txd->txd_txstat); 1186 if ((txstat & (RTK_TXSTAT_TX_OK| 1187 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0) 1188 break; 1189 1190 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1191 1192 bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0, 1193 txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1194 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1195 m_freem(txd->txd_mbuf); 1196 txd->txd_mbuf = NULL; 1197 1198 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1199 1200 if (txstat & RTK_TXSTAT_TX_OK) 1201 ifp->if_opackets++; 1202 else { 1203 ifp->if_oerrors++; 1204 1205 /* 1206 * Increase Early TX threshold if underrun occurred. 1207 * Increase step 64 bytes. 1208 */ 1209 if (txstat & RTK_TXSTAT_TX_UNDERRUN) { 1210 #ifdef DEBUG 1211 printf("%s: transmit underrun;", 1212 sc->sc_dev.dv_xname); 1213 #endif 1214 if (sc->sc_txthresh < RTK_TXTH_MAX) { 1215 sc->sc_txthresh += 2; 1216 #ifdef DEBUG 1217 printf(" new threshold: %d bytes", 1218 sc->sc_txthresh * 32); 1219 #endif 1220 } 1221 printf("\n"); 1222 } 1223 if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN)) 1224 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1225 } 1226 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 1227 ifp->if_flags &= ~IFF_OACTIVE; 1228 } 1229 1230 /* Clear the timeout timer if there is no pending packet. */ 1231 if (SIMPLEQ_EMPTY(&sc->rtk_tx_dirty)) 1232 ifp->if_timer = 0; 1233 1234 } 1235 1236 int 1237 rtk_intr(void *arg) 1238 { 1239 struct rtk_softc *sc; 1240 struct ifnet *ifp; 1241 uint16_t status; 1242 int handled; 1243 1244 sc = arg; 1245 ifp = &sc->ethercom.ec_if; 1246 1247 /* Disable interrupts. */ 1248 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1249 1250 handled = 0; 1251 for (;;) { 1252 1253 status = CSR_READ_2(sc, RTK_ISR); 1254 1255 if (status == 0xffff) 1256 break; /* Card is gone... */ 1257 1258 if (status) 1259 CSR_WRITE_2(sc, RTK_ISR, status); 1260 1261 if ((status & RTK_INTRS) == 0) 1262 break; 1263 1264 handled = 1; 1265 1266 if (status & RTK_ISR_RX_OK) 1267 rtk_rxeof(sc); 1268 1269 if (status & RTK_ISR_RX_ERR) 1270 rtk_rxeof(sc); 1271 1272 if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR)) 1273 rtk_txeof(sc); 1274 1275 if (status & RTK_ISR_SYSTEM_ERR) { 1276 rtk_reset(sc); 1277 rtk_init(ifp); 1278 } 1279 } 1280 1281 /* Re-enable interrupts. */ 1282 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1283 1284 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1285 rtk_start(ifp); 1286 1287 #if NRND > 0 1288 if (RND_ENABLED(&sc->rnd_source)) 1289 rnd_add_uint32(&sc->rnd_source, status); 1290 #endif 1291 1292 return handled; 1293 } 1294 1295 /* 1296 * Main transmit routine. 1297 */ 1298 1299 STATIC void 1300 rtk_start(struct ifnet *ifp) 1301 { 1302 struct rtk_softc *sc; 1303 struct rtk_tx_desc *txd; 1304 struct mbuf *m_head, *m_new; 1305 int error, len; 1306 1307 sc = ifp->if_softc; 1308 1309 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) { 1310 IFQ_POLL(&ifp->if_snd, m_head); 1311 if (m_head == NULL) 1312 break; 1313 m_new = NULL; 1314 1315 /* 1316 * Load the DMA map. If this fails, the packet didn't 1317 * fit in one DMA segment, and we need to copy. Note, 1318 * the packet must also be aligned. 1319 * if the packet is too small, copy it too, so we're sure 1320 * so have enouth room for the pad buffer. 1321 */ 1322 if ((mtod(m_head, uintptr_t) & 3) != 0 || 1323 m_head->m_pkthdr.len < ETHER_PAD_LEN || 1324 bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap, 1325 m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1326 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1327 if (m_new == NULL) { 1328 printf("%s: unable to allocate Tx mbuf\n", 1329 sc->sc_dev.dv_xname); 1330 break; 1331 } 1332 if (m_head->m_pkthdr.len > MHLEN) { 1333 MCLGET(m_new, M_DONTWAIT); 1334 if ((m_new->m_flags & M_EXT) == 0) { 1335 printf("%s: unable to allocate Tx " 1336 "cluster\n", sc->sc_dev.dv_xname); 1337 m_freem(m_new); 1338 break; 1339 } 1340 } 1341 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1342 mtod(m_new, caddr_t)); 1343 m_new->m_pkthdr.len = m_new->m_len = 1344 m_head->m_pkthdr.len; 1345 if (m_head->m_pkthdr.len < ETHER_PAD_LEN) { 1346 memset( 1347 mtod(m_new, caddr_t) + m_head->m_pkthdr.len, 1348 0, ETHER_PAD_LEN - m_head->m_pkthdr.len); 1349 m_new->m_pkthdr.len = m_new->m_len = 1350 ETHER_PAD_LEN; 1351 } 1352 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1353 txd->txd_dmamap, m_new, 1354 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1355 if (error) { 1356 printf("%s: unable to load Tx buffer, " 1357 "error = %d\n", sc->sc_dev.dv_xname, error); 1358 break; 1359 } 1360 } 1361 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1362 #if NBPFILTER > 0 1363 /* 1364 * If there's a BPF listener, bounce a copy of this frame 1365 * to him. 1366 */ 1367 if (ifp->if_bpf) 1368 bpf_mtap(ifp->if_bpf, m_head); 1369 #endif 1370 if (m_new != NULL) { 1371 m_freem(m_head); 1372 m_head = m_new; 1373 } 1374 txd->txd_mbuf = m_head; 1375 1376 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 1377 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q); 1378 1379 /* 1380 * Transmit the frame. 1381 */ 1382 bus_dmamap_sync(sc->sc_dmat, 1383 txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize, 1384 BUS_DMASYNC_PREWRITE); 1385 1386 len = txd->txd_dmamap->dm_segs[0].ds_len; 1387 1388 CSR_WRITE_4(sc, txd->txd_txaddr, 1389 txd->txd_dmamap->dm_segs[0].ds_addr); 1390 CSR_WRITE_4(sc, txd->txd_txstat, 1391 RTK_TXSTAT_THRESH(sc->sc_txthresh) | len); 1392 1393 /* 1394 * Set a timeout in case the chip goes out to lunch. 1395 */ 1396 ifp->if_timer = 5; 1397 } 1398 1399 /* 1400 * We broke out of the loop because all our TX slots are 1401 * full. Mark the NIC as busy until it drains some of the 1402 * packets from the queue. 1403 */ 1404 if (SIMPLEQ_EMPTY(&sc->rtk_tx_free)) 1405 ifp->if_flags |= IFF_OACTIVE; 1406 } 1407 1408 STATIC int 1409 rtk_init(struct ifnet *ifp) 1410 { 1411 struct rtk_softc *sc = ifp->if_softc; 1412 int error, i; 1413 uint32_t rxcfg; 1414 1415 if ((error = rtk_enable(sc)) != 0) 1416 goto out; 1417 1418 /* 1419 * Cancel pending I/O. 1420 */ 1421 rtk_stop(ifp, 0); 1422 1423 /* Init our MAC address */ 1424 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1425 CSR_WRITE_1(sc, RTK_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1426 } 1427 1428 /* Init the RX buffer pointer register. */ 1429 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1430 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1431 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1432 1433 /* Init TX descriptors. */ 1434 rtk_list_tx_init(sc); 1435 1436 /* Init Early TX threshold. */ 1437 sc->sc_txthresh = RTK_TXTH_256; 1438 /* 1439 * Enable transmit and receive. 1440 */ 1441 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1442 1443 /* 1444 * Set the initial TX and RX configuration. 1445 */ 1446 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1447 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1448 1449 /* Set the individual bit to receive frames for this host only. */ 1450 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1451 rxcfg |= RTK_RXCFG_RX_INDIV; 1452 1453 /* If we want promiscuous mode, set the allframes bit. */ 1454 if (ifp->if_flags & IFF_PROMISC) { 1455 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1456 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1457 } else { 1458 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1459 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1460 } 1461 1462 /* 1463 * Set capture broadcast bit to capture broadcast frames. 1464 */ 1465 if (ifp->if_flags & IFF_BROADCAST) { 1466 rxcfg |= RTK_RXCFG_RX_BROAD; 1467 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1468 } else { 1469 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1470 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1471 } 1472 1473 /* 1474 * Program the multicast filter, if necessary. 1475 */ 1476 rtk_setmulti(sc); 1477 1478 /* 1479 * Enable interrupts. 1480 */ 1481 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1482 1483 /* Start RX/TX process. */ 1484 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1485 1486 /* Enable receiver and transmitter. */ 1487 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1488 1489 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1490 1491 /* 1492 * Set current media. 1493 */ 1494 mii_mediachg(&sc->mii); 1495 1496 ifp->if_flags |= IFF_RUNNING; 1497 ifp->if_flags &= ~IFF_OACTIVE; 1498 1499 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1500 1501 out: 1502 if (error) { 1503 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1504 ifp->if_timer = 0; 1505 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1506 } 1507 return error; 1508 } 1509 1510 /* 1511 * Set media options. 1512 */ 1513 STATIC int 1514 rtk_ifmedia_upd(struct ifnet *ifp) 1515 { 1516 struct rtk_softc *sc; 1517 1518 sc = ifp->if_softc; 1519 1520 return mii_mediachg(&sc->mii); 1521 } 1522 1523 /* 1524 * Report current media status. 1525 */ 1526 STATIC void 1527 rtk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1528 { 1529 struct rtk_softc *sc; 1530 1531 sc = ifp->if_softc; 1532 1533 mii_pollstat(&sc->mii); 1534 ifmr->ifm_status = sc->mii.mii_media_status; 1535 ifmr->ifm_active = sc->mii.mii_media_active; 1536 } 1537 1538 STATIC int 1539 rtk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1540 { 1541 struct rtk_softc *sc = ifp->if_softc; 1542 struct ifreq *ifr = (struct ifreq *)data; 1543 int s, error; 1544 1545 s = splnet(); 1546 1547 switch (command) { 1548 case SIOCGIFMEDIA: 1549 case SIOCSIFMEDIA: 1550 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1551 break; 1552 1553 default: 1554 error = ether_ioctl(ifp, command, data); 1555 if (error == ENETRESET) { 1556 if (ifp->if_flags & IFF_RUNNING) { 1557 /* 1558 * Multicast list has changed. Set the 1559 * hardware filter accordingly. 1560 */ 1561 rtk_setmulti(sc); 1562 } 1563 error = 0; 1564 } 1565 break; 1566 } 1567 1568 splx(s); 1569 1570 return error; 1571 } 1572 1573 STATIC void 1574 rtk_watchdog(struct ifnet *ifp) 1575 { 1576 struct rtk_softc *sc; 1577 1578 sc = ifp->if_softc; 1579 1580 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1581 ifp->if_oerrors++; 1582 rtk_txeof(sc); 1583 rtk_rxeof(sc); 1584 rtk_init(ifp); 1585 } 1586 1587 /* 1588 * Stop the adapter and free any mbufs allocated to the 1589 * RX and TX lists. 1590 */ 1591 STATIC void 1592 rtk_stop(struct ifnet *ifp, int disable) 1593 { 1594 struct rtk_softc *sc = ifp->if_softc; 1595 struct rtk_tx_desc *txd; 1596 1597 callout_stop(&sc->rtk_tick_ch); 1598 1599 mii_down(&sc->mii); 1600 1601 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1602 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1603 1604 /* 1605 * Free the TX list buffers. 1606 */ 1607 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1608 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1609 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1610 m_freem(txd->txd_mbuf); 1611 txd->txd_mbuf = NULL; 1612 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 1613 } 1614 1615 if (disable) 1616 rtk_disable(sc); 1617 1618 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1619 ifp->if_timer = 0; 1620 } 1621 1622 /* 1623 * Stop all chip I/O so that the kernel's probe routines don't 1624 * get confused by errant DMAs when rebooting. 1625 */ 1626 STATIC void 1627 rtk_shutdown(void *arg) 1628 { 1629 struct rtk_softc *sc = (struct rtk_softc *)arg; 1630 1631 rtk_stop(&sc->ethercom.ec_if, 0); 1632 } 1633 1634 STATIC void 1635 rtk_tick(void *arg) 1636 { 1637 struct rtk_softc *sc = arg; 1638 int s; 1639 1640 s = splnet(); 1641 mii_tick(&sc->mii); 1642 splx(s); 1643 1644 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1645 }
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