FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/rtl81x9.c
1 /* $NetBSD: rtl81x9.c,v 1.82 2008/04/25 11:27:19 tsutsui Exp $ */
2
3 /*
4 * Copyright (c) 1997, 1998
5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp
35 */
36
37 /*
38 * RealTek 8129/8139 PCI NIC driver
39 *
40 * Supports several extremely cheap PCI 10/100 adapters based on
41 * the RealTek chipset. Datasheets can be obtained from
42 * www.realtek.com.tw.
43 *
44 * Written by Bill Paul <wpaul@ctr.columbia.edu>
45 * Electrical Engineering Department
46 * Columbia University, New York City
47 */
48
49 /*
50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is
51 * probably the worst PCI ethernet controller ever made, with the possible
52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master
53 * DMA, but it has a terrible interface that nullifies any performance
54 * gains that bus-master DMA usually offers.
55 *
56 * For transmission, the chip offers a series of four TX descriptor
57 * registers. Each transmit frame must be in a contiguous buffer, aligned
58 * on a longword (32-bit) boundary. This means we almost always have to
59 * do mbuf copies in order to transmit a frame, except in the unlikely
60 * case where a) the packet fits into a single mbuf, and b) the packet
61 * is 32-bit aligned within the mbuf's data area. The presence of only
62 * four descriptor registers means that we can never have more than four
63 * packets queued for transmission at any one time.
64 *
65 * Reception is not much better. The driver has to allocate a single large
66 * buffer area (up to 64K in size) into which the chip will DMA received
67 * frames. Because we don't know where within this region received packets
68 * will begin or end, we have no choice but to copy data from the buffer
69 * area into mbufs in order to pass the packets up to the higher protocol
70 * levels.
71 *
72 * It's impossible given this rotten design to really achieve decent
73 * performance at 100Mbps, unless you happen to have a 400MHz PII or
74 * some equally overmuscled CPU to drive it.
75 *
76 * On the bright side, the 8139 does have a built-in PHY, although
77 * rather than using an MDIO serial interface like most other NICs, the
78 * PHY registers are directly accessible through the 8139's register
79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast
80 * filter.
81 *
82 * The 8129 chip is an older version of the 8139 that uses an external PHY
83 * chip. The 8129 has a serial MDIO interface for accessing the MII where
84 * the 8139 lets you directly access the on-board PHY registers. We need
85 * to select which interface to use depending on the chip type.
86 */
87
88 #include <sys/cdefs.h>
89 __KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.82 2008/04/25 11:27:19 tsutsui Exp $");
90
91 #include "bpfilter.h"
92 #include "rnd.h"
93
94 #include <sys/param.h>
95 #include <sys/systm.h>
96 #include <sys/callout.h>
97 #include <sys/device.h>
98 #include <sys/sockio.h>
99 #include <sys/mbuf.h>
100 #include <sys/malloc.h>
101 #include <sys/kernel.h>
102 #include <sys/socket.h>
103
104 #include <uvm/uvm_extern.h>
105
106 #include <net/if.h>
107 #include <net/if_arp.h>
108 #include <net/if_ether.h>
109 #include <net/if_dl.h>
110 #include <net/if_media.h>
111
112 #if NBPFILTER > 0
113 #include <net/bpf.h>
114 #endif
115 #if NRND > 0
116 #include <sys/rnd.h>
117 #endif
118
119 #include <sys/bus.h>
120 #include <machine/endian.h>
121
122 #include <dev/mii/mii.h>
123 #include <dev/mii/miivar.h>
124
125 #include <dev/ic/rtl81x9reg.h>
126 #include <dev/ic/rtl81x9var.h>
127
128 #if defined(DEBUG)
129 #define STATIC
130 #else
131 #define STATIC static
132 #endif
133
134 STATIC void rtk_reset(struct rtk_softc *);
135 STATIC void rtk_rxeof(struct rtk_softc *);
136 STATIC void rtk_txeof(struct rtk_softc *);
137 STATIC void rtk_start(struct ifnet *);
138 STATIC int rtk_ioctl(struct ifnet *, u_long, void *);
139 STATIC int rtk_init(struct ifnet *);
140 STATIC void rtk_stop(struct ifnet *, int);
141
142 STATIC void rtk_watchdog(struct ifnet *);
143
144 STATIC void rtk_eeprom_putbyte(struct rtk_softc *, int, int);
145 STATIC void rtk_mii_sync(struct rtk_softc *);
146 STATIC void rtk_mii_send(struct rtk_softc *, uint32_t, int);
147 STATIC int rtk_mii_readreg(struct rtk_softc *, struct rtk_mii_frame *);
148 STATIC int rtk_mii_writereg(struct rtk_softc *, struct rtk_mii_frame *);
149
150 STATIC int rtk_phy_readreg(device_t, int, int);
151 STATIC void rtk_phy_writereg(device_t, int, int, int);
152 STATIC void rtk_phy_statchg(device_t);
153 STATIC void rtk_tick(void *);
154
155 STATIC int rtk_enable(struct rtk_softc *);
156 STATIC void rtk_disable(struct rtk_softc *);
157
158 STATIC void rtk_list_tx_init(struct rtk_softc *);
159
160 #define EE_SET(x) \
161 CSR_WRITE_1(sc, RTK_EECMD, \
162 CSR_READ_1(sc, RTK_EECMD) | (x))
163
164 #define EE_CLR(x) \
165 CSR_WRITE_1(sc, RTK_EECMD, \
166 CSR_READ_1(sc, RTK_EECMD) & ~(x))
167
168 #define EE_DELAY() DELAY(100)
169
170 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
171
172 /*
173 * Send a read command and address to the EEPROM, check for ACK.
174 */
175 STATIC void
176 rtk_eeprom_putbyte(struct rtk_softc *sc, int addr, int addr_len)
177 {
178 int d, i;
179
180 d = (RTK_EECMD_READ << addr_len) | addr;
181
182 /*
183 * Feed in each bit and stobe the clock.
184 */
185 for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) {
186 if (d & (1 << (i - 1))) {
187 EE_SET(RTK_EE_DATAIN);
188 } else {
189 EE_CLR(RTK_EE_DATAIN);
190 }
191 EE_DELAY();
192 EE_SET(RTK_EE_CLK);
193 EE_DELAY();
194 EE_CLR(RTK_EE_CLK);
195 EE_DELAY();
196 }
197 }
198
199 /*
200 * Read a word of data stored in the EEPROM at address 'addr.'
201 */
202 uint16_t
203 rtk_read_eeprom(struct rtk_softc *sc, int addr, int addr_len)
204 {
205 uint16_t word;
206 int i;
207
208 /* Enter EEPROM access mode. */
209 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM);
210 EE_DELAY();
211 EE_SET(RTK_EE_SEL);
212
213 /*
214 * Send address of word we want to read.
215 */
216 rtk_eeprom_putbyte(sc, addr, addr_len);
217
218 /*
219 * Start reading bits from EEPROM.
220 */
221 word = 0;
222 for (i = 16; i > 0; i--) {
223 EE_SET(RTK_EE_CLK);
224 EE_DELAY();
225 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT)
226 word |= 1 << (i - 1);
227 EE_CLR(RTK_EE_CLK);
228 EE_DELAY();
229 }
230
231 /* Turn off EEPROM access mode. */
232 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF);
233
234 return word;
235 }
236
237 /*
238 * MII access routines are provided for the 8129, which
239 * doesn't have a built-in PHY. For the 8139, we fake things
240 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the
241 * direct access PHY registers.
242 */
243 #define MII_SET(x) \
244 CSR_WRITE_1(sc, RTK_MII, \
245 CSR_READ_1(sc, RTK_MII) | (x))
246
247 #define MII_CLR(x) \
248 CSR_WRITE_1(sc, RTK_MII, \
249 CSR_READ_1(sc, RTK_MII) & ~(x))
250
251 /*
252 * Sync the PHYs by setting data bit and strobing the clock 32 times.
253 */
254 STATIC void
255 rtk_mii_sync(struct rtk_softc *sc)
256 {
257 int i;
258
259 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT);
260
261 for (i = 0; i < 32; i++) {
262 MII_SET(RTK_MII_CLK);
263 DELAY(1);
264 MII_CLR(RTK_MII_CLK);
265 DELAY(1);
266 }
267 }
268
269 /*
270 * Clock a series of bits through the MII.
271 */
272 STATIC void
273 rtk_mii_send(struct rtk_softc *sc, uint32_t bits, int cnt)
274 {
275 int i;
276
277 MII_CLR(RTK_MII_CLK);
278
279 for (i = cnt; i > 0; i--) {
280 if (bits & (1 << (i - 1))) {
281 MII_SET(RTK_MII_DATAOUT);
282 } else {
283 MII_CLR(RTK_MII_DATAOUT);
284 }
285 DELAY(1);
286 MII_CLR(RTK_MII_CLK);
287 DELAY(1);
288 MII_SET(RTK_MII_CLK);
289 }
290 }
291
292 /*
293 * Read an PHY register through the MII.
294 */
295 STATIC int
296 rtk_mii_readreg(struct rtk_softc *sc, struct rtk_mii_frame *frame)
297 {
298 int i, ack, s;
299
300 s = splnet();
301
302 /*
303 * Set up frame for RX.
304 */
305 frame->mii_stdelim = RTK_MII_STARTDELIM;
306 frame->mii_opcode = RTK_MII_READOP;
307 frame->mii_turnaround = 0;
308 frame->mii_data = 0;
309
310 CSR_WRITE_2(sc, RTK_MII, 0);
311
312 /*
313 * Turn on data xmit.
314 */
315 MII_SET(RTK_MII_DIR);
316
317 rtk_mii_sync(sc);
318
319 /*
320 * Send command/address info.
321 */
322 rtk_mii_send(sc, frame->mii_stdelim, 2);
323 rtk_mii_send(sc, frame->mii_opcode, 2);
324 rtk_mii_send(sc, frame->mii_phyaddr, 5);
325 rtk_mii_send(sc, frame->mii_regaddr, 5);
326
327 /* Idle bit */
328 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT));
329 DELAY(1);
330 MII_SET(RTK_MII_CLK);
331 DELAY(1);
332
333 /* Turn off xmit. */
334 MII_CLR(RTK_MII_DIR);
335
336 /* Check for ack */
337 MII_CLR(RTK_MII_CLK);
338 DELAY(1);
339 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN;
340 MII_SET(RTK_MII_CLK);
341 DELAY(1);
342
343 /*
344 * Now try reading data bits. If the ack failed, we still
345 * need to clock through 16 cycles to keep the PHY(s) in sync.
346 */
347 if (ack) {
348 for (i = 0; i < 16; i++) {
349 MII_CLR(RTK_MII_CLK);
350 DELAY(1);
351 MII_SET(RTK_MII_CLK);
352 DELAY(1);
353 }
354 goto fail;
355 }
356
357 for (i = 16; i > 0; i--) {
358 MII_CLR(RTK_MII_CLK);
359 DELAY(1);
360 if (!ack) {
361 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN)
362 frame->mii_data |= 1 << (i - 1);
363 DELAY(1);
364 }
365 MII_SET(RTK_MII_CLK);
366 DELAY(1);
367 }
368
369 fail:
370 MII_CLR(RTK_MII_CLK);
371 DELAY(1);
372 MII_SET(RTK_MII_CLK);
373 DELAY(1);
374
375 splx(s);
376
377 if (ack)
378 return 1;
379 return 0;
380 }
381
382 /*
383 * Write to a PHY register through the MII.
384 */
385 STATIC int
386 rtk_mii_writereg(struct rtk_softc *sc, struct rtk_mii_frame *frame)
387 {
388 int s;
389
390 s = splnet();
391 /*
392 * Set up frame for TX.
393 */
394 frame->mii_stdelim = RTK_MII_STARTDELIM;
395 frame->mii_opcode = RTK_MII_WRITEOP;
396 frame->mii_turnaround = RTK_MII_TURNAROUND;
397
398 /*
399 * Turn on data output.
400 */
401 MII_SET(RTK_MII_DIR);
402
403 rtk_mii_sync(sc);
404
405 rtk_mii_send(sc, frame->mii_stdelim, 2);
406 rtk_mii_send(sc, frame->mii_opcode, 2);
407 rtk_mii_send(sc, frame->mii_phyaddr, 5);
408 rtk_mii_send(sc, frame->mii_regaddr, 5);
409 rtk_mii_send(sc, frame->mii_turnaround, 2);
410 rtk_mii_send(sc, frame->mii_data, 16);
411
412 /* Idle bit. */
413 MII_SET(RTK_MII_CLK);
414 DELAY(1);
415 MII_CLR(RTK_MII_CLK);
416 DELAY(1);
417
418 /*
419 * Turn off xmit.
420 */
421 MII_CLR(RTK_MII_DIR);
422
423 splx(s);
424
425 return 0;
426 }
427
428 STATIC int
429 rtk_phy_readreg(device_t self, int phy, int reg)
430 {
431 struct rtk_softc *sc = device_private(self);
432 struct rtk_mii_frame frame;
433 int rval;
434 int rtk8139_reg;
435
436 if ((sc->sc_quirk & RTKQ_8129) == 0) {
437 if (phy != 7)
438 return 0;
439
440 switch (reg) {
441 case MII_BMCR:
442 rtk8139_reg = RTK_BMCR;
443 break;
444 case MII_BMSR:
445 rtk8139_reg = RTK_BMSR;
446 break;
447 case MII_ANAR:
448 rtk8139_reg = RTK_ANAR;
449 break;
450 case MII_ANER:
451 rtk8139_reg = RTK_ANER;
452 break;
453 case MII_ANLPAR:
454 rtk8139_reg = RTK_LPAR;
455 break;
456 default:
457 #if 0
458 printf("%s: bad phy register\n", device_xname(self));
459 #endif
460 return 0;
461 }
462 rval = CSR_READ_2(sc, rtk8139_reg);
463 return rval;
464 }
465
466 memset((char *)&frame, 0, sizeof(frame));
467
468 frame.mii_phyaddr = phy;
469 frame.mii_regaddr = reg;
470 rtk_mii_readreg(sc, &frame);
471
472 return frame.mii_data;
473 }
474
475 STATIC void
476 rtk_phy_writereg(device_t self, int phy, int reg, int data)
477 {
478 struct rtk_softc *sc = device_private(self);
479 struct rtk_mii_frame frame;
480 int rtk8139_reg;
481
482 if ((sc->sc_quirk & RTKQ_8129) == 0) {
483 if (phy != 7)
484 return;
485
486 switch (reg) {
487 case MII_BMCR:
488 rtk8139_reg = RTK_BMCR;
489 break;
490 case MII_BMSR:
491 rtk8139_reg = RTK_BMSR;
492 break;
493 case MII_ANAR:
494 rtk8139_reg = RTK_ANAR;
495 break;
496 case MII_ANER:
497 rtk8139_reg = RTK_ANER;
498 break;
499 case MII_ANLPAR:
500 rtk8139_reg = RTK_LPAR;
501 break;
502 default:
503 #if 0
504 printf("%s: bad phy register\n", device_xname(self));
505 #endif
506 return;
507 }
508 CSR_WRITE_2(sc, rtk8139_reg, data);
509 return;
510 }
511
512 memset((char *)&frame, 0, sizeof(frame));
513
514 frame.mii_phyaddr = phy;
515 frame.mii_regaddr = reg;
516 frame.mii_data = data;
517
518 rtk_mii_writereg(sc, &frame);
519 }
520
521 STATIC void
522 rtk_phy_statchg(device_t v)
523 {
524
525 /* Nothing to do. */
526 }
527
528 #define rtk_calchash(addr) \
529 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26)
530
531 /*
532 * Program the 64-bit multicast hash filter.
533 */
534 void
535 rtk_setmulti(struct rtk_softc *sc)
536 {
537 struct ifnet *ifp;
538 uint32_t hashes[2] = { 0, 0 };
539 uint32_t rxfilt;
540 struct ether_multi *enm;
541 struct ether_multistep step;
542 int h, mcnt;
543
544 ifp = &sc->ethercom.ec_if;
545
546 rxfilt = CSR_READ_4(sc, RTK_RXCFG);
547
548 if (ifp->if_flags & IFF_PROMISC) {
549 allmulti:
550 ifp->if_flags |= IFF_ALLMULTI;
551 rxfilt |= RTK_RXCFG_RX_MULTI;
552 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt);
553 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF);
554 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF);
555 return;
556 }
557
558 /* first, zot all the existing hash bits */
559 CSR_WRITE_4(sc, RTK_MAR0, 0);
560 CSR_WRITE_4(sc, RTK_MAR4, 0);
561
562 /* now program new ones */
563 ETHER_FIRST_MULTI(step, &sc->ethercom, enm);
564 mcnt = 0;
565 while (enm != NULL) {
566 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
567 ETHER_ADDR_LEN) != 0)
568 goto allmulti;
569
570 h = rtk_calchash(enm->enm_addrlo);
571 if (h < 32)
572 hashes[0] |= (1 << h);
573 else
574 hashes[1] |= (1 << (h - 32));
575 mcnt++;
576 ETHER_NEXT_MULTI(step, enm);
577 }
578
579 ifp->if_flags &= ~IFF_ALLMULTI;
580
581 if (mcnt)
582 rxfilt |= RTK_RXCFG_RX_MULTI;
583 else
584 rxfilt &= ~RTK_RXCFG_RX_MULTI;
585
586 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt);
587
588 /*
589 * For some unfathomable reason, RealTek decided to reverse
590 * the order of the multicast hash registers in the PCI Express
591 * parts. This means we have to write the hash pattern in reverse
592 * order for those devices.
593 */
594 if ((sc->sc_quirk & RTKQ_PCIE) != 0) {
595 CSR_WRITE_4(sc, RTK_MAR0, bswap32(hashes[1]));
596 CSR_WRITE_4(sc, RTK_MAR4, bswap32(hashes[0]));
597 } else {
598 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]);
599 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]);
600 }
601 }
602
603 void
604 rtk_reset(struct rtk_softc *sc)
605 {
606 int i;
607
608 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET);
609
610 for (i = 0; i < RTK_TIMEOUT; i++) {
611 DELAY(10);
612 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0)
613 break;
614 }
615 if (i == RTK_TIMEOUT)
616 printf("%s: reset never completed!\n",
617 device_xname(sc->sc_dev));
618 }
619
620 /*
621 * Attach the interface. Allocate softc structures, do ifmedia
622 * setup and ethernet/BPF attach.
623 */
624 void
625 rtk_attach(struct rtk_softc *sc)
626 {
627 device_t self = sc->sc_dev;
628 struct ifnet *ifp;
629 struct rtk_tx_desc *txd;
630 uint16_t val;
631 uint8_t eaddr[ETHER_ADDR_LEN];
632 int error;
633 int i, addr_len;
634
635 callout_init(&sc->rtk_tick_ch, 0);
636
637 /*
638 * Check EEPROM type 9346 or 9356.
639 */
640 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129)
641 addr_len = RTK_EEADDR_LEN1;
642 else
643 addr_len = RTK_EEADDR_LEN0;
644
645 /*
646 * Get station address.
647 */
648 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len);
649 eaddr[0] = val & 0xff;
650 eaddr[1] = val >> 8;
651 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len);
652 eaddr[2] = val & 0xff;
653 eaddr[3] = val >> 8;
654 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len);
655 eaddr[4] = val & 0xff;
656 eaddr[5] = val >> 8;
657
658 if ((error = bus_dmamem_alloc(sc->sc_dmat,
659 RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg,
660 BUS_DMA_NOWAIT)) != 0) {
661 aprint_error_dev(self,
662 "can't allocate recv buffer, error = %d\n", error);
663 goto fail_0;
664 }
665
666 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg,
667 RTK_RXBUFLEN + 16, (void **)&sc->rtk_rx_buf,
668 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
669 aprint_error_dev(self,
670 "can't map recv buffer, error = %d\n", error);
671 goto fail_1;
672 }
673
674 if ((error = bus_dmamap_create(sc->sc_dmat,
675 RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT,
676 &sc->recv_dmamap)) != 0) {
677 aprint_error_dev(self,
678 "can't create recv buffer DMA map, error = %d\n", error);
679 goto fail_2;
680 }
681
682 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap,
683 sc->rtk_rx_buf, RTK_RXBUFLEN + 16,
684 NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) {
685 aprint_error_dev(self,
686 "can't load recv buffer DMA map, error = %d\n", error);
687 goto fail_3;
688 }
689
690 for (i = 0; i < RTK_TX_LIST_CNT; i++) {
691 txd = &sc->rtk_tx_descs[i];
692 if ((error = bus_dmamap_create(sc->sc_dmat,
693 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT,
694 &txd->txd_dmamap)) != 0) {
695 aprint_error_dev(self,
696 "can't create snd buffer DMA map, error = %d\n",
697 error);
698 goto fail_4;
699 }
700 txd->txd_txaddr = RTK_TXADDR0 + (i * 4);
701 txd->txd_txstat = RTK_TXSTAT0 + (i * 4);
702 }
703 SIMPLEQ_INIT(&sc->rtk_tx_free);
704 SIMPLEQ_INIT(&sc->rtk_tx_dirty);
705
706 /*
707 * From this point forward, the attachment cannot fail. A failure
708 * before this releases all resources thar may have been
709 * allocated.
710 */
711 sc->sc_flags |= RTK_ATTACHED;
712
713 /* Reset the adapter. */
714 rtk_reset(sc);
715
716 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr));
717
718 ifp = &sc->ethercom.ec_if;
719 ifp->if_softc = sc;
720 strcpy(ifp->if_xname, device_xname(self));
721 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
722 ifp->if_ioctl = rtk_ioctl;
723 ifp->if_start = rtk_start;
724 ifp->if_watchdog = rtk_watchdog;
725 ifp->if_init = rtk_init;
726 ifp->if_stop = rtk_stop;
727 IFQ_SET_READY(&ifp->if_snd);
728
729 /*
730 * Do ifmedia setup.
731 */
732 sc->mii.mii_ifp = ifp;
733 sc->mii.mii_readreg = rtk_phy_readreg;
734 sc->mii.mii_writereg = rtk_phy_writereg;
735 sc->mii.mii_statchg = rtk_phy_statchg;
736 sc->ethercom.ec_mii = &sc->mii;
737 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange,
738 ether_mediastatus);
739 mii_attach(self, &sc->mii, 0xffffffff,
740 MII_PHY_ANY, MII_OFFSET_ANY, 0);
741
742 /* Choose a default media. */
743 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) {
744 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
745 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE);
746 } else {
747 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO);
748 }
749
750 /*
751 * Call MI attach routines.
752 */
753 if_attach(ifp);
754 ether_ifattach(ifp, eaddr);
755
756 #if NRND > 0
757 rnd_attach_source(&sc->rnd_source, device_xname(self),
758 RND_TYPE_NET, 0);
759 #endif
760
761 return;
762 fail_4:
763 for (i = 0; i < RTK_TX_LIST_CNT; i++) {
764 txd = &sc->rtk_tx_descs[i];
765 if (txd->txd_dmamap != NULL)
766 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap);
767 }
768 fail_3:
769 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap);
770 fail_2:
771 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rtk_rx_buf,
772 RTK_RXBUFLEN + 16);
773 fail_1:
774 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg);
775 fail_0:
776 return;
777 }
778
779 /*
780 * Initialize the transmit descriptors.
781 */
782 STATIC void
783 rtk_list_tx_init(struct rtk_softc *sc)
784 {
785 struct rtk_tx_desc *txd;
786 int i;
787
788 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL)
789 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q);
790 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL)
791 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q);
792
793 for (i = 0; i < RTK_TX_LIST_CNT; i++) {
794 txd = &sc->rtk_tx_descs[i];
795 CSR_WRITE_4(sc, txd->txd_txaddr, 0);
796 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q);
797 }
798 }
799
800 /*
801 * rtk_activate:
802 * Handle device activation/deactivation requests.
803 */
804 int
805 rtk_activate(device_t self, enum devact act)
806 {
807 struct rtk_softc *sc = device_private(self);
808 int s, error;
809
810 error = 0;
811 s = splnet();
812 switch (act) {
813 case DVACT_ACTIVATE:
814 error = EOPNOTSUPP;
815 break;
816 case DVACT_DEACTIVATE:
817 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY);
818 if_deactivate(&sc->ethercom.ec_if);
819 break;
820 }
821 splx(s);
822
823 return error;
824 }
825
826 /*
827 * rtk_detach:
828 * Detach a rtk interface.
829 */
830 int
831 rtk_detach(struct rtk_softc *sc)
832 {
833 struct ifnet *ifp = &sc->ethercom.ec_if;
834 struct rtk_tx_desc *txd;
835 int i;
836
837 /*
838 * Succeed now if there isn't any work to do.
839 */
840 if ((sc->sc_flags & RTK_ATTACHED) == 0)
841 return 0;
842
843 /* Unhook our tick handler. */
844 callout_stop(&sc->rtk_tick_ch);
845
846 /* Detach all PHYs. */
847 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY);
848
849 /* Delete all remaining media. */
850 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY);
851
852 #if NRND > 0
853 rnd_detach_source(&sc->rnd_source);
854 #endif
855
856 ether_ifdetach(ifp);
857 if_detach(ifp);
858
859 for (i = 0; i < RTK_TX_LIST_CNT; i++) {
860 txd = &sc->rtk_tx_descs[i];
861 if (txd->txd_dmamap != NULL)
862 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap);
863 }
864 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap);
865 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->rtk_rx_buf,
866 RTK_RXBUFLEN + 16);
867 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg);
868
869 return 0;
870 }
871
872 /*
873 * rtk_enable:
874 * Enable the RTL81X9 chip.
875 */
876 int
877 rtk_enable(struct rtk_softc *sc)
878 {
879
880 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) {
881 if ((*sc->sc_enable)(sc) != 0) {
882 printf("%s: device enable failed\n",
883 device_xname(sc->sc_dev));
884 return EIO;
885 }
886 sc->sc_flags |= RTK_ENABLED;
887 }
888 return 0;
889 }
890
891 /*
892 * rtk_disable:
893 * Disable the RTL81X9 chip.
894 */
895 void
896 rtk_disable(struct rtk_softc *sc)
897 {
898
899 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) {
900 (*sc->sc_disable)(sc);
901 sc->sc_flags &= ~RTK_ENABLED;
902 }
903 }
904
905 /*
906 * A frame has been uploaded: pass the resulting mbuf chain up to
907 * the higher level protocols.
908 *
909 * You know there's something wrong with a PCI bus-master chip design.
910 *
911 * The receive operation is badly documented in the datasheet, so I'll
912 * attempt to document it here. The driver provides a buffer area and
913 * places its base address in the RX buffer start address register.
914 * The chip then begins copying frames into the RX buffer. Each frame
915 * is preceded by a 32-bit RX status word which specifies the length
916 * of the frame and certain other status bits. Each frame (starting with
917 * the status word) is also 32-bit aligned. The frame length is in the
918 * first 16 bits of the status word; the lower 15 bits correspond with
919 * the 'rx status register' mentioned in the datasheet.
920 *
921 * Note: to make the Alpha happy, the frame payload needs to be aligned
922 * on a 32-bit boundary. To achieve this, we copy the data to mbuf
923 * shifted forward 2 bytes.
924 */
925 STATIC void
926 rtk_rxeof(struct rtk_softc *sc)
927 {
928 struct mbuf *m;
929 struct ifnet *ifp;
930 char *rxbufpos, *dst;
931 u_int total_len, wrap;
932 uint32_t rxstat;
933 uint16_t cur_rx, new_rx;
934 uint16_t limit;
935 uint16_t rx_bytes, max_bytes;
936
937 ifp = &sc->ethercom.ec_if;
938
939 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN;
940
941 /* Do not try to read past this point. */
942 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN;
943
944 if (limit < cur_rx)
945 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit;
946 else
947 max_bytes = limit - cur_rx;
948 rx_bytes = 0;
949
950 while ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) {
951 rxbufpos = (char *)sc->rtk_rx_buf + cur_rx;
952 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx,
953 RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD);
954 rxstat = le32toh(*(uint32_t *)rxbufpos);
955 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx,
956 RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD);
957
958 /*
959 * Here's a totally undocumented fact for you. When the
960 * RealTek chip is in the process of copying a packet into
961 * RAM for you, the length will be 0xfff0. If you spot a
962 * packet header with this value, you need to stop. The
963 * datasheet makes absolutely no mention of this and
964 * RealTek should be shot for this.
965 */
966 total_len = rxstat >> 16;
967 if (total_len == RTK_RXSTAT_UNFINISHED)
968 break;
969
970 if ((rxstat & RTK_RXSTAT_RXOK) == 0 ||
971 total_len < ETHER_MIN_LEN ||
972 total_len > (MCLBYTES - RTK_ETHER_ALIGN)) {
973 ifp->if_ierrors++;
974
975 /*
976 * submitted by:[netbsd-pcmcia:00484]
977 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp>
978 * obtain from:
979 * FreeBSD if_rl.c rev 1.24->1.25
980 *
981 */
982 #if 0
983 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT|
984 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR|
985 RTK_RXSTAT_ALIGNERR)) {
986 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB);
987 CSR_WRITE_2(sc, RTK_COMMAND,
988 RTK_CMD_TX_ENB|RTK_CMD_RX_ENB);
989 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG);
990 CSR_WRITE_4(sc, RTK_RXADDR,
991 sc->recv_dmamap->dm_segs[0].ds_addr);
992 cur_rx = 0;
993 }
994 break;
995 #else
996 rtk_init(ifp);
997 return;
998 #endif
999 }
1000
1001 /* No errors; receive the packet. */
1002 rx_bytes += total_len + RTK_RXSTAT_LEN;
1003
1004 /*
1005 * Avoid trying to read more bytes than we know
1006 * the chip has prepared for us.
1007 */
1008 if (rx_bytes > max_bytes)
1009 break;
1010
1011 /*
1012 * Skip the status word, wrapping around to the beginning
1013 * of the Rx area, if necessary.
1014 */
1015 cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN;
1016 rxbufpos = (char *)sc->rtk_rx_buf + cur_rx;
1017
1018 /*
1019 * Compute the number of bytes at which the packet
1020 * will wrap to the beginning of the ring buffer.
1021 */
1022 wrap = RTK_RXBUFLEN - cur_rx;
1023
1024 /*
1025 * Compute where the next pending packet is.
1026 */
1027 if (total_len > wrap)
1028 new_rx = total_len - wrap;
1029 else
1030 new_rx = cur_rx + total_len;
1031 /* Round up to 32-bit boundary. */
1032 new_rx = ((new_rx + 3) & ~3) % RTK_RXBUFLEN;
1033
1034 /*
1035 * The RealTek chip includes the CRC with every
1036 * incoming packet; trim it off here.
1037 */
1038 total_len -= ETHER_CRC_LEN;
1039
1040 /*
1041 * Now allocate an mbuf (and possibly a cluster) to hold
1042 * the packet. Note we offset the packet 2 bytes so that
1043 * data after the Ethernet header will be 4-byte aligned.
1044 */
1045 MGETHDR(m, M_DONTWAIT, MT_DATA);
1046 if (m == NULL) {
1047 printf("%s: unable to allocate Rx mbuf\n",
1048 device_xname(sc->sc_dev));
1049 ifp->if_ierrors++;
1050 goto next_packet;
1051 }
1052 if (total_len > (MHLEN - RTK_ETHER_ALIGN)) {
1053 MCLGET(m, M_DONTWAIT);
1054 if ((m->m_flags & M_EXT) == 0) {
1055 printf("%s: unable to allocate Rx cluster\n",
1056 device_xname(sc->sc_dev));
1057 ifp->if_ierrors++;
1058 m_freem(m);
1059 m = NULL;
1060 goto next_packet;
1061 }
1062 }
1063 m->m_data += RTK_ETHER_ALIGN; /* for alignment */
1064 m->m_pkthdr.rcvif = ifp;
1065 m->m_pkthdr.len = m->m_len = total_len;
1066 dst = mtod(m, void *);
1067
1068 /*
1069 * If the packet wraps, copy up to the wrapping point.
1070 */
1071 if (total_len > wrap) {
1072 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
1073 cur_rx, wrap, BUS_DMASYNC_POSTREAD);
1074 memcpy(dst, rxbufpos, wrap);
1075 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
1076 cur_rx, wrap, BUS_DMASYNC_PREREAD);
1077 cur_rx = 0;
1078 rxbufpos = sc->rtk_rx_buf;
1079 total_len -= wrap;
1080 dst += wrap;
1081 }
1082
1083 /*
1084 * ...and now the rest.
1085 */
1086 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
1087 cur_rx, total_len, BUS_DMASYNC_POSTREAD);
1088 memcpy(dst, rxbufpos, total_len);
1089 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap,
1090 cur_rx, total_len, BUS_DMASYNC_PREREAD);
1091
1092 next_packet:
1093 CSR_WRITE_2(sc, RTK_CURRXADDR, (new_rx - 16) % RTK_RXBUFLEN);
1094 cur_rx = new_rx;
1095
1096 if (m == NULL)
1097 continue;
1098
1099 ifp->if_ipackets++;
1100
1101 #if NBPFILTER > 0
1102 if (ifp->if_bpf)
1103 bpf_mtap(ifp->if_bpf, m);
1104 #endif
1105 /* pass it on. */
1106 (*ifp->if_input)(ifp, m);
1107 }
1108 }
1109
1110 /*
1111 * A frame was downloaded to the chip. It's safe for us to clean up
1112 * the list buffers.
1113 */
1114 STATIC void
1115 rtk_txeof(struct rtk_softc *sc)
1116 {
1117 struct ifnet *ifp;
1118 struct rtk_tx_desc *txd;
1119 uint32_t txstat;
1120
1121 ifp = &sc->ethercom.ec_if;
1122
1123 /*
1124 * Go through our tx list and free mbufs for those
1125 * frames that have been uploaded.
1126 */
1127 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) {
1128 txstat = CSR_READ_4(sc, txd->txd_txstat);
1129 if ((txstat & (RTK_TXSTAT_TX_OK|
1130 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0)
1131 break;
1132
1133 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q);
1134
1135 bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0,
1136 txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE);
1137 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap);
1138 m_freem(txd->txd_mbuf);
1139 txd->txd_mbuf = NULL;
1140
1141 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24;
1142
1143 if (txstat & RTK_TXSTAT_TX_OK)
1144 ifp->if_opackets++;
1145 else {
1146 ifp->if_oerrors++;
1147
1148 /*
1149 * Increase Early TX threshold if underrun occurred.
1150 * Increase step 64 bytes.
1151 */
1152 if (txstat & RTK_TXSTAT_TX_UNDERRUN) {
1153 #ifdef DEBUG
1154 printf("%s: transmit underrun;",
1155 device_xname(sc->sc_dev));
1156 #endif
1157 if (sc->sc_txthresh < RTK_TXTH_MAX) {
1158 sc->sc_txthresh += 2;
1159 #ifdef DEBUG
1160 printf(" new threshold: %d bytes",
1161 sc->sc_txthresh * 32);
1162 #endif
1163 }
1164 printf("\n");
1165 }
1166 if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN))
1167 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG);
1168 }
1169 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q);
1170 ifp->if_flags &= ~IFF_OACTIVE;
1171 }
1172
1173 /* Clear the timeout timer if there is no pending packet. */
1174 if (SIMPLEQ_EMPTY(&sc->rtk_tx_dirty))
1175 ifp->if_timer = 0;
1176
1177 }
1178
1179 int
1180 rtk_intr(void *arg)
1181 {
1182 struct rtk_softc *sc;
1183 struct ifnet *ifp;
1184 uint16_t status;
1185 int handled;
1186
1187 sc = arg;
1188 ifp = &sc->ethercom.ec_if;
1189
1190 if (!device_has_power(sc->sc_dev))
1191 return 0;
1192
1193 /* Disable interrupts. */
1194 CSR_WRITE_2(sc, RTK_IMR, 0x0000);
1195
1196 handled = 0;
1197 for (;;) {
1198
1199 status = CSR_READ_2(sc, RTK_ISR);
1200
1201 if (status == 0xffff)
1202 break; /* Card is gone... */
1203
1204 if (status)
1205 CSR_WRITE_2(sc, RTK_ISR, status);
1206
1207 if ((status & RTK_INTRS) == 0)
1208 break;
1209
1210 handled = 1;
1211
1212 if (status & RTK_ISR_RX_OK)
1213 rtk_rxeof(sc);
1214
1215 if (status & RTK_ISR_RX_ERR)
1216 rtk_rxeof(sc);
1217
1218 if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR))
1219 rtk_txeof(sc);
1220
1221 if (status & RTK_ISR_SYSTEM_ERR) {
1222 rtk_reset(sc);
1223 rtk_init(ifp);
1224 }
1225 }
1226
1227 /* Re-enable interrupts. */
1228 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
1229
1230 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0)
1231 rtk_start(ifp);
1232
1233 #if NRND > 0
1234 if (RND_ENABLED(&sc->rnd_source))
1235 rnd_add_uint32(&sc->rnd_source, status);
1236 #endif
1237
1238 return handled;
1239 }
1240
1241 /*
1242 * Main transmit routine.
1243 */
1244
1245 STATIC void
1246 rtk_start(struct ifnet *ifp)
1247 {
1248 struct rtk_softc *sc;
1249 struct rtk_tx_desc *txd;
1250 struct mbuf *m_head, *m_new;
1251 int error, len;
1252
1253 sc = ifp->if_softc;
1254
1255 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) {
1256 IFQ_POLL(&ifp->if_snd, m_head);
1257 if (m_head == NULL)
1258 break;
1259 m_new = NULL;
1260
1261 /*
1262 * Load the DMA map. If this fails, the packet didn't
1263 * fit in one DMA segment, and we need to copy. Note,
1264 * the packet must also be aligned.
1265 * if the packet is too small, copy it too, so we're sure
1266 * so have enouth room for the pad buffer.
1267 */
1268 if ((mtod(m_head, uintptr_t) & 3) != 0 ||
1269 m_head->m_pkthdr.len < ETHER_PAD_LEN ||
1270 bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap,
1271 m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) {
1272 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
1273 if (m_new == NULL) {
1274 printf("%s: unable to allocate Tx mbuf\n",
1275 device_xname(sc->sc_dev));
1276 break;
1277 }
1278 if (m_head->m_pkthdr.len > MHLEN) {
1279 MCLGET(m_new, M_DONTWAIT);
1280 if ((m_new->m_flags & M_EXT) == 0) {
1281 printf("%s: unable to allocate Tx "
1282 "cluster\n",
1283 device_xname(sc->sc_dev));
1284 m_freem(m_new);
1285 break;
1286 }
1287 }
1288 m_copydata(m_head, 0, m_head->m_pkthdr.len,
1289 mtod(m_new, void *));
1290 m_new->m_pkthdr.len = m_new->m_len =
1291 m_head->m_pkthdr.len;
1292 if (m_head->m_pkthdr.len < ETHER_PAD_LEN) {
1293 memset(
1294 mtod(m_new, char *) + m_head->m_pkthdr.len,
1295 0, ETHER_PAD_LEN - m_head->m_pkthdr.len);
1296 m_new->m_pkthdr.len = m_new->m_len =
1297 ETHER_PAD_LEN;
1298 }
1299 error = bus_dmamap_load_mbuf(sc->sc_dmat,
1300 txd->txd_dmamap, m_new,
1301 BUS_DMA_WRITE|BUS_DMA_NOWAIT);
1302 if (error) {
1303 printf("%s: unable to load Tx buffer, "
1304 "error = %d\n",
1305 device_xname(sc->sc_dev), error);
1306 break;
1307 }
1308 }
1309 IFQ_DEQUEUE(&ifp->if_snd, m_head);
1310 #if NBPFILTER > 0
1311 /*
1312 * If there's a BPF listener, bounce a copy of this frame
1313 * to him.
1314 */
1315 if (ifp->if_bpf)
1316 bpf_mtap(ifp->if_bpf, m_head);
1317 #endif
1318 if (m_new != NULL) {
1319 m_freem(m_head);
1320 m_head = m_new;
1321 }
1322 txd->txd_mbuf = m_head;
1323
1324 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q);
1325 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q);
1326
1327 /*
1328 * Transmit the frame.
1329 */
1330 bus_dmamap_sync(sc->sc_dmat,
1331 txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize,
1332 BUS_DMASYNC_PREWRITE);
1333
1334 len = txd->txd_dmamap->dm_segs[0].ds_len;
1335
1336 CSR_WRITE_4(sc, txd->txd_txaddr,
1337 txd->txd_dmamap->dm_segs[0].ds_addr);
1338 CSR_WRITE_4(sc, txd->txd_txstat,
1339 RTK_TXSTAT_THRESH(sc->sc_txthresh) | len);
1340
1341 /*
1342 * Set a timeout in case the chip goes out to lunch.
1343 */
1344 ifp->if_timer = 5;
1345 }
1346
1347 /*
1348 * We broke out of the loop because all our TX slots are
1349 * full. Mark the NIC as busy until it drains some of the
1350 * packets from the queue.
1351 */
1352 if (SIMPLEQ_EMPTY(&sc->rtk_tx_free))
1353 ifp->if_flags |= IFF_OACTIVE;
1354 }
1355
1356 STATIC int
1357 rtk_init(struct ifnet *ifp)
1358 {
1359 struct rtk_softc *sc = ifp->if_softc;
1360 int error, i;
1361 uint32_t rxcfg;
1362
1363 if ((error = rtk_enable(sc)) != 0)
1364 goto out;
1365
1366 /*
1367 * Cancel pending I/O.
1368 */
1369 rtk_stop(ifp, 0);
1370
1371 /* Init our MAC address */
1372 for (i = 0; i < ETHER_ADDR_LEN; i++) {
1373 CSR_WRITE_1(sc, RTK_IDR0 + i, CLLADDR(ifp->if_sadl)[i]);
1374 }
1375
1376 /* Init the RX buffer pointer register. */
1377 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0,
1378 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1379 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr);
1380
1381 /* Init TX descriptors. */
1382 rtk_list_tx_init(sc);
1383
1384 /* Init Early TX threshold. */
1385 sc->sc_txthresh = RTK_TXTH_256;
1386 /*
1387 * Enable transmit and receive.
1388 */
1389 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB);
1390
1391 /*
1392 * Set the initial TX and RX configuration.
1393 */
1394 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG);
1395 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG);
1396
1397 /* Set the individual bit to receive frames for this host only. */
1398 rxcfg = CSR_READ_4(sc, RTK_RXCFG);
1399 rxcfg |= RTK_RXCFG_RX_INDIV;
1400
1401 /* If we want promiscuous mode, set the allframes bit. */
1402 if (ifp->if_flags & IFF_PROMISC) {
1403 rxcfg |= RTK_RXCFG_RX_ALLPHYS;
1404 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1405 } else {
1406 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS;
1407 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1408 }
1409
1410 /*
1411 * Set capture broadcast bit to capture broadcast frames.
1412 */
1413 if (ifp->if_flags & IFF_BROADCAST) {
1414 rxcfg |= RTK_RXCFG_RX_BROAD;
1415 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1416 } else {
1417 rxcfg &= ~RTK_RXCFG_RX_BROAD;
1418 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg);
1419 }
1420
1421 /*
1422 * Program the multicast filter, if necessary.
1423 */
1424 rtk_setmulti(sc);
1425
1426 /*
1427 * Enable interrupts.
1428 */
1429 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS);
1430
1431 /* Start RX/TX process. */
1432 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0);
1433
1434 /* Enable receiver and transmitter. */
1435 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB);
1436
1437 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX);
1438
1439 /*
1440 * Set current media.
1441 */
1442 if ((error = ether_mediachange(ifp)) != 0)
1443 goto out;
1444
1445 ifp->if_flags |= IFF_RUNNING;
1446 ifp->if_flags &= ~IFF_OACTIVE;
1447
1448 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc);
1449
1450 out:
1451 if (error) {
1452 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1453 ifp->if_timer = 0;
1454 printf("%s: interface not running\n", device_xname(sc->sc_dev));
1455 }
1456 return error;
1457 }
1458
1459 STATIC int
1460 rtk_ioctl(struct ifnet *ifp, u_long command, void *data)
1461 {
1462 struct rtk_softc *sc = ifp->if_softc;
1463 int s, error;
1464
1465 s = splnet();
1466 error = ether_ioctl(ifp, command, data);
1467 if (error == ENETRESET) {
1468 if (ifp->if_flags & IFF_RUNNING) {
1469 /*
1470 * Multicast list has changed. Set the
1471 * hardware filter accordingly.
1472 */
1473 rtk_setmulti(sc);
1474 }
1475 error = 0;
1476 }
1477 splx(s);
1478
1479 return error;
1480 }
1481
1482 STATIC void
1483 rtk_watchdog(struct ifnet *ifp)
1484 {
1485 struct rtk_softc *sc;
1486
1487 sc = ifp->if_softc;
1488
1489 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev));
1490 ifp->if_oerrors++;
1491 rtk_txeof(sc);
1492 rtk_rxeof(sc);
1493 rtk_init(ifp);
1494 }
1495
1496 /*
1497 * Stop the adapter and free any mbufs allocated to the
1498 * RX and TX lists.
1499 */
1500 STATIC void
1501 rtk_stop(struct ifnet *ifp, int disable)
1502 {
1503 struct rtk_softc *sc = ifp->if_softc;
1504 struct rtk_tx_desc *txd;
1505
1506 callout_stop(&sc->rtk_tick_ch);
1507
1508 mii_down(&sc->mii);
1509
1510 CSR_WRITE_1(sc, RTK_COMMAND, 0x00);
1511 CSR_WRITE_2(sc, RTK_IMR, 0x0000);
1512
1513 /*
1514 * Free the TX list buffers.
1515 */
1516 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) {
1517 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q);
1518 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap);
1519 m_freem(txd->txd_mbuf);
1520 txd->txd_mbuf = NULL;
1521 CSR_WRITE_4(sc, txd->txd_txaddr, 0);
1522 }
1523
1524 if (disable)
1525 rtk_disable(sc);
1526
1527 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1528 ifp->if_timer = 0;
1529 }
1530
1531 STATIC void
1532 rtk_tick(void *arg)
1533 {
1534 struct rtk_softc *sc = arg;
1535 int s;
1536
1537 s = splnet();
1538 mii_tick(&sc->mii);
1539 splx(s);
1540
1541 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc);
1542 }
Cache object: 8bf7ed5f106d1fed8728647cc8e981ab
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