Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/rtwphy.c
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1 /* $NetBSD: rtwphy.c,v 1.5 2005/02/27 00:27:02 perry Exp $ */ 2 /*- 3 * Copyright (c) 2004, 2005 David Young. All rights reserved. 4 * 5 * Programmed for NetBSD by David Young. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of David Young may not be used to endorse or promote 16 * products derived from this software without specific prior 17 * written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 20 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 22 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 23 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 25 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 27 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 28 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 30 * OF SUCH DAMAGE. 31 */ 32 /* 33 * Control the Philips SA2400 RF front-end and the baseband processor 34 * built into the Realtek RTL8180. 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: rtwphy.c,v 1.5 2005/02/27 00:27:02 perry Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/types.h> 43 44 #include <machine/bus.h> 45 46 #include <net/if.h> 47 #include <net/if_media.h> 48 #include <net/if_ether.h> 49 50 #include <net80211/ieee80211_var.h> 51 #include <net80211/ieee80211_compat.h> 52 #include <net80211/ieee80211_radiotap.h> 53 54 #include <dev/ic/rtwreg.h> 55 #include <dev/ic/max2820reg.h> 56 #include <dev/ic/sa2400reg.h> 57 #include <dev/ic/rtwvar.h> 58 #include <dev/ic/rtwphyio.h> 59 #include <dev/ic/rtwphy.h> 60 61 static int rtw_max2820_pwrstate(struct rtw_rf *, enum rtw_pwrstate); 62 static int rtw_sa2400_pwrstate(struct rtw_rf *, enum rtw_pwrstate); 63 64 static int 65 rtw_bbp_preinit(struct rtw_regs *regs, u_int antatten0, int dflantb, 66 u_int freq) 67 { 68 u_int antatten = antatten0; 69 if (dflantb) 70 antatten |= RTW_BBP_ANTATTEN_DFLANTB; 71 if (freq == 2484) /* channel 14 */ 72 antatten |= RTW_BBP_ANTATTEN_CHAN14; 73 return rtw_bbp_write(regs, RTW_BBP_ANTATTEN, antatten); 74 } 75 76 static int 77 rtw_bbp_init(struct rtw_regs *regs, struct rtw_bbpset *bb, int antdiv, 78 int dflantb, uint8_t cs_threshold, u_int freq) 79 { 80 int rc; 81 uint32_t sys2, sys3; 82 83 sys2 = bb->bb_sys2; 84 if (antdiv) 85 sys2 |= RTW_BBP_SYS2_ANTDIV; 86 sys3 = bb->bb_sys3 | 87 LSHIFT(cs_threshold, RTW_BBP_SYS3_CSTHRESH_MASK); 88 89 #define RTW_BBP_WRITE_OR_RETURN(reg, val) \ 90 if ((rc = rtw_bbp_write(regs, reg, val)) != 0) \ 91 return rc; 92 93 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS1, bb->bb_sys1); 94 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TXAGC, bb->bb_txagc); 95 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_LNADET, bb->bb_lnadet); 96 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCINI, bb->bb_ifagcini); 97 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCLIMIT, bb->bb_ifagclimit); 98 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_IFAGCDET, bb->bb_ifagcdet); 99 100 if ((rc = rtw_bbp_preinit(regs, bb->bb_antatten, dflantb, freq)) != 0) 101 return rc; 102 103 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_TRL, bb->bb_trl); 104 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS2, sys2); 105 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_SYS3, sys3); 106 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHESTLIM, bb->bb_chestlim); 107 RTW_BBP_WRITE_OR_RETURN(RTW_BBP_CHSQLIM, bb->bb_chsqlim); 108 return 0; 109 } 110 111 static int 112 rtw_sa2400_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) 113 { 114 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 115 struct rtw_rfbus *bus = &sa->sa_bus; 116 117 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_TX, 118 opaque_txpower); 119 } 120 121 /* make sure we're using the same settings as the reference driver */ 122 static void 123 verify_syna(u_int freq, uint32_t val) 124 { 125 uint32_t expected_val = ~val; 126 127 switch (freq) { 128 case 2412: 129 expected_val = 0x0000096c; /* ch 1 */ 130 break; 131 case 2417: 132 expected_val = 0x00080970; /* ch 2 */ 133 break; 134 case 2422: 135 expected_val = 0x00100974; /* ch 3 */ 136 break; 137 case 2427: 138 expected_val = 0x00180978; /* ch 4 */ 139 break; 140 case 2432: 141 expected_val = 0x00000980; /* ch 5 */ 142 break; 143 case 2437: 144 expected_val = 0x00080984; /* ch 6 */ 145 break; 146 case 2442: 147 expected_val = 0x00100988; /* ch 7 */ 148 break; 149 case 2447: 150 expected_val = 0x0018098c; /* ch 8 */ 151 break; 152 case 2452: 153 expected_val = 0x00000994; /* ch 9 */ 154 break; 155 case 2457: 156 expected_val = 0x00080998; /* ch 10 */ 157 break; 158 case 2462: 159 expected_val = 0x0010099c; /* ch 11 */ 160 break; 161 case 2467: 162 expected_val = 0x001809a0; /* ch 12 */ 163 break; 164 case 2472: 165 expected_val = 0x000009a8; /* ch 13 */ 166 break; 167 case 2484: 168 expected_val = 0x000009b4; /* ch 14 */ 169 break; 170 } 171 KASSERT(val == expected_val); 172 } 173 174 /* freq is in MHz */ 175 static int 176 rtw_sa2400_tune(struct rtw_rf *rf, u_int freq) 177 { 178 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 179 struct rtw_rfbus *bus = &sa->sa_bus; 180 int rc; 181 uint32_t syna, synb, sync; 182 183 /* XO = 44MHz, R = 11, hence N is in units of XO / R = 4MHz. 184 * 185 * The channel spacing (5MHz) is not divisible by 4MHz, so 186 * we set the fractional part of N to compensate. 187 */ 188 int n = freq / 4, nf = (freq % 4) * 2; 189 190 syna = LSHIFT(nf, SA2400_SYNA_NF_MASK) | LSHIFT(n, SA2400_SYNA_N_MASK); 191 verify_syna(freq, syna); 192 193 /* Divide the 44MHz crystal down to 4MHz. Set the fractional 194 * compensation charge pump value to agree with the fractional 195 * modulus. 196 */ 197 synb = LSHIFT(11, SA2400_SYNB_R_MASK) | SA2400_SYNB_L_NORMAL | 198 SA2400_SYNB_ON | SA2400_SYNB_ONE | 199 LSHIFT(80, SA2400_SYNB_FC_MASK); /* agrees w/ SA2400_SYNA_FM = 0 */ 200 201 sync = SA2400_SYNC_CP_NORMAL; 202 203 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNA, 204 syna)) != 0) 205 return rc; 206 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNB, 207 synb)) != 0) 208 return rc; 209 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYNC, 210 sync)) != 0) 211 return rc; 212 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_SYND, 0x0); 213 } 214 215 static int 216 rtw_sa2400_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 217 { 218 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 219 struct rtw_rfbus *bus = &sa->sa_bus; 220 uint32_t opmode; 221 opmode = SA2400_OPMODE_DEFAULTS; 222 switch (power) { 223 case RTW_ON: 224 opmode |= SA2400_OPMODE_MODE_TXRX; 225 break; 226 case RTW_SLEEP: 227 opmode |= SA2400_OPMODE_MODE_WAIT; 228 break; 229 case RTW_OFF: 230 opmode |= SA2400_OPMODE_MODE_SLEEP; 231 break; 232 } 233 234 if (sa->sa_digphy) 235 opmode |= SA2400_OPMODE_DIGIN; 236 237 return rtw_rfbus_write(bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 238 opmode); 239 } 240 241 static int 242 rtw_sa2400_manrx_init(struct rtw_sa2400 *sa) 243 { 244 uint32_t manrx; 245 246 /* XXX we are not supposed to be in RXMGC mode when we do 247 * this? 248 */ 249 manrx = SA2400_MANRX_AHSN; 250 manrx |= SA2400_MANRX_TEN; 251 manrx |= LSHIFT(1023, SA2400_MANRX_RXGAIN_MASK); 252 253 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_MANRX, 254 manrx); 255 } 256 257 static int 258 rtw_sa2400_vcocal_start(struct rtw_sa2400 *sa, int start) 259 { 260 uint32_t opmode; 261 262 opmode = SA2400_OPMODE_DEFAULTS; 263 if (start) 264 opmode |= SA2400_OPMODE_MODE_VCOCALIB; 265 else 266 opmode |= SA2400_OPMODE_MODE_SLEEP; 267 268 if (sa->sa_digphy) 269 opmode |= SA2400_OPMODE_DIGIN; 270 271 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 272 opmode); 273 } 274 275 static int 276 rtw_sa2400_vco_calibration(struct rtw_sa2400 *sa) 277 { 278 int rc; 279 /* calibrate VCO */ 280 if ((rc = rtw_sa2400_vcocal_start(sa, 1)) != 0) 281 return rc; 282 DELAY(2200); /* 2.2 milliseconds */ 283 /* XXX superfluous: SA2400 automatically entered SLEEP mode. */ 284 return rtw_sa2400_vcocal_start(sa, 0); 285 } 286 287 static int 288 rtw_sa2400_filter_calibration(struct rtw_sa2400 *sa) 289 { 290 uint32_t opmode; 291 292 opmode = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_FCALIB; 293 if (sa->sa_digphy) 294 opmode |= SA2400_OPMODE_DIGIN; 295 296 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 297 opmode); 298 } 299 300 static int 301 rtw_sa2400_dc_calibration(struct rtw_sa2400 *sa) 302 { 303 struct rtw_rf *rf = &sa->sa_rf; 304 int rc; 305 uint32_t dccal; 306 307 (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 1); 308 309 dccal = SA2400_OPMODE_DEFAULTS | SA2400_OPMODE_MODE_TXRX; 310 311 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 312 dccal); 313 if (rc != 0) 314 return rc; 315 316 DELAY(5); /* DCALIB after being in Tx mode for 5 317 * microseconds 318 */ 319 320 dccal &= ~SA2400_OPMODE_MODE_MASK; 321 dccal |= SA2400_OPMODE_MODE_DCALIB; 322 323 rc = rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_OPMODE, 324 dccal); 325 if (rc != 0) 326 return rc; 327 328 DELAY(20); /* calibration takes at most 20 microseconds */ 329 330 (*rf->rf_continuous_tx_cb)(rf->rf_continuous_tx_arg, 0); 331 332 return 0; 333 } 334 335 static int 336 rtw_sa2400_agc_init(struct rtw_sa2400 *sa) 337 { 338 uint32_t agc; 339 340 agc = LSHIFT(25, SA2400_AGC_MAXGAIN_MASK); 341 agc |= LSHIFT(7, SA2400_AGC_BBPDELAY_MASK); 342 agc |= LSHIFT(15, SA2400_AGC_LNADELAY_MASK); 343 agc |= LSHIFT(27, SA2400_AGC_RXONDELAY_MASK); 344 345 return rtw_rfbus_write(&sa->sa_bus, RTW_RFCHIPID_PHILIPS, SA2400_AGC, 346 agc); 347 } 348 349 static void 350 rtw_sa2400_destroy(struct rtw_rf *rf) 351 { 352 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 353 memset(sa, 0, sizeof(*sa)); 354 free(sa, M_DEVBUF); 355 } 356 357 static int 358 rtw_sa2400_calibrate(struct rtw_rf *rf, u_int freq) 359 { 360 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 361 int i, rc; 362 363 /* XXX reference driver calibrates VCO twice. Is it a bug? */ 364 for (i = 0; i < 2; i++) { 365 if ((rc = rtw_sa2400_vco_calibration(sa)) != 0) 366 return rc; 367 } 368 /* VCO calibration erases synthesizer registers, so re-tune */ 369 if ((rc = rtw_sa2400_tune(rf, freq)) != 0) 370 return rc; 371 if ((rc = rtw_sa2400_filter_calibration(sa)) != 0) 372 return rc; 373 /* analog PHY needs DC calibration */ 374 if (!sa->sa_digphy) 375 return rtw_sa2400_dc_calibration(sa); 376 return 0; 377 } 378 379 static int 380 rtw_sa2400_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, 381 enum rtw_pwrstate power) 382 { 383 struct rtw_sa2400 *sa = (struct rtw_sa2400 *)rf; 384 int rc; 385 386 if ((rc = rtw_sa2400_txpower(rf, opaque_txpower)) != 0) 387 return rc; 388 389 /* skip configuration if it's time to sleep or to power-down. */ 390 if (power == RTW_SLEEP || power == RTW_OFF) 391 return rtw_sa2400_pwrstate(rf, power); 392 393 /* go to sleep for configuration */ 394 if ((rc = rtw_sa2400_pwrstate(rf, RTW_SLEEP)) != 0) 395 return rc; 396 397 if ((rc = rtw_sa2400_tune(rf, freq)) != 0) 398 return rc; 399 if ((rc = rtw_sa2400_agc_init(sa)) != 0) 400 return rc; 401 if ((rc = rtw_sa2400_manrx_init(sa)) != 0) 402 return rc; 403 if ((rc = rtw_sa2400_calibrate(rf, freq)) != 0) 404 return rc; 405 406 /* enter Tx/Rx mode */ 407 return rtw_sa2400_pwrstate(rf, power); 408 } 409 410 struct rtw_rf * 411 rtw_sa2400_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int digphy) 412 { 413 struct rtw_sa2400 *sa; 414 struct rtw_rfbus *bus; 415 struct rtw_rf *rf; 416 struct rtw_bbpset *bb; 417 418 sa = malloc(sizeof(*sa), M_DEVBUF, M_NOWAIT | M_ZERO); 419 if (sa == NULL) 420 return NULL; 421 422 sa->sa_digphy = digphy; 423 424 rf = &sa->sa_rf; 425 bus = &sa->sa_bus; 426 427 rf->rf_init = rtw_sa2400_init; 428 rf->rf_destroy = rtw_sa2400_destroy; 429 rf->rf_txpower = rtw_sa2400_txpower; 430 rf->rf_tune = rtw_sa2400_tune; 431 rf->rf_pwrstate = rtw_sa2400_pwrstate; 432 bb = &rf->rf_bbpset; 433 434 /* XXX magic */ 435 bb->bb_antatten = RTW_BBP_ANTATTEN_PHILIPS_MAGIC; 436 bb->bb_chestlim = 0x00; 437 bb->bb_chsqlim = 0xa0; 438 bb->bb_ifagcdet = 0x64; 439 bb->bb_ifagcini = 0x90; 440 bb->bb_ifagclimit = 0x1a; 441 bb->bb_lnadet = 0xe0; 442 bb->bb_sys1 = 0x98; 443 bb->bb_sys2 = 0x47; 444 bb->bb_sys3 = 0x90; 445 bb->bb_trl = 0x88; 446 bb->bb_txagc = 0x38; 447 448 bus->b_regs = regs; 449 bus->b_write = rf_write; 450 451 return &sa->sa_rf; 452 } 453 454 /* freq is in MHz */ 455 static int 456 rtw_max2820_tune(struct rtw_rf *rf, u_int freq) 457 { 458 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 459 struct rtw_rfbus *bus = &mx->mx_bus; 460 461 if (freq < 2400 || freq > 2499) 462 return -1; 463 464 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_CHANNEL, 465 LSHIFT(freq - 2400, MAX2820_CHANNEL_CF_MASK)); 466 } 467 468 static void 469 rtw_max2820_destroy(struct rtw_rf *rf) 470 { 471 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 472 memset(mx, 0, sizeof(*mx)); 473 free(mx, M_DEVBUF); 474 } 475 476 static int 477 rtw_max2820_init(struct rtw_rf *rf, u_int freq, uint8_t opaque_txpower, 478 enum rtw_pwrstate power) 479 { 480 struct rtw_max2820 *mx = (struct rtw_max2820 *)rf; 481 struct rtw_rfbus *bus = &mx->mx_bus; 482 int rc; 483 484 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TEST, 485 MAX2820_TEST_DEFAULT)) != 0) 486 return rc; 487 488 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, 489 MAX2820_ENABLE_DEFAULT)) != 0) 490 return rc; 491 492 /* skip configuration if it's time to sleep or to power-down. */ 493 if ((rc = rtw_max2820_pwrstate(rf, power)) != 0) 494 return rc; 495 else if (power == RTW_OFF || power == RTW_SLEEP) 496 return 0; 497 498 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_SYNTH, 499 MAX2820_SYNTH_R_44MHZ)) != 0) 500 return rc; 501 502 if ((rc = rtw_max2820_tune(rf, freq)) != 0) 503 return rc; 504 505 /* XXX The MAX2820 datasheet indicates that 1C and 2C should not 506 * be changed from 7, however, the reference driver sets them 507 * to 4 and 1, respectively. 508 */ 509 if ((rc = rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_RECEIVE, 510 MAX2820_RECEIVE_DL_DEFAULT | 511 LSHIFT(4, MAX2820A_RECEIVE_1C_MASK) | 512 LSHIFT(1, MAX2820A_RECEIVE_2C_MASK))) != 0) 513 return rc; 514 515 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_TRANSMIT, 516 MAX2820_TRANSMIT_PA_DEFAULT); 517 } 518 519 static int 520 rtw_max2820_txpower(struct rtw_rf *rf, uint8_t opaque_txpower) 521 { 522 /* TBD */ 523 return 0; 524 } 525 526 static int 527 rtw_max2820_pwrstate(struct rtw_rf *rf, enum rtw_pwrstate power) 528 { 529 uint32_t enable; 530 struct rtw_max2820 *mx; 531 struct rtw_rfbus *bus; 532 533 mx = (struct rtw_max2820 *)rf; 534 bus = &mx->mx_bus; 535 536 switch (power) { 537 case RTW_OFF: 538 case RTW_SLEEP: 539 default: 540 enable = 0x0; 541 break; 542 case RTW_ON: 543 enable = MAX2820_ENABLE_DEFAULT; 544 break; 545 } 546 return rtw_rfbus_write(bus, RTW_RFCHIPID_MAXIM, MAX2820_ENABLE, enable); 547 } 548 549 struct rtw_rf * 550 rtw_max2820_create(struct rtw_regs *regs, rtw_rf_write_t rf_write, int is_a) 551 { 552 struct rtw_max2820 *mx; 553 struct rtw_rfbus *bus; 554 struct rtw_rf *rf; 555 struct rtw_bbpset *bb; 556 557 mx = malloc(sizeof(*mx), M_DEVBUF, M_NOWAIT | M_ZERO); 558 if (mx == NULL) 559 return NULL; 560 561 mx->mx_is_a = is_a; 562 563 rf = &mx->mx_rf; 564 bus = &mx->mx_bus; 565 566 rf->rf_init = rtw_max2820_init; 567 rf->rf_destroy = rtw_max2820_destroy; 568 rf->rf_txpower = rtw_max2820_txpower; 569 rf->rf_tune = rtw_max2820_tune; 570 rf->rf_pwrstate = rtw_max2820_pwrstate; 571 bb = &rf->rf_bbpset; 572 573 /* XXX magic */ 574 bb->bb_antatten = RTW_BBP_ANTATTEN_MAXIM_MAGIC; 575 bb->bb_chestlim = 0; 576 bb->bb_chsqlim = 159; 577 bb->bb_ifagcdet = 100; 578 bb->bb_ifagcini = 144; 579 bb->bb_ifagclimit = 26; 580 bb->bb_lnadet = 248; 581 bb->bb_sys1 = 136; 582 bb->bb_sys2 = 71; 583 bb->bb_sys3 = 155; 584 bb->bb_trl = 136; 585 bb->bb_txagc = 8; 586 587 bus->b_regs = regs; 588 bus->b_write = rf_write; 589 590 return &mx->mx_rf; 591 } 592 593 /* freq is in MHz */ 594 int 595 rtw_phy_init(struct rtw_regs *regs, struct rtw_rf *rf, uint8_t opaque_txpower, 596 uint8_t cs_threshold, u_int freq, int antdiv, int dflantb, 597 enum rtw_pwrstate power) 598 { 599 int rc; 600 RTW_DPRINTF(RTW_DEBUG_PHY, 601 ("%s: txpower %u csthresh %u freq %u antdiv %u dflantb %u " 602 "pwrstate %s\n", __func__, opaque_txpower, cs_threshold, freq, 603 antdiv, dflantb, rtw_pwrstate_string(power))); 604 605 /* XXX is this really necessary? */ 606 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) 607 return rc; 608 if ((rc = rtw_bbp_preinit(regs, rf->rf_bbpset.bb_antatten, dflantb, 609 freq)) != 0) 610 return rc; 611 if ((rc = rtw_rf_tune(rf, freq)) != 0) 612 return rc; 613 /* initialize RF */ 614 if ((rc = rtw_rf_init(rf, freq, opaque_txpower, power)) != 0) 615 return rc; 616 #if 0 /* what is this redundant tx power setting here for? */ 617 if ((rc = rtw_rf_txpower(rf, opaque_txpower)) != 0) 618 return rc; 619 #endif 620 return rtw_bbp_init(regs, &rf->rf_bbpset, antdiv, dflantb, 621 cs_threshold, freq); 622 }
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