The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/rtwreg.h

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    1 /*      $NetBSD: rtwreg.h,v 1.13 2005/02/27 00:27:02 perry Exp $        */
    2 /*-
    3  * Copyright (c) 2004, 2005 David Young.  All rights reserved.
    4  *
    5  * Programmed for NetBSD by David Young.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. The name of David Young may not be used to endorse or promote
   16  *    products derived from this software without specific prior
   17  *    written permission.
   18  *
   19  * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
   20  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
   21  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
   22  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
   23  * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
   24  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
   25  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
   27  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   28  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
   30  * OF SUCH DAMAGE.
   31  */
   32 /* Macros for bit twiddling. */
   33 /* TBD factor w/ dev/ic/atwreg.h. */
   34 
   35 #ifndef _BIT_TWIDDLE
   36 #define _BIT_TWIDDLE
   37 /* nth bit, BIT(0) == 0x1. */
   38 #define BIT(n) (((n) == 32) ? 0 : ((uint32_t)1 << (n)))
   39 
   40 /* bits m through n, m < n. */
   41 #define BITS(m, n) ((BIT(MAX((m), (n)) + 1) - 1) ^ (BIT(MIN((m), (n))) - 1))
   42 
   43 /* find least significant bit that is set */
   44 #define LOWEST_SET_BIT(x) ((((x) - 1) & (x)) ^ (x))
   45 
   46 /* for x a power of two and p a non-negative integer, is x a greater
   47  * power than 2**p?
   48  */
   49 #define GTEQ_POWER(x, p) (((u_long)(x) >> (p)) != 0)
   50 
   51 #define MASK_TO_SHIFT2(m) (GTEQ_POWER(LOWEST_SET_BIT((m)), 1) ? 1 : 0)
   52 
   53 #define MASK_TO_SHIFT4(m) \
   54         (GTEQ_POWER(LOWEST_SET_BIT((m)), 2) \
   55             ? 2 + MASK_TO_SHIFT2((m) >> 2) \
   56             : MASK_TO_SHIFT2((m)))
   57 
   58 #define MASK_TO_SHIFT8(m) \
   59         (GTEQ_POWER(LOWEST_SET_BIT((m)), 4) \
   60             ? 4 + MASK_TO_SHIFT4((m) >> 4) \
   61             : MASK_TO_SHIFT4((m)))
   62 
   63 #define MASK_TO_SHIFT16(m) \
   64         (GTEQ_POWER(LOWEST_SET_BIT((m)), 8) \
   65             ? 8 + MASK_TO_SHIFT8((m) >> 8) \
   66             : MASK_TO_SHIFT8((m)))
   67 
   68 #define MASK_TO_SHIFT(m) \
   69         (GTEQ_POWER(LOWEST_SET_BIT((m)), 16) \
   70             ? 16 + MASK_TO_SHIFT16((m) >> 16) \
   71             : MASK_TO_SHIFT16((m)))
   72 
   73 #define MASK_AND_RSHIFT(x, mask) (((x) & (mask)) >> MASK_TO_SHIFT(mask))
   74 #define LSHIFT(x, mask) ((x) << MASK_TO_SHIFT(mask))
   75 #define MASK_AND_REPLACE(reg, val, mask) ((reg & ~mask) | LSHIFT(val, mask))
   76 #define PRESHIFT(m) MASK_AND_RSHIFT((m), (m))
   77 
   78 #endif /* _BIT_TWIDDLE */
   79 
   80 /* RTL8180L Host Control and Status Registers */
   81 
   82 #define RTW_IDR0        0x00    /* ID Register: MAC addr, 6 bytes.
   83                                  * Auto-loaded from EEPROM. Read by byte,
   84                                  * by word, or by double word, but write
   85                                  * only by double word.
   86                                  */
   87 #define RTW_IDR1        0x04
   88 
   89 #define RTW_MAR0        0x08    /* Multicast filter, 64b. */
   90 #define RTW_MAR1        0x0c
   91 
   92 #define RTW_TSFTRL      0x18    /* Timing Synchronization Function Timer
   93                                  * Register, low word, 32b, read-only.
   94                                  */
   95 #define RTW_TSFTRH      0x1c    /* High word, 32b, read-only. */
   96 #define RTW_TLPDA       0x20    /* Transmit Low Priority Descriptors Start
   97                                  * Address, 32b, 256-byte alignment.
   98                                  */
   99 #define RTW_TNPDA       0x24    /* Transmit Normal Priority Descriptors Start
  100                                  * Address, 32b, 256-byte alignment.
  101                                  */
  102 #define RTW_THPDA       0x28    /* Transmit High Priority Descriptors Start
  103                                  * Address, 32b, 256-byte alignment.
  104                                  */
  105 
  106 #define RTW_BRSR        0x2c    /* Basic Rate Set Register, 16b */
  107 #define RTW_BRSR_BPLCP  BIT(8)  /* 1: use short PLCP header for CTS/ACK packet,
  108                                  * 0: use long PLCP header
  109                                  */
  110 #define RTW_BRSR_MBR8180_MASK   BITS(1,0)       /* Maximum Basic Service Rate */
  111 #define RTW_BRSR_MBR8180_1MBPS  LSHIFT(0, RTW_BRSR_MBR8180_MASK)
  112 #define RTW_BRSR_MBR8180_2MBPS  LSHIFT(1, RTW_BRSR_MBR8180_MASK)
  113 #define RTW_BRSR_MBR8180_5MBPS  LSHIFT(2, RTW_BRSR_MBR8180_MASK)
  114 #define RTW_BRSR_MBR8180_11MBPS LSHIFT(3, RTW_BRSR_MBR8180_MASK)
  115 
  116 /* 8181 and 8180 docs conflict! */
  117 #define RTW_BRSR_MBR8181_1MBPS  BIT(0)
  118 #define RTW_BRSR_MBR8181_2MBPS  BIT(1)
  119 #define RTW_BRSR_MBR8181_5MBPS  BIT(2)
  120 #define RTW_BRSR_MBR8181_11MBPS BIT(3)
  121 
  122 #define RTW_BSSID       0x2e
  123 /* BSSID, 6 bytes */
  124 #define RTW_BSSID16     0x2e            /* first two bytes */
  125 #define RTW_BSSID32     (0x2e + 4)      /* remaining four bytes */
  126 #define RTW_BSSID0      RTW_BSSID16             /* BSSID[0], 8b */
  127 #define RTW_BSSID1      (RTW_BSSID0 + 1)        /* BSSID[1], 8b */
  128 #define RTW_BSSID2      (RTW_BSSID1 + 1)        /* BSSID[2], 8b */
  129 #define RTW_BSSID3      (RTW_BSSID2 + 1)        /* BSSID[3], 8b */
  130 #define RTW_BSSID4      (RTW_BSSID3 + 1)        /* BSSID[4], 8b */
  131 #define RTW_BSSID5      (RTW_BSSID4 + 1)        /* BSSID[5], 8b */
  132 
  133 #define RTW_CR          0x37    /* Command Register, 8b */
  134 #define RTW_CR_RST      BIT(4)  /* Reset: host sets to 1 to disable
  135                                  * transmitter & receiver, reinitialize FIFO.
  136                                  * RTL8180L sets to 0 to signal completion.
  137                                  */
  138 #define RTW_CR_RE       BIT(3)  /* Receiver Enable: host enables receiver
  139                                  * by writing 1. RTL8180L indicates receiver
  140                                  * is active with 1. After power-up, host
  141                                  * must wait for reset before writing.
  142                                  */
  143 #define RTW_CR_TE       BIT(2)  /* Transmitter Enable: host enables transmitter
  144                                  * by writing 1. RTL8180L indicates transmitter
  145                                  * is active with 1. After power-up, host
  146                                  * must wait for reset before writing.
  147                                  */
  148 #define RTW_CR_MULRW    BIT(0)  /* PCI Multiple Read/Write enable: 1 enables,
  149                                  * 0 disables. XXX RTL8180, only?
  150                                  */
  151 
  152 #define RTW_IMR         0x3c    /* Interrupt Mask Register, 16b */
  153 #define RTW_ISR         0x3e    /* Interrupt status register, 16b */
  154 
  155 #define RTW_INTR_TXFOVW BIT(15)         /* Tx FIFO Overflow */
  156 #define RTW_INTR_TIMEOUT        BIT(14) /* Time Out: 1 indicates
  157                                          * RTW_TSFTR[0:31] = RTW_TINT
  158                                          */
  159 #define RTW_INTR_BCNINT BIT(13) /* Beacon Time Out: time for host to
  160                                  * prepare beacon:
  161                                  * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
  162                                  * (RTW_BCNITV_BCNITV * TU - RTW_BINTRITV)
  163                                  */
  164 #define RTW_INTR_ATIMINT        BIT(12)
  165                                 /* ATIM Time Out: ATIM interval will pass,
  166                                  * RTW_TSFTR % (RTW_BCNITV_BCNITV * TU) =
  167                                  * (RTW_ATIMWND_ATIMWND * TU - RTW_ATIMTRITV)
  168                                  */
  169 #define RTW_INTR_TBDER  BIT(11) /* Tx Beacon Descriptor Error:
  170                                  * beacon transmission aborted because
  171                                  * frame Rx'd
  172                                  */
  173 #define RTW_INTR_TBDOK  BIT(10) /* Tx Beacon Descriptor OK */
  174 #define RTW_INTR_THPDER BIT(9)  /* Tx High Priority Descriptor Error:
  175                                  * reached short/long retry limit
  176                                  */
  177 #define RTW_INTR_THPDOK BIT(8)  /* Tx High Priority Descriptor OK */
  178 #define RTW_INTR_TNPDER BIT(7)  /* Tx Normal Priority Descriptor Error:
  179                                  * reached short/long retry limit
  180                                  */
  181 #define RTW_INTR_TNPDOK BIT(6)  /* Tx Normal Priority Descriptor OK */
  182 #define RTW_INTR_RXFOVW BIT(5)  /* Rx FIFO Overflow: either RDU (see below)
  183                                  * or PCI bus too slow/busy
  184                                  */
  185 #define RTW_INTR_RDU    BIT(4)  /* Rx Descriptor Unavailable */
  186 #define RTW_INTR_TLPDER BIT(3)  /* Tx Normal Priority Descriptor Error
  187                                  * reached short/long retry limit
  188                                  */
  189 #define RTW_INTR_TLPDOK BIT(2)  /* Tx Normal Priority Descriptor OK */
  190 #define RTW_INTR_RER    BIT(1)  /* Rx Error: CRC32 or ICV error */
  191 #define RTW_INTR_ROK    BIT(0)  /* Rx OK */
  192 
  193 /* Convenient interrupt conjunctions. */
  194 #define RTW_INTR_RX     (RTW_INTR_RER|RTW_INTR_ROK)
  195 #define RTW_INTR_TX     (RTW_INTR_TLPDER|RTW_INTR_TLPDOK|RTW_INTR_THPDER|\
  196                          RTW_INTR_THPDOK|RTW_INTR_TNPDER|RTW_INTR_TNPDOK|\
  197                          RTW_INTR_TBDER|RTW_INTR_TBDOK)
  198 #define RTW_INTR_BEACON (RTW_INTR_BCNINT)
  199 #define RTW_INTR_IOERROR        (RTW_INTR_TXFOVW|RTW_INTR_RXFOVW|RTW_INTR_RDU)
  200 
  201 #define RTW_TCR         0x40    /* Transmit Configuration Register, 32b */
  202 #define RTW_TCR_CWMIN   BIT(31) /* 1: CWmin = 8, 0: CWmin = 32. */
  203 #define RTW_TCR_SWSEQ   BIT(30) /* 1: host assigns 802.11 sequence number,
  204                                  * 0: hardware assigns sequence number
  205                                  */
  206 /* Hardware version ID, read-only */
  207 #define RTW_TCR_HWVERID_MASK    BITS(29, 25)
  208 #define RTW_TCR_HWVERID_D       LSHIFT(26, RTW_TCR_HWVERID_MASK)
  209 #define RTW_TCR_HWVERID_F       LSHIFT(27, RTW_TCR_HWVERID_MASK)
  210 #define RTW_TCR_HWVERID_RTL8180 RTW_TCR_HWVERID_F
  211 
  212 /* Set ACK/CTS Timeout (EIFS).
  213  * 1: ACK rate = max(RTW_BRSR_MBR, Rx rate) (XXX not min? typo in datasheet?)
  214  * 0: ACK rate = 1Mbps
  215  */
  216 #define RTW_TCR_SAT     BIT(24)
  217 /* Max DMA Burst Size per Tx DMA Burst */
  218 #define RTW_TCR_MXDMA_MASK      BITS(23,21)
  219 #define RTW_TCR_MXDMA_16        LSHIFT(0, RTW_TCR_MXDMA_MASK)
  220 #define RTW_TCR_MXDMA_32        LSHIFT(1, RTW_TCR_MXDMA_MASK)
  221 #define RTW_TCR_MXDMA_64        LSHIFT(2, RTW_TCR_MXDMA_MASK)
  222 #define RTW_TCR_MXDMA_128       LSHIFT(3, RTW_TCR_MXDMA_MASK)
  223 #define RTW_TCR_MXDMA_256       LSHIFT(4, RTW_TCR_MXDMA_MASK)
  224 #define RTW_TCR_MXDMA_512       LSHIFT(5, RTW_TCR_MXDMA_MASK)
  225 #define RTW_TCR_MXDMA_1024      LSHIFT(6, RTW_TCR_MXDMA_MASK)
  226 #define RTW_TCR_MXDMA_2048      LSHIFT(7, RTW_TCR_MXDMA_MASK)
  227 
  228 #define RTW_TCR_DISCW           BIT(20) /* disable 802.11 random backoff */
  229 
  230 #define RTW_TCR_ICV             BIT(19) /* host lets RTL8180 append ICV to
  231                                          * WEP packets
  232                                          */
  233 
  234 /* Loopback Test: disables TXI/TXQ outputs. */
  235 #define RTW_TCR_LBK_MASK        BITS(18,17)
  236 #define RTW_TCR_LBK_NORMAL      LSHIFT(0, RTW_TCR_LBK_MASK) /* normal ops */
  237 #define RTW_TCR_LBK_MAC         LSHIFT(1, RTW_TCR_LBK_MASK) /* MAC loopback */
  238 #define RTW_TCR_LBK_BBP         LSHIFT(2, RTW_TCR_LBK_MASK) /* baseband loop. */
  239 #define RTW_TCR_LBK_CONT        LSHIFT(3, RTW_TCR_LBK_MASK) /* continuous Tx */
  240 
  241 #define RTW_TCR_CRC     BIT(16)         /* 0: RTL8180 appends CRC32
  242                                          * 1: host appends CRC32
  243                                          *
  244                                          * (I *think* this is right.
  245                                          *  The docs have a mysterious
  246                                          *  description in the
  247                                          *  passive voice.)
  248                                          */
  249 #define RTW_TCR_SRL_MASK        BITS(15,8)      /* Short Retry Limit */
  250 #define RTW_TCR_LRL_MASK        BITS(7,0)       /* Long Retry Limit */
  251 
  252 #define RTW_RCR         0x44    /* Receive Configuration Register, 32b */
  253 #define RTW_RCR_ONLYERLPKT      BIT(31) /* only do Early Rx on packets
  254                                          * longer than 1536 bytes
  255                                          */
  256 #define RTW_RCR_ENCS2           BIT(30) /* enable carrier sense method 2 */
  257 #define RTW_RCR_ENCS1           BIT(29) /* enable carrier sense method 1 */
  258 #define RTW_RCR_ENMARP          BIT(28) /* enable MAC auto-reset PHY */
  259 #define RTW_RCR_CBSSID          BIT(23) /* Check BSSID/ToDS/FromDS: set
  260                                          * "Link On" when received BSSID
  261                                          * matches RTW_BSSID and received
  262                                          * ToDS/FromDS are appropriate
  263                                          * according to RTW_MSR_NETYPE.
  264                                          */
  265 #define RTW_RCR_APWRMGT         BIT(22) /* accept packets w/ PWRMGMT bit set */
  266 #define RTW_RCR_ADD3            BIT(21) /* when RTW_MSR_NETYPE ==
  267                                          * RTW_MSR_NETYPE_INFRA_OK, accept
  268                                          * broadcast/multicast packets whose
  269                                          * 3rd address matches RTL8180's MAC.
  270                                          */
  271 #define RTW_RCR_AMF             BIT(20) /* accept management frames */
  272 #define RTW_RCR_ACF             BIT(19) /* accept control frames */
  273 #define RTW_RCR_ADF             BIT(18) /* accept data frames */
  274 /* Rx FIFO Threshold: RTL8180 begins PCI transfer when this many data
  275  * bytes are received
  276  */
  277 #define RTW_RCR_RXFTH_MASK      BITS(15,13)
  278 #define RTW_RCR_RXFTH_64        LSHIFT(2, RTW_RCR_RXFTH_MASK)
  279 #define RTW_RCR_RXFTH_128       LSHIFT(3, RTW_RCR_RXFTH_MASK)
  280 #define RTW_RCR_RXFTH_256       LSHIFT(4, RTW_RCR_RXFTH_MASK)
  281 #define RTW_RCR_RXFTH_512       LSHIFT(5, RTW_RCR_RXFTH_MASK)
  282 #define RTW_RCR_RXFTH_1024      LSHIFT(6, RTW_RCR_RXFTH_MASK)
  283 #define RTW_RCR_RXFTH_WHOLE     LSHIFT(7, RTW_RCR_RXFTH_MASK)
  284 
  285 #define RTW_RCR_AICV            BIT(12) /* accept frames w/ ICV errors */
  286 
  287 /* Max DMA Burst Size per Rx DMA Burst */
  288 #define RTW_RCR_MXDMA_MASK      BITS(10,8)
  289 #define RTW_RCR_MXDMA_16        LSHIFT(0, RTW_RCR_MXDMA_MASK)
  290 #define RTW_RCR_MXDMA_32        LSHIFT(1, RTW_RCR_MXDMA_MASK)
  291 #define RTW_RCR_MXDMA_64        LSHIFT(2, RTW_RCR_MXDMA_MASK)
  292 #define RTW_RCR_MXDMA_128       LSHIFT(3, RTW_RCR_MXDMA_MASK)
  293 #define RTW_RCR_MXDMA_256       LSHIFT(4, RTW_RCR_MXDMA_MASK)
  294 #define RTW_RCR_MXDMA_512       LSHIFT(5, RTW_RCR_MXDMA_MASK)
  295 #define RTW_RCR_MXDMA_1024      LSHIFT(6, RTW_RCR_MXDMA_MASK)
  296 #define RTW_RCR_MXDMA_UNLIMITED LSHIFT(7, RTW_RCR_MXDMA_MASK)
  297 
  298 /* EEPROM type, read-only. 1: EEPROM is 93c56, 0: 93c46 */
  299 #define RTW_RCR_9356SEL         BIT(6)
  300 
  301 #define RTW_RCR_ACRC32          BIT(5)  /* accept frames w/ CRC32 errors */
  302 #define RTW_RCR_AB              BIT(3)  /* accept broadcast frames */
  303 #define RTW_RCR_AM              BIT(2)  /* accept multicast frames */
  304 /* accept physical match frames. XXX means PLCP header ok? */
  305 #define RTW_RCR_APM             BIT(1)
  306 #define RTW_RCR_AAP             BIT(0)  /* accept frames w/ destination */
  307 
  308 /* Additional bits to set in monitor mode. */
  309 #define RTW_RCR_MONITOR (               \
  310     RTW_RCR_AAP |                       \
  311     RTW_RCR_ACF |                       \
  312     RTW_RCR_ACRC32 |                    \
  313     RTW_RCR_AICV |                      \
  314     0)
  315 
  316 /* The packet filter bits. */
  317 #define RTW_RCR_PKTFILTER_MASK (\
  318     RTW_RCR_AAP |               \
  319     RTW_RCR_AB |                \
  320     RTW_RCR_ACF |               \
  321     RTW_RCR_ACRC32 |            \
  322     RTW_RCR_ADD3 |              \
  323     RTW_RCR_ADF |               \
  324     RTW_RCR_AICV |              \
  325     RTW_RCR_AM |                \
  326     RTW_RCR_AMF |               \
  327     RTW_RCR_APM |               \
  328     RTW_RCR_APWRMGT |           \
  329     0)
  330 
  331 /* Receive power-management frames and mgmt/ctrl/data frames. */
  332 #define RTW_RCR_PKTFILTER_DEFAULT       (       \
  333     RTW_RCR_ADF |                               \
  334     RTW_RCR_AMF |                               \
  335     RTW_RCR_APM |                               \
  336     RTW_RCR_APWRMGT |                           \
  337     0)
  338 
  339 #define RTW_TINT        0x48    /* Timer Interrupt Register, 32b */
  340 #define RTW_TBDA        0x4c    /* Transmit Beacon Descriptor Start Address,
  341                                  * 32b, 256-byte alignment
  342                                  */
  343 #define RTW_9346CR      0x50    /* 93c46/93c56 Command Register, 8b */
  344 #define RTW_9346CR_EEM_MASK     BITS(7,6)       /* Operating Mode */
  345 #define RTW_9346CR_EEM_NORMAL   LSHIFT(0, RTW_9346CR_EEM_MASK)
  346 /* Load the EEPROM. Reset registers to defaults.
  347  * Takes ~2ms. RTL8180 indicates completion with RTW_9346CR_EEM_NORMAL.
  348  * XXX RTL8180 only?
  349  */
  350 #define RTW_9346CR_EEM_AUTOLOAD LSHIFT(1, RTW_9346CR_EEM_MASK)
  351 /* Disable network & bus-master operations and enable
  352  * _EECS, _EESK, _EEDI, _EEDO.
  353  * XXX RTL8180 only?
  354  */
  355 #define RTW_9346CR_EEM_PROGRAM  LSHIFT(2, RTW_9346CR_EEM_MASK)
  356 /* Enable RTW_CONFIG[0123] registers. */
  357 #define RTW_9346CR_EEM_CONFIG   LSHIFT(3, RTW_9346CR_EEM_MASK)
  358 /* EEPROM pin status/control in _EEM_CONFIG, _EEM_AUTOLOAD modes.
  359  * XXX RTL8180 only?
  360  */
  361 #define RTW_9346CR_EECS BIT(3)
  362 #define RTW_9346CR_EESK BIT(2)
  363 #define RTW_9346CR_EEDI BIT(1)
  364 #define RTW_9346CR_EEDO BIT(0)  /* read-only */
  365 
  366 #define RTW_CONFIG0     0x51    /* Configuration Register 0, 8b */
  367 #define RTW_CONFIG0_WEP40       BIT(7)  /* implements 40-bit WEP,
  368                                          * XXX RTL8180 only?
  369                                          */
  370 #define RTW_CONFIG0_WEP104      BIT(6)  /* implements 104-bit WEP,
  371                                          * from EEPROM, read-only
  372                                          * XXX RTL8180 only?
  373                                          */
  374 #define RTW_CONFIG0_LEDGPOEN    BIT(4)  /* 1: RTW_PSR_LEDGPO[01] control
  375                                          *    LED[01] pins.
  376                                          * 0: LED behavior defined by
  377                                          *    RTW_CONFIG1_LEDS10_MASK
  378                                          * XXX RTL8180 only?
  379                                          */
  380 /* auxiliary power is present, read-only */
  381 #define RTW_CONFIG0_AUXPWR      BIT(3)
  382 /* Geographic Location, read-only */
  383 #define RTW_CONFIG0_GL_MASK             BITS(1,0)
  384 /* _RTW_CONFIG0_GL_* is what the datasheet says, but RTW_CONFIG0_GL_*
  385  * work.
  386  */
  387 #define _RTW_CONFIG0_GL_USA             LSHIFT(3, RTW_CONFIG0_GL_MASK)
  388 #define RTW_CONFIG0_GL_EUROPE           LSHIFT(2, RTW_CONFIG0_GL_MASK)
  389 #define RTW_CONFIG0_GL_JAPAN            LSHIFT(1, RTW_CONFIG0_GL_MASK)
  390 #define RTW_CONFIG0_GL_USA              LSHIFT(0, RTW_CONFIG0_GL_MASK)
  391 /* RTL8181 datasheet says RTW_CONFIG0_GL_JAPAN = 0. */
  392 
  393 #define RTW_CONFIG1     0x52    /* Configuration Register 1, 8b */
  394 
  395 /* LED configuration. From EEPROM. Read/write.
  396  *
  397  * Setting                              LED0            LED1
  398  * -------                              ----            ----
  399  * RTW_CONFIG1_LEDS_ACT_INFRA           Activity        Infrastructure
  400  * RTW_CONFIG1_LEDS_ACT_LINK            Activity        Link
  401  * RTW_CONFIG1_LEDS_TX_RX               Tx              Rx
  402  * RTW_CONFIG1_LEDS_LINKACT_INFRA       Link/Activity   Infrastructure
  403  */
  404 #define RTW_CONFIG1_LEDS_MASK   BITS(7,6)
  405 #define RTW_CONFIG1_LEDS_ACT_INFRA      LSHIFT(0, RTW_CONFIG1_LEDS_MASK)
  406 #define RTW_CONFIG1_LEDS_ACT_LINK       LSHIFT(1, RTW_CONFIG1_LEDS_MASK)
  407 #define RTW_CONFIG1_LEDS_TX_RX          LSHIFT(2, RTW_CONFIG1_LEDS_MASK)
  408 #define RTW_CONFIG1_LEDS_LINKACT_INFRA  LSHIFT(3, RTW_CONFIG1_LEDS_MASK)
  409 
  410 /* LWAKE Output Signal. Only applicable to Cardbus. Pulse width is 150ms.
  411  *
  412  *                                   RTW_CONFIG1_LWACT
  413  *                              0                       1
  414  * RTW_CONFIG4_LWPTN    0       active high             active low
  415  *                      1       positive pulse          negative pulse
  416  */
  417 #define RTW_CONFIG1_LWACT       BIT(4)
  418 
  419 #define RTW_CONFIG1_MEMMAP      BIT(3)  /* using PCI memory space, read-only */
  420 #define RTW_CONFIG1_IOMAP       BIT(2)  /* using PCI I/O space, read-only */
  421 #define RTW_CONFIG1_VPD         BIT(1)  /* if set, VPD from offsets
  422                                          * 0x40-0x7f in EEPROM are at
  423                                          * registers 0x60-0x67 of PCI
  424                                          * Configuration Space (XXX huh?)
  425                                          */
  426 #define RTW_CONFIG1_PMEN        BIT(0)  /* Power Management Enable: TBD */
  427 
  428 #define RTW_CONFIG2     0x53    /* Configuration Register 2, 8b */
  429 #define RTW_CONFIG2_LCK BIT(7)  /* clocks are locked, read-only:
  430                                  * Tx frequency & symbol clocks
  431                                  * are derived from the same OSC
  432                                  */
  433 #define RTW_CONFIG2_ANT BIT(6)  /* diversity enabled, read-only */
  434 #define RTW_CONFIG2_DPS BIT(3)  /* Descriptor Polling State: enable
  435                                  * test mode.
  436                                  */
  437 #define RTW_CONFIG2_PAPESIGN            BIT(2)          /* TBD, from EEPROM */
  438 #define RTW_CONFIG2_PAPETIME_MASK       BITS(1,0)       /* TBD, from EEPROM */
  439 
  440 #define RTW_ANAPARM     0x54    /* Analog parameter, 32b */
  441 #define RTW_ANAPARM_RFPOW0_MASK BITS(30,28)             /* undocumented bits
  442                                                          * which appear to
  443                                                          * control the power
  444                                                          * state of the RF
  445                                                          * components
  446                                                          */
  447 #define RTW_ANAPARM_RFPOW_MASK  \
  448     (RTW_ANAPARM_RFPOW0_MASK|RTW_ANAPARM_RFPOW1_MASK)
  449 
  450 #define RTW_ANAPARM_TXDACOFF    BIT(27)                 /* 1: disable Tx DAC,
  451                                                          * 0: enable
  452                                                          */
  453 #define RTW_ANAPARM_RFPOW1_MASK BITS(26,20)             /* undocumented bits
  454                                                          * which appear to
  455                                                          * control the power
  456                                                          * state of the RF
  457                                                          * components
  458                                                          */
  459 
  460 /*
  461  * Maxim On/Sleep/Off control
  462  */
  463 #define RTW_ANAPARM_RFPOW_MAXIM_ON      LSHIFT(0x8, RTW_ANAPARM_RFPOW1_MASK)
  464 
  465 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
  466 #define RTW_ANAPARM_RFPOW_MAXIM_SLEEP   LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK)
  467 
  468 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
  469 #define RTW_ANAPARM_RFPOW_MAXIM_OFF     LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK)
  470 
  471 /*
  472  * RFMD On/Sleep/Off control
  473  */
  474 #define RTW_ANAPARM_RFPOW_RFMD_ON       LSHIFT(0x408, RTW_ANAPARM_RFPOW1_MASK)
  475 
  476 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
  477 #define RTW_ANAPARM_RFPOW_RFMD_SLEEP    LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK)
  478 
  479 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
  480 #define RTW_ANAPARM_RFPOW_RFMD_OFF      LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK)
  481 
  482 /*
  483  * Philips On/Sleep/Off control
  484  */
  485 #define RTW_ANAPARM_RFPOW_ANA_PHILIPS_ON        \
  486     LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK)
  487 #define RTW_ANAPARM_RFPOW_DIG_PHILIPS_ON        \
  488     LSHIFT(0x008, RTW_ANAPARM_RFPOW1_MASK)
  489 
  490 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
  491 #define RTW_ANAPARM_RFPOW_PHILIPS_SLEEP\
  492     LSHIFT(0x378, RTW_ANAPARM_RFPOW1_MASK)
  493 
  494 /* reg[RTW_ANAPARM] |= RTW_ANAPARM_TXDACOFF; */
  495 #define RTW_ANAPARM_RFPOW_PHILIPS_OFF\
  496     LSHIFT(0x379, RTW_ANAPARM_RFPOW1_MASK)
  497 
  498 #define RTW_ANAPARM_RFPOW_PHILIPS_ON    LSHIFT(0x328, RTW_ANAPARM_RFPOW1_MASK)
  499 
  500 #define RTW_ANAPARM_CARDSP_MASK BITS(19,0)              /* undocumented
  501                                                          * card-specific
  502                                                          * bits from the
  503                                                          * EEPROM.
  504                                                          */
  505 
  506 #define RTW_MSR         0x58    /* Media Status Register, 8b */
  507 /* Network Type and Link Status */
  508 #define RTW_MSR_NETYPE_MASK     BITS(3,2)
  509 /* AP, XXX RTL8181 only? */
  510 #define RTW_MSR_NETYPE_AP_OK    LSHIFT(3, RTW_MSR_NETYPE_MASK)
  511 /* infrastructure link ok */
  512 #define RTW_MSR_NETYPE_INFRA_OK LSHIFT(2, RTW_MSR_NETYPE_MASK)
  513 /* ad-hoc link ok */
  514 #define RTW_MSR_NETYPE_ADHOC_OK LSHIFT(1, RTW_MSR_NETYPE_MASK)
  515 /* no link */
  516 #define RTW_MSR_NETYPE_NOLINK   LSHIFT(0, RTW_MSR_NETYPE_MASK)
  517 
  518 #define RTW_CONFIG3     0x59    /* Configuration Register 3, 8b */
  519 #define RTW_CONFIG3_GNTSEL      BIT(7)  /* Grant Select, read-only */
  520 #define RTW_CONFIG3_PARMEN      BIT(6)  /* Set RTW_CONFIG3_PARMEN and
  521                                          * RTW_9346CR_EEM_CONFIG to
  522                                          * allow RTW_ANAPARM writes.
  523                                          */
  524 #define RTW_CONFIG3_MAGIC       BIT(5)  /* Valid when RTW_CONFIG1_PMEN is
  525                                          * set. If set, RTL8180 wakes up
  526                                          * OS when Magic Packet is Rx'd.
  527                                          */
  528 #define RTW_CONFIG3_CARDBEN     BIT(3)  /* Cardbus-related registers
  529                                          * and functions are enabled,
  530                                          * read-only. XXX RTL8180 only.
  531                                          */
  532 #define RTW_CONFIG3_CLKRUNEN    BIT(2)  /* CLKRUN enabled, read-only.
  533                                          * XXX RTL8180 only.
  534                                          */
  535 #define RTW_CONFIG3_FUNCREGEN   BIT(1)  /* Function Registers Enabled,
  536                                          * read-only. XXX RTL8180 only.
  537                                          */
  538 #define RTW_CONFIG3_FBTBEN      BIT(0)  /* Fast back-to-back enabled,
  539                                          * read-only.
  540                                          */
  541 #define RTW_CONFIG4     0x5A    /* Configuration Register 4, 8b */
  542 #define RTW_CONFIG4_VCOPDN      BIT(7)  /* VCO Power Down
  543                                          * 0: normal operation
  544                                          *    (power-on default)
  545                                          * 1: power-down VCO, RF front-end,
  546                                          *    and most RTL8180 components.
  547                                          */
  548 #define RTW_CONFIG4_PWROFF      BIT(6)  /* Power Off
  549                                          * 0: normal operation
  550                                          *    (power-on default)
  551                                          * 1: power-down RF front-end,
  552                                          *    and most RTL8180 components,
  553                                          *    but leave VCO on.
  554                                          *
  555                                          * XXX RFMD front-end only?
  556                                          */
  557 #define RTW_CONFIG4_PWRMGT      BIT(5)  /* Power Management
  558                                          * 0: normal operation
  559                                          *    (power-on default)
  560                                          * 1: set Tx packet's PWRMGMT bit.
  561                                          */
  562 #define RTW_CONFIG4_LWPME       BIT(4)  /* LANWAKE vs. PMEB: Cardbus-only
  563                                          * 0: LWAKE & PMEB asserted
  564                                          *    simultaneously
  565                                          * 1: LWAKE asserted only if
  566                                          *    both PMEB is asserted and
  567                                          *    ISOLATEB is low.
  568                                          * XXX RTL8180 only.
  569                                          */
  570 #define RTW_CONFIG4_LWPTN       BIT(2)  /* see RTW_CONFIG1_LWACT
  571                                          * XXX RTL8180 only.
  572                                          */
  573 /* Radio Front-End Programming Method */
  574 #define RTW_CONFIG4_RFTYPE_MASK BITS(1,0)
  575 #define RTW_CONFIG4_RFTYPE_INTERSIL     LSHIFT(1, RTW_CONFIG4_RFTYPE_MASK)
  576 #define RTW_CONFIG4_RFTYPE_RFMD         LSHIFT(2, RTW_CONFIG4_RFTYPE_MASK)
  577 #define RTW_CONFIG4_RFTYPE_PHILIPS      LSHIFT(3, RTW_CONFIG4_RFTYPE_MASK)
  578 
  579 #define RTW_TESTR       0x5B    /* TEST mode register, 8b */
  580 
  581 #define RTW_PSR         0x5e    /* Page Select Register, 8b */
  582 #define RTW_PSR_GPO     BIT(7)  /* Control/status of pin 52. */
  583 #define RTW_PSR_GPI     BIT(6)  /* Status of pin 64. */
  584 #define RTW_PSR_LEDGPO1 BIT(5)  /* Status/control of LED1 pin if
  585                                  * RTW_CONFIG0_LEDGPOEN is set.
  586                                  */
  587 #define RTW_PSR_LEDGPO0 BIT(4)  /* Status/control of LED0 pin if
  588                                  * RTW_CONFIG0_LEDGPOEN is set.
  589                                  */
  590 #define RTW_PSR_UWF     BIT(1)  /* Enable Unicast Wakeup Frame */
  591 #define RTW_PSR_PSEN    BIT(0)  /* 1: page 1, 0: page 0 */
  592 
  593 #define RTW_SCR         0x5f    /* Security Configuration Register, 8b */
  594 #define RTW_SCR_KM_MASK BITS(5,4)       /* Key Mode */
  595 #define RTW_SCR_KM_WEP104       LSHIFT(1, RTW_SCR_KM_MASK)
  596 #define RTW_SCR_KM_WEP40        LSHIFT(0, RTW_SCR_KM_MASK)
  597 #define RTW_SCR_TXSECON         BIT(1)  /* Enable Tx WEP. Invalid if
  598                                          * neither RTW_CONFIG0_WEP40 nor
  599                                          * RTW_CONFIG0_WEP104 is set.
  600                                          */
  601 #define RTW_SCR_RXSECON         BIT(0)  /* Enable Rx WEP. Invalid if
  602                                          * neither RTW_CONFIG0_WEP40 nor
  603                                          * RTW_CONFIG0_WEP104 is set.
  604                                          */
  605 
  606 #define RTW_BCNITV      0x70    /* Beacon Interval Register, 16b */
  607 #define RTW_BCNITV_BCNITV_MASK  BITS(9,0)       /* TU between TBTT, written
  608                                                  * by host.
  609                                                  */
  610 #define RTW_ATIMWND     0x72    /* ATIM Window Register, 16b */
  611 #define RTW_ATIMWND_ATIMWND     BITS(9,0)       /* ATIM Window length in TU,
  612                                                  * written by host.
  613                                                  */
  614 
  615 #define RTW_BINTRITV    0x74    /* Beacon Interrupt Interval Register, 16b */
  616 #define RTW_BINTRITV_BINTRITV   BITS(9,0)       /* RTL8180 wakes host with
  617                                                  * RTW_INTR_BCNINT at BINTRITV
  618                                                  * microseconds before TBTT
  619                                                  */
  620 #define RTW_ATIMTRITV   0x76    /* ATIM Interrupt Interval Register, 16b */
  621 #define RTW_ATIMTRITV_ATIMTRITV BITS(9,0)       /* RTL8180 wakes host with
  622                                                  * RTW_INTR_ATIMINT at ATIMTRITV
  623                                                  * microseconds before end of
  624                                                  * ATIM Window
  625                                                  */
  626 
  627 #define RTW_PHYDELAY    0x78    /* PHY Delay Register, 8b */
  628 #define RTW_PHYDELAY_REVC_MAGIC BIT(3)          /* Rev. C magic from reference
  629                                                  * driver
  630                                                  */
  631 #define RTW_PHYDELAY_PHYDELAY   BITS(2,0)       /* microsecond Tx delay between
  632                                                  * MAC and RF front-end
  633                                                  */
  634 #define RTW_CRCOUNT     0x79    /* Carrier Sense Counter, 8b */
  635 #define RTW_CRCOUNT_MAGIC       0x4c
  636 
  637 #define RTW_CRC16ERR    0x7a    /* CRC16 error count, 16b, XXX RTL8181 only? */
  638 
  639 #define RTW_BB  0x7c            /* Baseband interface, 32b */
  640 /* used for writing RTL8180's integrated baseband processor */
  641 #define RTW_BB_RD_MASK          BITS(23,16)     /* data to read */
  642 #define RTW_BB_WR_MASK          BITS(15,8)      /* data to write */
  643 #define RTW_BB_WREN             BIT(7)          /* write enable */
  644 #define RTW_BB_ADDR_MASK        BITS(6,0)       /* address */
  645 
  646 #define RTW_PHYADDR     0x7c    /* Address register for PHY interface, 8b */
  647 #define RTW_PHYDATAW    0x7d    /* Write data to PHY, 8b, write-only */
  648 #define RTW_PHYDATAR    0x7e    /* Read data from PHY, 8b (?), read-only */
  649 
  650 #define RTW_PHYCFG      0x80    /* PHY Configuration Register, 32b */
  651 #define RTW_PHYCFG_MAC_POLL     BIT(31)         /* if !RTW_PHYCFG_HST,
  652                                                  * host sets. MAC clears
  653                                                  * after banging bits.
  654                                                  */
  655 #define RTW_PHYCFG_HST          BIT(30)         /* 1: host bangs bits
  656                                                  * 0: MAC bangs bits
  657                                                  */
  658 #define RTW_PHYCFG_MAC_RFTYPE_MASK      BITS(29,28)
  659 #define RTW_PHYCFG_MAC_RFTYPE_INTERSIL  LSHIFT(0, RTW_PHYCFG_MAC_RFTYPE_MASK)
  660 #define RTW_PHYCFG_MAC_RFTYPE_RFMD      LSHIFT(1, RTW_PHYCFG_MAC_RFTYPE_MASK)
  661 #define RTW_PHYCFG_MAC_RFTYPE_GCT       RTW_PHYCFG_MAC_RFTYPE_RFMD
  662 #define RTW_PHYCFG_MAC_RFTYPE_PHILIPS   LSHIFT(3, RTW_PHYCFG_MAC_RFTYPE_MASK)
  663 #define RTW_PHYCFG_MAC_PHILIPS_ADDR_MASK        BITS(27,24)
  664 #define RTW_PHYCFG_MAC_PHILIPS_DATA_MASK        BITS(23,0)
  665 #define RTW_PHYCFG_MAC_MAXIM_LODATA_MASK        BITS(27,24)
  666 #define RTW_PHYCFG_MAC_MAXIM_ADDR_MASK          BITS(11,8)
  667 #define RTW_PHYCFG_MAC_MAXIM_HIDATA_MASK        BITS(7,0)
  668 #define RTW_PHYCFG_HST_EN               BIT(2)
  669 #define RTW_PHYCFG_HST_CLK              BIT(1)
  670 #define RTW_PHYCFG_HST_DATA             BIT(0)
  671 
  672 #define RTW_MAXIM_HIDATA_MASK                   BITS(11,4)
  673 #define RTW_MAXIM_LODATA_MASK                   BITS(3,0)
  674 
  675 /**
  676  ** 0x84 - 0xD3, page 1, selected when RTW_PSR[PSEN] == 1.
  677  **/
  678 
  679 #define RTW_WAKEUP0L    0x84    /* Power Management Wakeup Frame */
  680 #define RTW_WAKEUP0H    0x88    /* 32b */
  681 
  682 #define RTW_WAKEUP1L    0x8c
  683 #define RTW_WAKEUP1H    0x90
  684 
  685 #define RTW_WAKEUP2LL   0x94
  686 #define RTW_WAKEUP2LH   0x98
  687 
  688 #define RTW_WAKEUP2HL   0x9c
  689 #define RTW_WAKEUP2HH   0xa0
  690 
  691 #define RTW_WAKEUP3LL   0xa4
  692 #define RTW_WAKEUP3LH   0xa8
  693 
  694 #define RTW_WAKEUP3HL   0xac
  695 #define RTW_WAKEUP3HH   0xb0
  696 
  697 #define RTW_WAKEUP4LL   0xb4
  698 #define RTW_WAKEUP4LH   0xb8
  699 
  700 #define RTW_WAKEUP4HL   0xbc
  701 #define RTW_WAKEUP4HH   0xc0
  702 
  703 #define RTW_CRC0        0xc4    /* CRC of wakeup frame 0, 16b */
  704 #define RTW_CRC1        0xc6    /* CRC of wakeup frame 1, 16b */
  705 #define RTW_CRC2        0xc8    /* CRC of wakeup frame 2, 16b */
  706 #define RTW_CRC3        0xca    /* CRC of wakeup frame 3, 16b */
  707 #define RTW_CRC4        0xcc    /* CRC of wakeup frame 4, 16b */
  708 
  709 /**
  710  ** 0x84 - 0xD3, page 0, selected when RTW_PSR[PSEN] == 0.
  711  **/
  712 
  713 /* Default Key Registers, each 128b
  714  *
  715  * If RTW_SCR_KM_WEP104, 104 lsb are the key.
  716  * If RTW_SCR_KM_WEP40, 40 lsb are the key.
  717  */
  718 #define RTW_DK0         0x90    /* Default Key 0 Register, 128b */
  719 #define RTW_DK1         0xa0    /* Default Key 1 Register, 128b */
  720 #define RTW_DK2         0xb0    /* Default Key 2 Register, 128b */
  721 #define RTW_DK3         0xc0    /* Default Key 3 Register, 128b */
  722 
  723 #define RTW_CONFIG5     0xd8    /* Configuration Register 5, 8b */
  724 #define RTW_CONFIG5_TXFIFOOK    BIT(7)  /* Tx FIFO self-test pass, read-only */
  725 #define RTW_CONFIG5_RXFIFOOK    BIT(6)  /* Rx FIFO self-test pass, read-only */
  726 #define RTW_CONFIG5_CALON       BIT(5)  /* 1: start calibration cycle
  727                                          *    and raise AGCRESET pin.
  728                                          * 0: lower AGCRESET pin
  729                                          */
  730 #define RTW_CONFIG5_EACPI       BIT(2)  /* Enable ACPI Wake up, default 0 */
  731 #define RTW_CONFIG5_LANWAKE     BIT(1)  /* Enable LAN Wake signal,
  732                                          * from EEPROM
  733                                          */
  734 #define RTW_CONFIG5_PMESTS      BIT(0)  /* 1: both software & PCI Reset
  735                                          *    reset PME_Status
  736                                          * 0: only software resets PME_Status
  737                                          *
  738                                          * From EEPROM.
  739                                          */
  740 
  741 #define RTW_TPPOLL      0xd9    /* Transmit Priority Polling Register, 8b,
  742                                  * write-only.
  743                                  */
  744 #define RTW_TPPOLL_BQ   BIT(7)  /* RTL8180 clears to notify host of a beacon
  745                                  * Tx. Host writes have no effect.
  746                                  */
  747 #define RTW_TPPOLL_HPQ  BIT(6)  /* Host writes 1 to notify RTL8180 of
  748                                  * high-priority Tx packets, RTL8180 clears
  749                                  * to after high-priority Tx is complete.
  750                                  */
  751 #define RTW_TPPOLL_NPQ  BIT(5)  /* If RTW_CONFIG2_DPS is set,
  752                                  * host writes 1 to notify RTL8180 of
  753                                  * normal-priority Tx packets, RTL8180 clears
  754                                  * after normal-priority Tx is complete.
  755                                  *
  756                                  * If RTW_CONFIG2_DPS is clear, host writes
  757                                  * have no effect. RTL8180 clears after
  758                                  * normal-priority Tx is complete.
  759                                  */
  760 #define RTW_TPPOLL_LPQ  BIT(4)  /* Host writes 1 to notify RTL8180 of
  761                                  * low-priority Tx packets, RTL8180 clears
  762                                  * after low-priority Tx is complete.
  763                                  */
  764 #define RTW_TPPOLL_SBQ  BIT(3)  /* Host writes 1 to tell RTL8180 to
  765                                  * stop beacon DMA. This bit is invalid
  766                                  * when RTW_CONFIG2_DPS is set.
  767                                  */
  768 #define RTW_TPPOLL_SHPQ BIT(2)  /* Host writes 1 to tell RTL8180 to
  769                                  * stop high-priority DMA.
  770                                  */
  771 #define RTW_TPPOLL_SNPQ BIT(1)  /* Host writes 1 to tell RTL8180 to
  772                                  * stop normal-priority DMA. This bit is invalid
  773                                  * when RTW_CONFIG2_DPS is set.
  774                                  */
  775 #define RTW_TPPOLL_SLPQ BIT(0)  /* Host writes 1 to tell RTL8180 to
  776                                  * stop low-priority DMA.
  777                                  */
  778 
  779 /* Start all queues. */
  780 #define RTW_TPPOLL_ALL  (RTW_TPPOLL_BQ | RTW_TPPOLL_HPQ | \
  781                          RTW_TPPOLL_NPQ | RTW_TPPOLL_LPQ)
  782 /* Stop all queues. */
  783 #define RTW_TPPOLL_SALL (RTW_TPPOLL_SBQ | RTW_TPPOLL_SHPQ | \
  784                          RTW_TPPOLL_SNPQ | RTW_TPPOLL_SLPQ)
  785 
  786 #define RTW_CWR         0xdc    /* Contention Window Register, 16b, read-only */
  787 /* Contention Window: indicates number of contention windows before Tx
  788  */
  789 #define RTW_CWR_CW      BITS(9,0)
  790 
  791 /* Retry Count Register, 16b, read-only */
  792 #define RTW_RETRYCTR    0xde
  793 /* Retry Count: indicates number of retries after Tx */
  794 #define RTW_RETRYCTR_RETRYCT    BITS(7,0)
  795 
  796 #define RTW_RDSAR       0xe4    /* Receive descriptor Start Address Register,
  797                                  * 32b, 256-byte alignment.
  798                                  */
  799 /* Function Event Register, 32b, Cardbus only. Only valid when
  800  * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
  801  */
  802 #define RTW_FER         0xf0
  803 #define RTW_FER_INTR    BIT(15) /* set when RTW_FFER_INTR is set */
  804 #define RTW_FER_GWAKE   BIT(4)  /* General Wakeup */
  805 /* Function Event Mask Register, 32b, Cardbus only. Only valid when
  806  * both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN are set.
  807  */
  808 #define RTW_FEMR        0xf4
  809 #define RTW_FEMR_INTR   BIT(15) /* set when RTW_FFER_INTR is set */
  810 #define RTW_FEMR_WKUP   BIT(14) /* Wakeup Mask */
  811 #define RTW_FEMR_GWAKE  BIT(4)  /* General Wakeup */
  812 /* Function Present State Register, 32b, read-only, Cardbus only.
  813  * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
  814  * are set.
  815  */
  816 #define RTW_FPSR        0xf8
  817 #define RTW_FPSR_INTR   BIT(15) /* TBD */
  818 #define RTW_FPSR_GWAKE  BIT(4)  /* General Wakeup: TBD */
  819 /* Function Force Event Register, 32b, write-only, Cardbus only.
  820  * Only valid when both RTW_CONFIG3_CARDBEN and RTW_CONFIG3_FUNCREGEN
  821  * are set.
  822  */
  823 #define RTW_FFER        0xfc
  824 #define RTW_FFER_INTR   BIT(15) /* TBD */
  825 #define RTW_FFER_GWAKE  BIT(4)  /* General Wakeup: TBD */
  826 
  827 /* Serial EEPROM offsets */
  828 #define RTW_SR_ID       0x00    /* 16b */
  829 #define RTW_SR_VID      0x02    /* 16b */
  830 #define RTW_SR_DID      0x04    /* 16b */
  831 #define RTW_SR_SVID     0x06    /* 16b */
  832 #define RTW_SR_SMID     0x08    /* 16b */
  833 #define RTW_SR_MNGNT    0x0a
  834 #define RTW_SR_MXLAT    0x0b
  835 #define RTW_SR_RFCHIPID 0x0c
  836 #define RTW_SR_CONFIG3  0x0d
  837 #define RTW_SR_MAC      0x0e    /* 6 bytes */
  838 #define RTW_SR_CONFIG0  0x14
  839 #define RTW_SR_CONFIG1  0x15
  840 #define RTW_SR_PMC      0x16    /* Power Management Capabilities, 16b */
  841 #define RTW_SR_CONFIG2  0x18
  842 #define RTW_SR_CONFIG4  0x19
  843 #define RTW_SR_ANAPARM  0x1a    /* Analog Parameters, 32b */
  844 #define RTW_SR_TESTR    0x1e
  845 #define RTW_SR_CONFIG5  0x1f
  846 #define RTW_SR_TXPOWER1         0x20
  847 #define RTW_SR_TXPOWER2         0x21
  848 #define RTW_SR_TXPOWER3         0x22
  849 #define RTW_SR_TXPOWER4         0x23
  850 #define RTW_SR_TXPOWER5         0x24
  851 #define RTW_SR_TXPOWER6         0x25
  852 #define RTW_SR_TXPOWER7         0x26
  853 #define RTW_SR_TXPOWER8         0x27
  854 #define RTW_SR_TXPOWER9         0x28
  855 #define RTW_SR_TXPOWER10        0x29
  856 #define RTW_SR_TXPOWER11        0x2a
  857 #define RTW_SR_TXPOWER12        0x2b
  858 #define RTW_SR_TXPOWER13        0x2c
  859 #define RTW_SR_TXPOWER14        0x2d
  860 #define RTW_SR_CHANNELPLAN      0x2e    /* bitmap of channels to scan */
  861 #define RTW_SR_ENERGYDETTHR     0x2f    /* energy-detect threshold */
  862 #define RTW_SR_ENERGYDETTHR_DEFAULT     0x0c    /* use this if old SROM */
  863 #define RTW_SR_CISPOINTER       0x30    /* 16b */
  864 #define RTW_SR_RFPARM           0x32    /* RF-specific parameter */
  865 #define RTW_SR_RFPARM_DIGPHY    BIT(0)          /* 1: digital PHY */
  866 #define RTW_SR_RFPARM_DFLANTB   BIT(1)          /* 1: antenna B is default */
  867 #define RTW_SR_RFPARM_CS_MASK   BITS(2,3)       /* carrier-sense type */
  868 #define RTW_SR_VERSION          0x3c    /* EEPROM content version, 16b */
  869 #define RTW_SR_CRC              0x3e    /* EEPROM content CRC, 16b */
  870 #define RTW_SR_VPD              0x40    /* Vital Product Data, 64 bytes */
  871 #define RTW_SR_CIS              0x80    /* CIS Data, 93c56 only, 128 bytes*/
  872 
  873 /*
  874  * RTL8180 Transmit/Receive Descriptors
  875  */
  876 
  877 /* the first descriptor in each ring must be on a 256-byte boundary */
  878 #define RTW_DESC_ALIGNMENT 256
  879 
  880 /* Tx descriptor */
  881 struct rtw_txdesc {
  882         uint32_t        td_ctl0;
  883         uint32_t        td_ctl1;
  884         uint32_t        td_buf;
  885         uint32_t        td_len;
  886         uint32_t        td_next;
  887         uint32_t        td_rsvd[3];
  888 };
  889 
  890 #define td_stat td_ctl0
  891 
  892 #define RTW_TXCTL0_OWN                  BIT(31)         /* 1: ready to Tx */
  893 #define RTW_TXCTL0_RSVD0                BIT(30)         /* reserved */
  894 #define RTW_TXCTL0_FS                   BIT(29)         /* first segment */
  895 #define RTW_TXCTL0_LS                   BIT(28)         /* last segment */
  896 
  897 #define RTW_TXCTL0_RATE_MASK            BITS(27,24)     /* Tx rate */
  898 #define RTW_TXCTL0_RATE_1MBPS           LSHIFT(0, RTW_TXCTL0_RATE_MASK)
  899 #define RTW_TXCTL0_RATE_2MBPS           LSHIFT(1, RTW_TXCTL0_RATE_MASK)
  900 #define RTW_TXCTL0_RATE_5MBPS           LSHIFT(2, RTW_TXCTL0_RATE_MASK)
  901 #define RTW_TXCTL0_RATE_11MBPS          LSHIFT(3, RTW_TXCTL0_RATE_MASK)
  902 
  903 #define RTW_TXCTL0_RTSEN                BIT(23)         /* RTS Enable */
  904 
  905 #define RTW_TXCTL0_RTSRATE_MASK         BITS(22,19)     /* Tx rate */
  906 #define RTW_TXCTL0_RTSRATE_1MBPS        LSHIFT(0, RTW_TXCTL0_RTSRATE_MASK)
  907 #define RTW_TXCTL0_RTSRATE_2MBPS        LSHIFT(1, RTW_TXCTL0_RTSRATE_MASK)
  908 #define RTW_TXCTL0_RTSRATE_5MBPS        LSHIFT(2, RTW_TXCTL0_RTSRATE_MASK)
  909 #define RTW_TXCTL0_RTSRATE_11MBPS       LSHIFT(3, RTW_TXCTL0_RTSRATE_MASK)
  910 
  911 #define RTW_TXCTL0_BEACON               BIT(18) /* packet is a beacon */
  912 #define RTW_TXCTL0_MOREFRAG             BIT(17) /* another fragment follows */
  913 #define RTW_TXCTL0_SPLCP                BIT(16) /* add short PLCP preamble
  914                                                  * and header
  915                                                  */
  916 #define RTW_TXCTL0_KEYID_MASK           BITS(15,14)     /* default key id */
  917 #define RTW_TXCTL0_RSVD1_MASK           BITS(13,12)     /* reserved */
  918 #define RTW_TXCTL0_TPKTSIZE_MASK        BITS(11,0)      /* Tx packet size
  919                                                          * in bytes
  920                                                          */
  921 
  922 #define RTW_TXSTAT_OWN          RTW_TXCTL0_OWN
  923 #define RTW_TXSTAT_RSVD0        RTW_TXCTL0_RSVD0
  924 #define RTW_TXSTAT_FS           RTW_TXCTL0_FS
  925 #define RTW_TXSTAT_LS           RTW_TXCTL0_LS
  926 #define RTW_TXSTAT_RSVD1_MASK   BITS(27,16)
  927 #define RTW_TXSTAT_TOK          BIT(15)
  928 #define RTW_TXSTAT_RTSRETRY_MASK        BITS(14,8)      /* RTS retry count */
  929 #define RTW_TXSTAT_DRC_MASK             BITS(7,0)       /* Data retry count */
  930 
  931 #define RTW_TXCTL1_LENGEXT      BIT(31)         /* supplements _LENGTH
  932                                                  * in packets sent 5.5Mb/s or
  933                                                  * faster
  934                                                  */
  935 #define RTW_TXCTL1_LENGTH_MASK  BITS(30,16)     /* PLCP length (microseconds) */
  936 #define RTW_TXCTL1_RTSDUR_MASK  BITS(15,0)      /* RTS Duration
  937                                                  * (microseconds)
  938                                                  */
  939 
  940 #define RTW_TXLEN_LENGTH_MASK   BITS(11,0)      /* Tx buffer length in bytes */
  941 
  942 /* Rx descriptor */
  943 struct rtw_rxdesc {
  944     uint32_t    rd_ctl;
  945     uint32_t    rd_rsvd0;
  946     uint32_t    rd_buf;
  947     uint32_t    rd_rsvd1;
  948 };
  949 
  950 #define rd_stat rd_ctl
  951 #define rd_rssi rd_rsvd0
  952 #define rd_tsftl rd_buf         /* valid only when RTW_RXSTAT_LS is set */
  953 #define rd_tsfth rd_rsvd1       /* valid only when RTW_RXSTAT_LS is set */
  954 
  955 #define RTW_RXCTL_OWN           BIT(31)         /* 1: owned by NIC */
  956 #define RTW_RXCTL_EOR           BIT(30)         /* end of ring */
  957 #define RTW_RXCTL_FS            BIT(29)         /* first segment */
  958 #define RTW_RXCTL_LS            BIT(28)         /* last segment */
  959 #define RTW_RXCTL_RSVD0_MASK    BITS(29,12)     /* reserved */
  960 #define RTW_RXCTL_LENGTH_MASK   BITS(11,0)      /* Rx buffer length */
  961 
  962 #define RTW_RXSTAT_OWN          RTW_RXCTL_OWN
  963 #define RTW_RXSTAT_EOR          RTW_RXCTL_EOR
  964 #define RTW_RXSTAT_FS           RTW_RXCTL_FS    /* first segment */
  965 #define RTW_RXSTAT_LS           RTW_RXCTL_LS    /* last segment */
  966 #define RTW_RXSTAT_DMAFAIL      BIT(27)         /* DMA failure on this pkt */
  967 #define RTW_RXSTAT_BOVF         BIT(26)         /* buffer overflow XXX means
  968                                                  * FIFO exhausted?
  969                                                  */
  970 #define RTW_RXSTAT_SPLCP        BIT(25)         /* Rx'd with short preamble
  971                                                  * and PLCP header
  972                                                  */
  973 #define RTW_RXSTAT_RSVD1        BIT(24)         /* reserved */
  974 #define RTW_RXSTAT_RATE_MASK    BITS(23,20)     /* Rx rate */
  975 #define RTW_RXSTAT_RATE_1MBPS   LSHIFT(0, RTW_RXSTAT_RATE_MASK)
  976 #define RTW_RXSTAT_RATE_2MBPS   LSHIFT(1, RTW_RXSTAT_RATE_MASK)
  977 #define RTW_RXSTAT_RATE_5MBPS   LSHIFT(2, RTW_RXSTAT_RATE_MASK)
  978 #define RTW_RXSTAT_RATE_11MBPS  LSHIFT(3, RTW_RXSTAT_RATE_MASK)
  979 #define RTW_RXSTAT_MIC          BIT(19)         /* XXX from reference driver */
  980 #define RTW_RXSTAT_MAR          BIT(18)         /* is multicast */
  981 #define RTW_RXSTAT_PAR          BIT(17)         /* matches RTL8180's MAC */
  982 #define RTW_RXSTAT_BAR          BIT(16)         /* is broadcast */
  983 #define RTW_RXSTAT_RES          BIT(15)         /* error summary. valid when
  984                                                  * RTW_RXSTAT_LS set. indicates
  985                                                  * that either RTW_RXSTAT_CRC32
  986                                                  * or RTW_RXSTAT_ICV is set.
  987                                                  */
  988 #define RTW_RXSTAT_PWRMGT       BIT(14)         /* 802.11 PWRMGMT bit is set */
  989 #define RTW_RXSTAT_CRC16        BIT(14)         /* XXX CRC16 error, from
  990                                                  * reference driver
  991                                                  */
  992 #define RTW_RXSTAT_CRC32        BIT(13)         /* CRC32 error */
  993 #define RTW_RXSTAT_ICV          BIT(12)         /* ICV error */
  994 #define RTW_RXSTAT_LENGTH_MASK  BITS(11,0)      /* frame length, including
  995                                                  * CRC32
  996                                                  */
  997 
  998 /* Convenient status conjunction. */
  999 #define RTW_RXSTAT_ONESEG       (RTW_RXSTAT_FS|RTW_RXSTAT_LS)
 1000 /* Convenient status disjunctions. */
 1001 #define RTW_RXSTAT_IOERROR      (RTW_RXSTAT_DMAFAIL|RTW_RXSTAT_BOVF)
 1002 #define RTW_RXSTAT_DEBUG        (RTW_RXSTAT_SPLCP|RTW_RXSTAT_MAR|\
 1003                                  RTW_RXSTAT_PAR|RTW_RXSTAT_BAR|\
 1004                                  RTW_RXSTAT_PWRMGT|RTW_RXSTAT_CRC32|\
 1005                                  RTW_RXSTAT_ICV)
 1006 
 1007 
 1008 #define RTW_RXRSSI_VLAN         BITS(32,16)     /* XXX from reference driver */
 1009 /* for Philips RF front-ends */
 1010 #define RTW_RXRSSI_RSSI         BITS(15,8)      /* RF energy at the PHY */
 1011 /* for RF front-ends by Intersil, Maxim, RFMD */
 1012 #define RTW_RXRSSI_IMR_RSSI     BITS(15,9)      /* RF energy at the PHY */
 1013 #define RTW_RXRSSI_IMR_LNA      BIT(8)          /* 1: LNA activated */
 1014 #define RTW_RXRSSI_SQ           BITS(7,0)       /* Barker code-lock quality */
 1015 
 1016 #define RTW_READ8(regs, ofs)                                            \
 1017         bus_space_read_1((regs)->r_bt, (regs)->r_bh, (ofs))
 1018 
 1019 #define RTW_READ16(regs, ofs)                                           \
 1020         bus_space_read_2((regs)->r_bt, (regs)->r_bh, (ofs))
 1021 
 1022 #define RTW_READ(regs, ofs)                                             \
 1023         bus_space_read_4((regs)->r_bt, (regs)->r_bh, (ofs))
 1024 
 1025 #define RTW_WRITE8(regs, ofs, val)                                      \
 1026         bus_space_write_1((regs)->r_bt, (regs)->r_bh, (ofs), (val))
 1027 
 1028 #define RTW_WRITE16(regs, ofs, val)                                     \
 1029         bus_space_write_2((regs)->r_bt, (regs)->r_bh, (ofs), (val))
 1030 
 1031 #define RTW_WRITE(regs, ofs, val)                                       \
 1032         bus_space_write_4((regs)->r_bt, (regs)->r_bh, (ofs), (val))
 1033 
 1034 #define RTW_ISSET(regs, reg, mask)                                      \
 1035         (RTW_READ((regs), (reg)) & (mask))
 1036 
 1037 #define RTW_CLR(regs, reg, mask)                                        \
 1038         RTW_WRITE((regs), (reg), RTW_READ((regs), (reg)) & ~(mask))
 1039 
 1040 /* bus_space(9) lied? */
 1041 #ifndef BUS_SPACE_BARRIER_SYNC
 1042 #define BUS_SPACE_BARRIER_SYNC (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE)
 1043 #endif
 1044 
 1045 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_READ
 1046 #define BUS_SPACE_BARRIER_READ_BEFORE_READ BUS_SPACE_BARRIER_READ
 1047 #endif
 1048 
 1049 #ifndef BUS_SPACE_BARRIER_READ_BEFORE_WRITE
 1050 #define BUS_SPACE_BARRIER_READ_BEFORE_WRITE BUS_SPACE_BARRIER_READ
 1051 #endif
 1052 
 1053 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_READ
 1054 #define BUS_SPACE_BARRIER_WRITE_BEFORE_READ BUS_SPACE_BARRIER_WRITE
 1055 #endif
 1056 
 1057 #ifndef BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE
 1058 #define BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE BUS_SPACE_BARRIER_WRITE
 1059 #endif
 1060 
 1061 /*
 1062  * Bus barrier
 1063  *
 1064  * Complete outstanding read and/or write ops on [reg0, reg1]
 1065  * ([reg1, reg0]) before starting new ops on the same region. See
 1066  * acceptable bus_space_barrier(9) for the flag definitions.
 1067  */
 1068 #define RTW_BARRIER(regs, reg0, reg1, flags)                    \
 1069         bus_space_barrier((regs)->r_bh, (regs)->r_bt,           \
 1070             MIN(reg0, reg1), MAX(reg0, reg1) - MIN(reg0, reg1) + 4, flags)
 1071 
 1072 /*
 1073  * Barrier convenience macros.
 1074  */
 1075 /* sync */
 1076 #define RTW_SYNC(regs, reg0, reg1)                              \
 1077         RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_SYNC)
 1078 
 1079 /* write-before-write */
 1080 #define RTW_WBW(regs, reg0, reg1)                               \
 1081         RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
 1082 
 1083 /* write-before-read */
 1084 #define RTW_WBR(regs, reg0, reg1)                               \
 1085         RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_WRITE_BEFORE_READ)
 1086 
 1087 /* read-before-read */
 1088 #define RTW_RBR(regs, reg0, reg1)                               \
 1089         RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_READ)
 1090 
 1091 /* read-before-read */
 1092 #define RTW_RBW(regs, reg0, reg1)                               \
 1093         RTW_BARRIER(regs, reg0, reg1, BUS_SPACE_BARRIER_READ_BEFORE_WRITE)
 1094 
 1095 #define RTW_WBRW(regs, reg0, reg1)                              \
 1096                 RTW_BARRIER(regs, reg0, reg1,                   \
 1097                     BUS_SPACE_BARRIER_WRITE_BEFORE_READ |       \
 1098                     BUS_SPACE_BARRIER_WRITE_BEFORE_WRITE)
 1099 
 1100 /*
 1101  * Registers for RTL8180L's built-in baseband modem.
 1102  */
 1103 #define RTW_BBP_SYS1            0x00
 1104 #define RTW_BBP_TXAGC           0x03    /* guess: transmit auto gain control */
 1105 #define RTW_BBP_LNADET          0x04    /* guess: low-noise amplifier activation
 1106                                          * threshold
 1107                                          */
 1108 #define RTW_BBP_IFAGCINI        0x05    /* guess: intermediate frequency (IF)
 1109                                          * auto-gain control (AGC) initial value
 1110                                          */
 1111 #define RTW_BBP_IFAGCLIMIT      0x06    /* guess: IF AGC maximum value */
 1112 #define RTW_BBP_IFAGCDET        0x07    /* guess: activation threshold for
 1113                                          * IF AGC loop
 1114                                          */
 1115 
 1116 #define RTW_BBP_ANTATTEN        0x10    /* guess: antenna & attenuation */
 1117 #define RTW_BBP_ANTATTEN_PHILIPS_MAGIC          0x91
 1118 #define RTW_BBP_ANTATTEN_INTERSIL_MAGIC         0x92
 1119 #define RTW_BBP_ANTATTEN_RFMD_MAGIC             0x93
 1120 #define RTW_BBP_ANTATTEN_MAXIM_MAGIC            0xb3
 1121 #define RTW_BBP_ANTATTEN_DFLANTB                0x40
 1122 #define RTW_BBP_ANTATTEN_CHAN14                 0x0c
 1123 
 1124 #define RTW_BBP_TRL                     0x11    /* guess: transmit/receive
 1125                                                  * switch latency
 1126                                                  */
 1127 #define RTW_BBP_SYS2                    0x12
 1128 #define RTW_BBP_SYS2_ANTDIV             0x80    /* enable antenna diversity */
 1129 #define RTW_BBP_SYS2_RATE_MASK          BITS(5,4)       /* loopback rate?
 1130                                                          * 0: 1Mbps
 1131                                                          * 1: 2Mbps
 1132                                                          * 2: 5.5Mbps
 1133                                                          * 3: 11Mbps
 1134                                                          */
 1135 #define RTW_BBP_SYS3                    0x13
 1136 /* carrier-sense threshold */
 1137 #define RTW_BBP_SYS3_CSTHRESH_MASK      BITS(0,3)
 1138 #define RTW_BBP_CHESTLIM        0x19    /* guess: channel energy-detect
 1139                                          * threshold
 1140                                          */
 1141 #define RTW_BBP_CHSQLIM         0x1a    /* guess: channel signal-quality
 1142                                          * threshold
 1143                                          */

Cache object: 3f5d00db155228839a59a9aff612e721


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