Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/rtwvar.h
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1 /* $OpenBSD: rtwvar.h,v 1.31 2015/11/04 12:11:59 dlg Exp $ */ 2 /* $NetBSD: rtwvar.h,v 1.10 2004/12/26 22:37:57 mycroft Exp $ */ 3 4 /*- 5 * Copyright (c) 2004, 2005 David Young. All rights reserved. 6 * 7 * Driver for the Realtek RTL8180 802.11 MAC/BBP by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of David Young may not be used to endorse or promote 18 * products derived from this software without specific prior 19 * written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 23 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 24 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 25 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 26 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 27 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 * OF SUCH DAMAGE. 33 */ 34 35 #ifndef _DEV_IC_RTWVAR_H_ 36 #define _DEV_IC_RTWVAR_H_ 37 38 #include <sys/device.h> 39 #include <sys/queue.h> 40 #include <sys/timeout.h> 41 42 #ifdef RTW_DEBUG 43 #define RTW_DEBUG_TUNE 0x0000001 44 #define RTW_DEBUG_PKTFILT 0x0000002 45 #define RTW_DEBUG_XMIT 0x0000004 46 #define RTW_DEBUG_XMIT_DESC 0x0000008 47 #define RTW_DEBUG_NODE 0x0000010 48 #define RTW_DEBUG_PWR 0x0000020 49 #define RTW_DEBUG_ATTACH 0x0000040 50 #define RTW_DEBUG_REGDUMP 0x0000080 51 #define RTW_DEBUG_ACCESS 0x0000100 52 #define RTW_DEBUG_RESET 0x0000200 53 #define RTW_DEBUG_INIT 0x0000400 54 #define RTW_DEBUG_IOSTATE 0x0000800 55 #define RTW_DEBUG_RECV 0x0001000 56 #define RTW_DEBUG_RECV_DESC 0x0002000 57 #define RTW_DEBUG_IO_KICK 0x0004000 58 #define RTW_DEBUG_INTR 0x0008000 59 #define RTW_DEBUG_PHY 0x0010000 60 #define RTW_DEBUG_PHYIO 0x0020000 61 #define RTW_DEBUG_PHYBITIO 0x0040000 62 #define RTW_DEBUG_TIMEOUT 0x0080000 63 #define RTW_DEBUG_BUGS 0x0100000 64 #define RTW_DEBUG_BEACON 0x0200000 65 #define RTW_DEBUG_LED 0x0400000 66 #define RTW_DEBUG_KEY 0x0800000 67 #define RTW_DEBUG_XMIT_RSRC 0x1000000 68 #define RTW_DEBUG_OACTIVE 0x2000000 69 #define RTW_DEBUG_MAX 0x3ffffff 70 71 extern int rtw_debug; 72 #define RTW_DPRINTF(__flags, __x) \ 73 if ((rtw_debug & (__flags)) != 0) printf __x 74 #define DPRINTF(__sc, __flags, __x) \ 75 if (((__sc)->sc_ic.ic_if.if_flags & IFF_DEBUG) != 0) \ 76 RTW_DPRINTF(__flags, __x) 77 #else /* RTW_DEBUG */ 78 #define RTW_DPRINTF(__flags, __x) 79 #define DPRINTF(__sc, __flags, __x) 80 #endif /* RTW_DEBUG */ 81 82 #define KASSERT2(__cond, __msg) \ 83 do { \ 84 if (!(__cond)) \ 85 panic __msg ; \ 86 } while (0) 87 88 enum rtw_locale { 89 RTW_LOCALE_USA = 0, 90 RTW_LOCALE_EUROPE, 91 RTW_LOCALE_JAPAN, 92 RTW_LOCALE_UNKNOWN 93 }; 94 95 #define RTW_RFCHIPID_RESERVED 0x00 96 #define RTW_RFCHIPID_INTERSIL 0x01 97 #define RTW_RFCHIPID_RFMD2948 0x02 98 #define RTW_RFCHIPID_PHILIPS 0x03 99 #define RTW_RFCHIPID_MAXIM2820 0x04 100 #define RTW_RFCHIPID_GCT 0x05 101 #define RTW_RFCHIPID_RFMD2958 0x06 102 #define RTW_RFCHIPID_MAXIM2822 0x07 103 #define RTW_RFCHIPID_MAXIM2825 0x08 104 #define RTW_RFCHIPID_RTL8225 0x09 105 #define RTW_RFCHIPID_RTL8255 0x0a 106 107 /* sc_flags */ 108 #define RTW_F_ENABLED 0x00000001 /* chip is enabled */ 109 #define RTW_F_DIGPHY 0x00000002 /* digital PHY */ 110 #define RTW_F_DFLANTB 0x00000004 /* B antenna is default */ 111 #define RTW_F_RTL8185 0x00000008 /* RTL8185 or newer */ 112 #define RTW_F_ANTDIV 0x00000010 /* h/w antenna diversity */ 113 #define RTW_F_9356SROM 0x00000020 /* 93c56 SROM */ 114 #define RTW_F_SLEEP 0x00000040 /* chip is asleep */ 115 #define RTW_F_INVALID 0x00000080 /* chip is absent */ 116 /* all PHY flags */ 117 #define RTW_F_ALLPHY (RTW_F_DIGPHY|RTW_F_DFLANTB|RTW_F_ANTDIV) 118 119 enum rtw_access { 120 RTW_ACCESS_NONE = 0, 121 RTW_ACCESS_CONFIG = 1, 122 RTW_ACCESS_ANAPARM = 2 123 }; 124 125 struct rtw_regs { 126 bus_space_tag_t r_bt; 127 bus_space_handle_t r_bh; 128 enum rtw_access r_access; 129 void *r_priv; 130 131 /* bus independent I/O callbacks */ 132 u_int8_t (*r_read8)(void *, u_int32_t); 133 u_int16_t (*r_read16)(void *, u_int32_t); 134 u_int32_t (*r_read32)(void *, u_int32_t); 135 void (*r_write8)(void *, u_int32_t, u_int8_t); 136 void (*r_write16)(void *, u_int32_t, u_int16_t); 137 void (*r_write32)(void *, u_int32_t, u_int32_t); 138 void (*r_barrier)(void *, u_int32_t, u_int32_t, int); 139 }; 140 141 #define RTW_SR_GET(sr, ofs) \ 142 (((sr)->sr_content[(ofs)/2] >> (((ofs) % 2 == 0) ? 0 : 8)) & 0xff) 143 144 #define RTW_SR_GET16(sr, ofs) \ 145 (RTW_SR_GET((sr), (ofs)) | (RTW_SR_GET((sr), (ofs) + 1) << 8)) 146 147 struct rtw_srom { 148 u_int16_t *sr_content; 149 u_int16_t sr_size; 150 }; 151 152 struct rtw_rxsoft { 153 struct mbuf *rs_mbuf; 154 bus_dmamap_t rs_dmamap; 155 }; 156 157 struct rtw_duration { 158 uint16_t d_rts_dur; 159 uint16_t d_data_dur; 160 uint16_t d_plcp_len; 161 uint8_t d_residue; /* unused octets in time slot */ 162 }; 163 164 struct rtw_txsoft { 165 SIMPLEQ_ENTRY(rtw_txsoft) ts_q; 166 struct mbuf *ts_mbuf; 167 bus_dmamap_t ts_dmamap; 168 struct ieee80211_node *ts_ni; /* destination node */ 169 u_int ts_first; /* 1st hw descriptor */ 170 u_int ts_last; /* last hw descriptor */ 171 struct rtw_duration ts_d0; 172 struct rtw_duration ts_dn; 173 }; 174 175 #define RTW_NTXPRI 4 /* number of Tx priorities */ 176 #define RTW_TXPRILO 0 177 #define RTW_TXPRIMD 1 178 #define RTW_TXPRIHI 2 179 #define RTW_TXPRIBCN 3 /* beacon priority */ 180 181 #define RTW_MAXPKTSEGS 64 /* max 64 segments per Tx packet */ 182 183 /* Note well: the descriptor rings must begin on RTW_DESC_ALIGNMENT 184 * boundaries. I allocate them consecutively from one buffer, so 185 * just round up. 186 */ 187 #define RTW_TXQLENLO 64 /* low-priority queue length */ 188 #define RTW_TXQLENMD 64 /* medium-priority */ 189 #define RTW_TXQLENHI 64 /* high-priority */ 190 #define RTW_TXQLENBCN 8 /* beacon */ 191 192 #define RTW_NTXDESCLO RTW_TXQLENLO 193 #define RTW_NTXDESCMD RTW_TXQLENMD 194 #define RTW_NTXDESCHI RTW_TXQLENHI 195 #define RTW_NTXDESCBCN RTW_TXQLENBCN 196 197 #define RTW_NTXDESCTOTAL (RTW_NTXDESCLO + RTW_NTXDESCMD + \ 198 RTW_NTXDESCHI + RTW_NTXDESCBCN) 199 200 #define RTW_RXQLEN 64 201 202 struct rtw_rxdesc_blk { 203 struct rtw_rxdesc *rdb_desc; 204 u_int rdb_next; 205 u_int rdb_ndesc; 206 bus_dma_tag_t rdb_dmat; 207 bus_dmamap_t rdb_dmamap; 208 }; 209 210 struct rtw_txdesc_blk { 211 u_int tdb_ndesc; 212 u_int tdb_next; 213 u_int tdb_nfree; 214 bus_dma_tag_t tdb_dmat; 215 bus_dmamap_t tdb_dmamap; 216 bus_addr_t tdb_physbase; 217 bus_addr_t tdb_ofs; 218 bus_size_t tdb_basereg; 219 uint32_t tdb_base; 220 221 struct rtw_txdesc *tdb_desc; 222 }; 223 224 #define RTW_NEXT_IDX(__htc, __idx) (((__idx) + 1) % (__htc)->tdb_ndesc) 225 226 #define RTW_NEXT_DESC(__htc, __idx) \ 227 ((__htc)->tdb_physbase + \ 228 sizeof(struct rtw_txdesc) * RTW_NEXT_IDX((__htc), (__idx))) 229 230 SIMPLEQ_HEAD(rtw_txq, rtw_txsoft); 231 232 struct rtw_txsoft_blk { 233 /* dirty/free s/w descriptors */ 234 struct rtw_txq tsb_dirtyq; 235 struct rtw_txq tsb_freeq; 236 u_int tsb_ndesc; 237 int tsb_tx_timer; 238 struct rtw_txsoft *tsb_desc; 239 u_int8_t tsb_poll; 240 }; 241 242 struct rtw_descs { 243 struct rtw_txdesc hd_txlo[RTW_NTXDESCLO]; 244 struct rtw_txdesc hd_txmd[RTW_NTXDESCMD]; 245 struct rtw_txdesc hd_txhi[RTW_NTXDESCMD]; 246 struct rtw_rxdesc hd_rx[RTW_RXQLEN]; 247 struct rtw_txdesc hd_bcn[RTW_NTXDESCBCN]; 248 }; 249 #define RTW_DESC_OFFSET(ring, i) offsetof(struct rtw_descs, ring[i]) 250 #define RTW_RING_OFFSET(ring) RTW_DESC_OFFSET(ring, 0) 251 #define RTW_RING_BASE(sc, ring) ((sc)->sc_desc_physaddr + \ 252 RTW_RING_OFFSET(ring)) 253 254 /* Radio capture format for RTL8180. */ 255 256 #define RTW_RX_RADIOTAP_PRESENT \ 257 ((1 << IEEE80211_RADIOTAP_TSFT) | \ 258 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 259 (1 << IEEE80211_RADIOTAP_RATE) | \ 260 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 261 (1 << IEEE80211_RADIOTAP_LOCK_QUALITY) | \ 262 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ 263 0) 264 265 struct rtw_rx_radiotap_header { 266 struct ieee80211_radiotap_header rr_ihdr; 267 u_int64_t rr_tsft; 268 u_int8_t rr_flags; 269 u_int8_t rr_rate; 270 u_int16_t rr_chan_freq; 271 u_int16_t rr_chan_flags; 272 u_int16_t rr_barker_lock; 273 u_int8_t rr_antsignal; 274 } __packed; 275 276 #define RTW_TX_RADIOTAP_PRESENT \ 277 ((1 << IEEE80211_RADIOTAP_FLAGS) | \ 278 (1 << IEEE80211_RADIOTAP_RATE) | \ 279 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 280 0) 281 282 struct rtw_tx_radiotap_header { 283 struct ieee80211_radiotap_header rt_ihdr; 284 u_int8_t rt_flags; 285 u_int8_t rt_rate; 286 u_int16_t rt_chan_freq; 287 u_int16_t rt_chan_flags; 288 } __packed; 289 290 struct rtw_mtbl { 291 int (*mt_newstate)(struct ieee80211com *, 292 enum ieee80211_state, int); 293 void (*mt_recv_mgmt)(struct ieee80211com *, 294 struct mbuf *, struct ieee80211_node *, 295 struct ieee80211_rxinfo *, int); 296 struct ieee80211_node *(*mt_node_alloc)(struct ieee80211com *); 297 void (*mt_node_free)(struct ieee80211com *, 298 struct ieee80211_node *); 299 }; 300 301 enum rtw_pwrstate { RTW_OFF = 0, RTW_SLEEP, RTW_ON }; 302 303 struct rtw_phy { 304 struct rtw_rf *p_rf; 305 struct rtw_regs *p_regs; 306 }; 307 308 struct rtw_bbpset { 309 u_int bb_antatten; 310 u_int bb_chestlim; 311 u_int bb_chsqlim; 312 u_int bb_ifagcdet; 313 u_int bb_ifagcini; 314 u_int bb_ifagclimit; 315 u_int bb_lnadet; 316 u_int bb_sys1; 317 u_int bb_sys2; 318 u_int bb_sys3; 319 u_int bb_trl; 320 u_int bb_txagc; 321 }; 322 323 typedef int (*rtw_rf_write_t)(struct rtw_regs *, int, u_int, 324 u_int32_t); 325 326 typedef void (*rtw_pwrstate_t)(struct rtw_regs *, enum rtw_pwrstate, int, int); 327 328 union rtw_keys { 329 u_int8_t rk_keys[4][16]; 330 u_int32_t rk_words[16]; 331 }; 332 333 #define RTW_LED_SLOW_MSEC 500 334 #define RTW_LED_FAST_MSEC 100 335 336 struct rtw_led_state { 337 #define RTW_LED0 0x1 338 #define RTW_LED1 0x2 339 u_int8_t ls_slowblink:2; 340 u_int8_t ls_actblink:2; 341 u_int8_t ls_default:2; 342 u_int8_t ls_state; 343 u_int8_t ls_event; 344 #define RTW_LED_S_RX 0x1 345 #define RTW_LED_S_TX 0x2 346 #define RTW_LED_S_SLOW 0x4 347 struct timeout ls_slow_ch; 348 struct timeout ls_fast_ch; 349 }; 350 351 struct rtw_softc { 352 struct device sc_dev; 353 struct ieee80211com sc_ic; 354 struct rtw_regs sc_regs; 355 bus_dma_tag_t sc_dmat; 356 u_int32_t sc_flags; 357 358 int sc_rfchipid; 359 enum rtw_locale sc_locale; 360 u_int8_t sc_phydelay; 361 struct rtw_bbpset sc_bbpset; 362 363 /* s/w Tx/Rx descriptors */ 364 struct rtw_txsoft_blk sc_txsoft_blk[RTW_NTXPRI]; 365 struct rtw_txdesc_blk sc_txdesc_blk[RTW_NTXPRI]; 366 367 struct rtw_rxsoft sc_rxsoft[RTW_RXQLEN]; 368 struct rtw_rxdesc_blk sc_rxdesc_blk; 369 370 struct rtw_descs *sc_descs; 371 372 bus_dma_segment_t sc_desc_segs; 373 int sc_desc_nsegs; 374 bus_dmamap_t sc_desc_dmamap; 375 #define sc_desc_physaddr sc_desc_dmamap->dm_segs[0].ds_addr 376 377 struct rtw_srom sc_srom; 378 379 enum rtw_pwrstate sc_pwrstate; 380 381 rtw_pwrstate_t sc_pwrstate_cb; 382 383 u_int16_t sc_inten; 384 int (*sc_rf_init)(struct rtw_softc *, u_int, 385 u_int8_t, enum rtw_pwrstate); 386 int (*sc_rf_pwrstate)(struct rtw_softc *, 387 enum rtw_pwrstate); 388 int (*sc_rf_tune)(struct rtw_softc *, u_int); 389 int (*sc_rf_txpower)(struct rtw_softc *, u_int8_t); 390 391 /* interrupt acknowledge hook */ 392 void (*sc_intr_ack)(struct rtw_regs *); 393 394 int (*sc_enable)(struct rtw_softc *); 395 void (*sc_disable)(struct rtw_softc *); 396 void (*sc_power)(struct rtw_softc *, int); 397 struct rtw_mtbl sc_mtbl; 398 399 caddr_t sc_radiobpf; 400 401 struct timeval sc_last_beacon; 402 struct timeout sc_scan_to; 403 u_int sc_cur_chan; 404 405 u_int32_t sc_tsfth; /* most significant TSFT bits */ 406 u_int32_t sc_rcr; /* RTW_RCR */ 407 u_int8_t sc_csthr; /* carrier-sense threshold */ 408 409 int sc_do_tick; /* indicate 1s ticks */ 410 struct timeval sc_tick0; /* first tick */ 411 412 u_int8_t sc_rev; /* PCI/Cardbus revision */ 413 414 u_int32_t sc_anaparm[2]; /* RTW_ANAPARM_? registers */ 415 416 union { 417 struct rtw_rx_radiotap_header tap; 418 u_int8_t pad[64]; 419 } sc_rxtapu; 420 union { 421 struct rtw_tx_radiotap_header tap; 422 u_int8_t pad[64]; 423 } sc_txtapu; 424 union rtw_keys sc_keys; 425 int sc_txkey; 426 struct mbuf_queue sc_beaconq; 427 struct rtw_led_state sc_led_state; 428 u_int sc_hwverid; 429 }; 430 431 #define sc_if sc_ic.ic_if 432 #define sc_rxtap sc_rxtapu.tap 433 #define sc_txtap sc_txtapu.tap 434 435 extern int rtw_host_rfio; 436 437 void rtw_txdac_enable(struct rtw_softc *, int); 438 void rtw_anaparm_enable(struct rtw_regs *, int); 439 void rtw_config0123_enable(struct rtw_regs *, int); 440 void rtw_continuous_tx_enable(struct rtw_softc *, int); 441 void rtw_set_access(struct rtw_regs *, enum rtw_access); 442 443 void rtw_attach(struct rtw_softc *); 444 int rtw_detach(struct rtw_softc *); 445 int rtw_intr(void *); 446 447 void rtw_disable(struct rtw_softc *); 448 int rtw_enable(struct rtw_softc *); 449 450 int rtw_activate(struct device *, int); 451 void rtw_shutdown(void *); 452 453 const char *rtw_pwrstate_string(enum rtw_pwrstate); 454 455 #endif /* _DEV_IC_RTWVAR_H_ */
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