The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/sa2400reg.h

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    1 /* $NetBSD: sa2400reg.h,v 1.3 2005/02/27 00:27:02 perry Exp $ */
    2 
    3 /*
    4  * Copyright (c) 2005 David Young.  All rights reserved.
    5  *
    6  * This code was written by David Young.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
   21  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
   22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
   23  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
   24  * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
   25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
   26  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
   28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   29  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
   31  * OF SUCH DAMAGE.
   32  */
   33 
   34 #ifndef _DEV_IC_SA2400REG_H_
   35 #define _DEV_IC_SA2400REG_H_
   36 
   37 /*
   38  * Serial bus format for Philips SA2400 Single-chip Transceiver.
   39  */
   40 #define SA2400_TWI_DATA_MASK    BITS(31,8)
   41 #define SA2400_TWI_WREN         BIT(7)          /* enable write */
   42 #define SA2400_TWI_ADDR_MASK    BITS(6,0)
   43 
   44 /*
   45  * Registers for Philips SA2400 Single-chip Transceiver.
   46  */
   47 #define SA2400_SYNA             0               /* Synthesizer Register A */
   48 #define SA2400_SYNA_FM          BIT(21)         /* fractional modulus select,
   49                                                  * 0: /8 (default)
   50                                                  * 1: /5
   51                                                  */
   52 #define SA2400_SYNA_NF_MASK     BITS(20,18)     /* fractional increment value,
   53                                                  * 0 to 7, default 4
   54                                                  */
   55 #define SA2400_SYNA_N_MASK      BITS(17,2)      /* main divider division ratio,
   56                                                  * 512 to 65535, default 615
   57                                                  */
   58 
   59 #define SA2400_SYNB             1               /* Synthesizer Register B */
   60 #define SA2400_SYNB_R_MASK      BITS(21,12)     /* reference divider ratio,
   61                                                  * 4 to 1023, default 11
   62                                                  */
   63 #define SA2400_SYNB_L_MASK      BITS(11,10)     /* lock detect mode */
   64 #define SA2400_SYNB_L_INACTIVE0 LSHIFT(0, SA2400_SYNB_L_MASK)
   65 #define SA2400_SYNB_L_INACTIVE1 LSHIFT(1, SA2400_SYNB_L_MASK)
   66 #define SA2400_SYNB_L_NORMAL    LSHIFT(2, SA2400_SYNB_L_MASK)
   67 #define SA2400_SYNB_L_INACTIVE2 LSHIFT(3, SA2400_SYNB_L_MASK)
   68 
   69 #define SA2400_SYNB_ON          BIT(9)          /* power on/off,
   70                                                  * 0: inverted chip mode control
   71                                                  * 1: as defined by chip mode
   72                                                  *    (see SA2400_OPMODE)
   73                                                  */
   74 #define SA2400_SYNB_ONE         BIT(8)          /* always 1 */
   75 #define SA2400_SYNB_FC_MASK     BITS(7,0)       /* fractional compensation
   76                                                  * charge pump current DAC,
   77                                                  * 0 to 255, default 80.
   78                                                  */
   79 
   80 #define SA2400_SYNC             2               /* Synthesizer Register C */
   81 #define SA2400_SYNC_CP_MASK     BITS(7,6)       /* charge pump current
   82                                                  * setting
   83                                                  */
   84 #define SA2400_SYNC_CP_NORMAL_  LSHIFT(0, SA2400_SYNC_CP_MASK)
   85 #define SA2400_SYNC_CP_THIRD_   LSHIFT(1, SA2400_SYNC_CP_MASK)
   86 #define SA2400_SYNC_CP_NORMAL   LSHIFT(2, SA2400_SYNC_CP_MASK) /* recommended */
   87 #define SA2400_SYNC_CP_THIRD    LSHIFT(3, SA2400_SYNC_CP_MASK)
   88 
   89 #define SA2400_SYNC_SM_MASK     BITS(5,3)       /* comparison divider select,
   90                                                  * 0 to 4, extra division
   91                                                  * ratio is 2**SM.
   92                                                  */
   93 #define SA2400_SYNC_ZERO        BIT(2)          /* always 0 */
   94 
   95 #define SA2400_SYND             3               /* Synthesizer Register D */
   96 #define SA2400_SYND_ZERO1_MASK  BITS(21,17)     /* always 0 */
   97 #define SA2400_SYND_TPHPSU      BIT(16)         /* T[phpsu], 1: disable
   98                                                  * PHP speedup pump,
   99                                                  * overrides SA2400_SYND_TSPU
  100                                                  */
  101 #define SA2400_SYND_TPSU        BIT(15)         /* T[spu], 1: speedup on,
  102                                                  * 0: speedup off
  103                                                  */
  104 #define SA2400_SYND_ZERO2_MASK  BITS(14,3)      /* always 0 */
  105 
  106 #define SA2400_OPMODE           4               /* Operating mode, filter tuner,
  107                                                  * other controls
  108                                                  */
  109 #define SA2400_OPMODE_ADC       BIT(19) /* 1: in Rx mode, RSSI-ADC always on
  110                                          * 0: RSSI-ADC only on during AGC
  111                                          */
  112 #define SA2400_OPMODE_FTERR     BIT(18) /* read-only filter tuner error:
  113                                          * 1 if tuner out of range
  114                                          */
  115 /* Rx & Tx filter tuning, write tuning value (test mode only) or
  116  * read tuner setting (in normal mode).
  117  */
  118 #define SA2400_OPMODE_FILTTUNE_MASK     BITS(17,15)
  119 
  120 #define SA2400_OPMODE_V2P5      BIT(14) /* external reference voltage
  121                                          * (pad v2p5) on
  122                                          */
  123 #define SA2400_OPMODE_I1M       BIT(13) /* external reference current ... */
  124 #define SA2400_OPMODE_I0P3      BIT(12) /* external reference current ... */
  125 #define SA2400_OPMODE_IN22      BIT(10) /* xtal input frequency,
  126                                          * 0: 44 MHz
  127                                          * 1: 22 MHz
  128                                          */
  129 #define SA2400_OPMODE_CLK       BIT(9)  /* reference clock output on */
  130 #define SA2400_OPMODE_XO        BIT(8)  /* xtal oscillator on */
  131 #define SA2400_OPMODE_DIGIN     BIT(7)  /* use digital Tx inputs (FIRDAC) */
  132 #define SA2400_OPMODE_RXLV      BIT(6)  /* Rx output common mode voltage,
  133                                          * 0: V[DD]/2
  134                                          * 1: 1.25V
  135                                          */
  136 #define SA2400_OPMODE_VEO       BIT(5)  /* make internal vco
  137                                          * available at vco pads (vcoextout)
  138                                          */
  139 #define SA2400_OPMODE_VEI       BIT(4)  /* use external vco input (vcoextin) */
  140 /* main operating mode */
  141 #define SA2400_OPMODE_MODE_MASK         BITS(3,0)
  142 #define SA2400_OPMODE_MODE_SLEEP        LSHIFT(0, SA2400_OPMODE_MODE_MASK)
  143 #define SA2400_OPMODE_MODE_TXRX         LSHIFT(1, SA2400_OPMODE_MODE_MASK)
  144 #define SA2400_OPMODE_MODE_WAIT         LSHIFT(2, SA2400_OPMODE_MODE_MASK)
  145 #define SA2400_OPMODE_MODE_RXMGC        LSHIFT(3, SA2400_OPMODE_MODE_MASK)
  146 #define SA2400_OPMODE_MODE_FCALIB       LSHIFT(4, SA2400_OPMODE_MODE_MASK)
  147 #define SA2400_OPMODE_MODE_DCALIB       LSHIFT(5, SA2400_OPMODE_MODE_MASK)
  148 #define SA2400_OPMODE_MODE_FASTTXRXMGC  LSHIFT(6, SA2400_OPMODE_MODE_MASK)
  149 #define SA2400_OPMODE_MODE_RESET        LSHIFT(7, SA2400_OPMODE_MODE_MASK)
  150 #define SA2400_OPMODE_MODE_VCOCALIB     LSHIFT(8, SA2400_OPMODE_MODE_MASK)
  151 
  152 #define SA2400_OPMODE_DEFAULTS                                          \
  153         (SA2400_OPMODE_XO | SA2400_OPMODE_RXLV | SA2400_OPMODE_CLK |    \
  154          SA2400_OPMODE_I0P3 | LSHIFT(3, SA2400_OPMODE_FILTTUNE_MASK))
  155 
  156 #define SA2400_AGC              5               /* AGC adjustment */
  157 #define SA2400_AGC_TARGETSIGN   BIT(23)         /* fine-tune AGC target:
  158                                                  * -7dB to 7dB, sign bit ... */
  159 #define SA2400_AGC_TARGET_MASK  BITS(22,20)     /* ... plus 0dB - 7dB */
  160 #define SA2400_AGC_MAXGAIN_MASK BITS(19,15)     /* maximum AGC gain, 0 to 31,
  161                                                  * (yields 54dB to 85dB)
  162                                                  */
  163 /* write: settling time after baseband gain switching, units of
  164  *        182 nanoseconds.
  165  * read:  output of RSSI/Tx-peak detector's ADC in 5-bit Gray code.
  166  */
  167 #define SA2400_AGC_BBPDELAY_MASK        BITS(14,10)
  168 #define SA2400_AGC_ADCVAL_MASK          SA2400_AGC_BBPDELAY_MASK
  169 
  170 /* write: settling time after LNA gain switching, units of
  171  *        182 nanoseconds
  172  * read:  2nd sample of RSSI in AGC cycle
  173  */
  174 #define SA2400_AGC_LNADELAY_MASK        BITS(9,5)
  175 #define SA2400_AGC_SAMPLE2_MASK         SA2400_AGC_LNADELAY_MASK
  176 
  177 /* write: time between turning on Rx and AGCSET, units of
  178  *        182 nanoseconds
  179  * read:  1st sample of RSSI in AGC cycle
  180  */
  181 #define SA2400_AGC_RXONDELAY_MASK       BITS(4,0)
  182 #define SA2400_AGC_SAMPLE1_MASK         SA2400_AGC_RXONDELAY_MASK
  183 
  184 #define SA2400_MANRX            6       /* Manual receiver control settings */
  185 #define SA2400_MANRX_AHSN       BIT(23) /* 1: AGC w/ high S/N---switch LNA at
  186                                          *    step 52 (recommended)
  187                                          * 0: switch LNA at step 60
  188                                          */
  189 
  190 /* If _RXOSQON, Q offset is
  191  * (_RXOSQSIGN ? -1 : 1) * (1 + _RXOSQ_MASK) * 8 millivolts,
  192  * otherwise, Q offset is 0.
  193  *
  194  * Ditto I offset.
  195  */
  196 #define SA2400_MANRX_RXOSQON    BIT(22)         /* Rx Q-channel correction. */
  197 #define SA2400_MANRX_RXOSQSIGN  BIT(21)
  198 #define SA2400_MANRX_RXOSQ_MASK BITS(20,18)
  199 
  200 #define SA2400_MANRX_RXOSION    BIT(17)         /* Rx I-channel correction. */
  201 #define SA2400_MANRX_RXOSISIGN  BIT(16)
  202 #define SA2400_MANRX_RXOSI_MASK BITS(15,13)
  203 #define SA2400_MANRX_TEN        BIT(12)         /* use 10MHz offset cancellation
  204                                                  * cornerpoint for brief period
  205                                                  * after each gain change
  206                                                  */
  207 
  208 /* DC offset cancellation cornerpoint select
  209  * write: in RXMGC, set the cornerpoint
  210  * read:  in other modes, read AGC-controlled cornerpoint
  211  */
  212 #define SA2400_MANRX_CORNERFREQ_MASK    BITS(11,10)
  213 
  214 /* write: in RXMGC mode, sets receiver gain
  215  * read:  in other modes, read AGC-controlled gain
  216  */
  217 #define SA2400_MANRX_RXGAIN_MASK        BITS(9,0)
  218 
  219 #define SA2400_TX       7               /* Transmitter settings */
  220 /* Tx offsets
  221  *
  222  * write: in test mode, sets the offsets
  223  * read:  in normal mode, returns automatic settings
  224  */
  225 #define SA2400_TX_TXOSQON       BIT(19)
  226 #define SA2400_TX_TXOSQSIGN     BIT(18)
  227 #define SA2400_TX_TXOSQ_MASK    BITS(17,15)
  228 #define SA2400_TX_TXOSION       BIT(14)
  229 #define SA2400_TX_TXOSISIGN     BIT(13)
  230 #define SA2400_TX_TXOSI_MASK    BITS(12,10)
  231 
  232 #define SA2400_TX_RAMP_MASK     BITS(9,8)       /* Ramp-up delay,
  233                                                  * 0: 1us
  234                                                  * 1: 2us
  235                                                  * 2: 3us
  236                                                  * 3: 4us
  237                                                  * datasheet says, "ramp-up
  238                                                  * time always 1us". huh?
  239                                                  */
  240 #define SA2400_TX_HIGAIN_MASK   BITS(7,4)       /* Transmitter gain settings
  241                                                  * for TXHI output
  242                                                  */
  243 #define SA2400_TX_LOGAIN_MASK   BITS(3,0)       /* Transmitter gain settings
  244                                                  * for TXLO output
  245                                                  */
  246 
  247 #define SA2400_VCO      8                       /* VCO settings */
  248 #define SA2400_VCO_ZERO         BITS(6,5)       /* always zero */
  249 #define SA2400_VCO_VCERR        BIT(4)  /* VCO calibration error flag---no
  250                                          * band with low enough frequency
  251                                          * could be found
  252                                          */
  253 #define SA2400_VCO_VCOBAND_MASK BITS(3,0)       /* VCO band,
  254                                                  * write: in test mode, sets
  255                                                  *        VCO band
  256                                                  * read:  in normal mode,
  257                                                  *        the result of
  258                                                  *        calibration (VCOCAL).
  259                                                  *        0 = highest
  260                                                  *        frequencies
  261                                                  */
  262 #endif /* _DEV_IC_SA2400REG_H_ */

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