The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/sa2400reg.h

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    1 /* $NetBSD: sa2400reg.h,v 1.7 2006/08/31 19:24:38 dyoung Exp $ */
    2 
    3 /*
    4  * Copyright (c) 2005 David Young.  All rights reserved.
    5  *
    6  * This code was written by David Young.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. Neither the name of the author nor the names of any co-contributors
   17  *    may be used to endorse or promote products derived from this software
   18  *    without specific prior written permission.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY
   21  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
   22  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
   23  * PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL David
   24  * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
   25  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
   26  * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   27  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
   28  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
   29  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
   31  * OF SUCH DAMAGE.
   32  */
   33 
   34 #ifndef _DEV_IC_SA2400REG_H_
   35 #define _DEV_IC_SA2400REG_H_
   36 
   37 /*
   38  * Serial bus format for Philips SA2400 Single-chip Transceiver.
   39  */
   40 #define SA2400_TWI_DATA_MASK    __BITS(31,8)
   41 #define SA2400_TWI_WREN         __BIT(7)                /* enable write */
   42 #define SA2400_TWI_ADDR_MASK    __BITS(6,0)
   43 
   44 /*
   45  * Registers for Philips SA2400 Single-chip Transceiver.
   46  */
   47 #define SA2400_SYNA             0               /* Synthesizer Register A */
   48 #define SA2400_SYNA_FM          __BIT(21)       /* fractional modulus select,
   49                                                  * 0: /8 (default)
   50                                                  * 1: /5
   51                                                  */
   52 #define SA2400_SYNA_NF_MASK     __BITS(20,18)   /* fractional increment value,
   53                                                  * 0 to 7, default 4
   54                                                  */
   55 #define SA2400_SYNA_N_MASK      __BITS(17,2)    /* main divider division ratio,
   56                                                  * 512 to 65535, default 615
   57                                                  */
   58 
   59 #define SA2400_SYNB             1               /* Synthesizer Register B */
   60 #define SA2400_SYNB_R_MASK      __BITS(21,12)   /* reference divider ratio,
   61                                                  * 4 to 1023, default 11
   62                                                  */
   63 #define SA2400_SYNB_L_MASK      __BITS(11,10)   /* lock detect mode */
   64 #define SA2400_SYNB_L_INACTIVE0 __SHIFTIN(0, SA2400_SYNB_L_MASK)
   65 #define SA2400_SYNB_L_INACTIVE1 __SHIFTIN(1, SA2400_SYNB_L_MASK)
   66 #define SA2400_SYNB_L_NORMAL    __SHIFTIN(2, SA2400_SYNB_L_MASK)
   67 #define SA2400_SYNB_L_INACTIVE2 __SHIFTIN(3, SA2400_SYNB_L_MASK)
   68 
   69 #define SA2400_SYNB_ON          __BIT(9)        /* power on/off,
   70                                                  * 0: inverted chip mode control
   71                                                  * 1: as defined by chip mode
   72                                                  *    (see SA2400_OPMODE)
   73                                                  */
   74 #define SA2400_SYNB_ONE         __BIT(8)        /* always 1 */
   75 #define SA2400_SYNB_FC_MASK     __BITS(7,0)     /* fractional compensation
   76                                                  * charge pump current DAC,
   77                                                  * 0 to 255, default 80.
   78                                                  */
   79 
   80 #define SA2400_SYNC             2               /* Synthesizer Register C */
   81 #define SA2400_SYNC_CP_MASK     __BITS(7,6)     /* charge pump current
   82                                                  * setting
   83                                                  */
   84 #define SA2400_SYNC_CP_NORMAL_  __SHIFTIN(0, SA2400_SYNC_CP_MASK)
   85 #define SA2400_SYNC_CP_THIRD_   __SHIFTIN(1, SA2400_SYNC_CP_MASK)
   86 #define SA2400_SYNC_CP_NORMAL   __SHIFTIN(2, SA2400_SYNC_CP_MASK) /* recommended */
   87 #define SA2400_SYNC_CP_THIRD    __SHIFTIN(3, SA2400_SYNC_CP_MASK)
   88 
   89 #define SA2400_SYNC_SM_MASK     __BITS(5,3)     /* comparison divider select,
   90                                                  * 0 to 4, extra division
   91                                                  * ratio is 2**SM.
   92                                                  */
   93 #define SA2400_SYNC_ZERO        __BIT(2)        /* always 0 */
   94 
   95 #define SA2400_SYND             3               /* Synthesizer Register D */
   96 #define SA2400_SYND_ZERO1_MASK  __BITS(21,17)   /* always 0 */
   97 #define SA2400_SYND_TPHPSU      __BIT(16)       /* T[phpsu], 1: disable
   98                                                  * PHP speedup pump,
   99                                                  * overrides SA2400_SYND_TSPU
  100                                                  */
  101 #define SA2400_SYND_TPSU        __BIT(15)       /* T[spu], 1: speedup on,
  102                                                  * 0: speedup off
  103                                                  */
  104 #define SA2400_SYND_ZERO2_MASK  __BITS(14,3)    /* always 0 */
  105 
  106 #define SA2400_OPMODE           4               /* Operating mode, filter tuner,
  107                                                  * other controls
  108                                                  */
  109 /* 1: in Rx mode, RSSI-ADC always on 0: RSSI-ADC only on during AGC */
  110 #define SA2400_OPMODE_ADC       __BIT(19)
  111 /* read-only filter tuner error: 1 if tuner out of range */
  112 #define SA2400_OPMODE_FTERR     __BIT(18)
  113 /* Rx & Tx filter tuning, write tuning value (test mode only) or
  114  * read tuner setting (in normal mode).
  115  */
  116 #define SA2400_OPMODE_FILTTUNE_MASK     __BITS(17,15)
  117 
  118 /* external reference voltage (pad v2p5) on */
  119 #define SA2400_OPMODE_V2P5      __BIT(14)
  120 /* external reference current ... */
  121 #define SA2400_OPMODE_I1M       __BIT(13)
  122 /* external reference current ... */
  123 #define SA2400_OPMODE_I0P3      __BIT(12)
  124 #define SA2400_OPMODE_IN22      __BIT(10)       /* xtal input frequency,
  125                                                  * 0: 44 MHz
  126                                                  * 1: 22 MHz
  127                                                  */
  128 #define SA2400_OPMODE_CLK       __BIT(9)        /* reference clock output on */
  129 #define SA2400_OPMODE_XO        __BIT(8)        /* xtal oscillator on */
  130 #define SA2400_OPMODE_DIGIN     __BIT(7)        /* use digital Tx inputs
  131                                                  * (FIRDAC)
  132                                                  */
  133 #define SA2400_OPMODE_RXLV      __BIT(6)        /* Rx output common mode
  134                                                  * voltage,
  135                                                  * 0: V[DD]/2
  136                                                  * 1: 1.25V
  137                                                  */
  138 #define SA2400_OPMODE_VEO       __BIT(5)        /* make internal vco
  139                                                  * available at vco pads
  140                                                  * (vcoextout)
  141                                                  */
  142 #define SA2400_OPMODE_VEI       __BIT(4)        /* use external vco input
  143                                                  * (vcoextin)
  144                                                  */
  145 /* main operating mode */
  146 #define SA2400_OPMODE_MODE_MASK         __BITS(3,0)
  147 #define SA2400_OPMODE_MODE_SLEEP        __SHIFTIN(0, SA2400_OPMODE_MODE_MASK)
  148 #define SA2400_OPMODE_MODE_TXRX         __SHIFTIN(1, SA2400_OPMODE_MODE_MASK)
  149 #define SA2400_OPMODE_MODE_WAIT         __SHIFTIN(2, SA2400_OPMODE_MODE_MASK)
  150 #define SA2400_OPMODE_MODE_RXMGC        __SHIFTIN(3, SA2400_OPMODE_MODE_MASK)
  151 #define SA2400_OPMODE_MODE_FCALIB       __SHIFTIN(4, SA2400_OPMODE_MODE_MASK)
  152 #define SA2400_OPMODE_MODE_DCALIB       __SHIFTIN(5, SA2400_OPMODE_MODE_MASK)
  153 #define SA2400_OPMODE_MODE_FASTTXRXMGC  __SHIFTIN(6, SA2400_OPMODE_MODE_MASK)
  154 #define SA2400_OPMODE_MODE_RESET        __SHIFTIN(7, SA2400_OPMODE_MODE_MASK)
  155 #define SA2400_OPMODE_MODE_VCOCALIB     __SHIFTIN(8, SA2400_OPMODE_MODE_MASK)
  156 
  157 #define SA2400_OPMODE_DEFAULTS                                          \
  158         (SA2400_OPMODE_XO | SA2400_OPMODE_RXLV | SA2400_OPMODE_CLK |    \
  159          SA2400_OPMODE_I0P3 | __SHIFTIN(3, SA2400_OPMODE_FILTTUNE_MASK))
  160 
  161 #define SA2400_AGC              5               /* AGC adjustment */
  162 #define SA2400_AGC_TARGETSIGN   __BIT(23)       /* fine-tune AGC target:
  163                                                  * -7dB to 7dB, sign bit ... */
  164 #define SA2400_AGC_TARGET_MASK  __BITS(22,20)   /* ... plus 0dB - 7dB */
  165 #define SA2400_AGC_MAXGAIN_MASK __BITS(19,15)   /* maximum AGC gain, 0 to 31,
  166                                                  * (yields 54dB to 85dB)
  167                                                  */
  168 /* write: settling time after baseband gain switching, units of
  169  *        182 nanoseconds.
  170  * read:  output of RSSI/Tx-peak detector's ADC in 5-bit Gray code.
  171  */
  172 #define SA2400_AGC_BBPDELAY_MASK        __BITS(14,10)
  173 #define SA2400_AGC_ADCVAL_MASK          SA2400_AGC_BBPDELAY_MASK
  174 
  175 /* write: settling time after LNA gain switching, units of
  176  *        182 nanoseconds
  177  * read:  2nd sample of RSSI in AGC cycle
  178  */
  179 #define SA2400_AGC_LNADELAY_MASK        __BITS(9,5)
  180 #define SA2400_AGC_SAMPLE2_MASK         SA2400_AGC_LNADELAY_MASK
  181 
  182 /* write: time between turning on Rx and AGCSET, units of
  183  *        182 nanoseconds
  184  * read:  1st sample of RSSI in AGC cycle
  185  */
  186 #define SA2400_AGC_RXONDELAY_MASK       __BITS(4,0)
  187 #define SA2400_AGC_SAMPLE1_MASK         SA2400_AGC_RXONDELAY_MASK
  188 
  189 #define SA2400_MANRX            6       /* Manual receiver control settings */
  190 #define SA2400_MANRX_AHSN       __BIT(23)       /* 1: AGC w/ high S/N---switch
  191                                                  *    LNA at step 52
  192                                                  *    (recommended)
  193                                                  * 0: switch LNA at step 60
  194                                                  */
  195 
  196 /* If _RXOSQON, Q offset is
  197  * (_RXOSQSIGN ? -1 : 1) * (1 + _RXOSQ_MASK) * 8 millivolts,
  198  * otherwise, Q offset is 0.
  199  *
  200  * Ditto I offset.
  201  */
  202 #define SA2400_MANRX_RXOSQON    __BIT(22)       /* Rx Q-channel correction. */
  203 #define SA2400_MANRX_RXOSQSIGN  __BIT(21)
  204 #define SA2400_MANRX_RXOSQ_MASK __BITS(20,18)
  205 
  206 #define SA2400_MANRX_RXOSION    __BIT(17)       /* Rx I-channel correction. */
  207 #define SA2400_MANRX_RXOSISIGN  __BIT(16)
  208 #define SA2400_MANRX_RXOSI_MASK __BITS(15,13)
  209 #define SA2400_MANRX_TEN        __BIT(12)       /* use 10MHz offset cancellation
  210                                                  * cornerpoint for brief period
  211                                                  * after each gain change
  212                                                  */
  213 
  214 /* DC offset cancellation cornerpoint select
  215  * write: in RXMGC, set the cornerpoint
  216  * read:  in other modes, read AGC-controlled cornerpoint
  217  */
  218 #define SA2400_MANRX_CORNERFREQ_MASK    __BITS(11,10)
  219 
  220 /* write: in RXMGC mode, sets receiver gain
  221  * read:  in other modes, read AGC-controlled gain
  222  */
  223 #define SA2400_MANRX_RXGAIN_MASK        __BITS(9,0)
  224 
  225 #define SA2400_TX       7               /* Transmitter settings */
  226 /* Tx offsets
  227  *
  228  * write: in test mode, sets the offsets
  229  * read:  in normal mode, returns automatic settings
  230  */
  231 #define SA2400_TX_TXOSQON       __BIT(19)
  232 #define SA2400_TX_TXOSQSIGN     __BIT(18)
  233 #define SA2400_TX_TXOSQ_MASK    __BITS(17,15)
  234 #define SA2400_TX_TXOSION       __BIT(14)
  235 #define SA2400_TX_TXOSISIGN     __BIT(13)
  236 #define SA2400_TX_TXOSI_MASK    __BITS(12,10)
  237 
  238 #define SA2400_TX_RAMP_MASK     __BITS(9,8)     /* Ramp-up delay,
  239                                                  * 0: 1us
  240                                                  * 1: 2us
  241                                                  * 2: 3us
  242                                                  * 3: 4us
  243                                                  * datasheet says, "ramp-up
  244                                                  * time always 1us". huh?
  245                                                  */
  246 #define SA2400_TX_HIGAIN_MASK   __BITS(7,4)     /* Transmitter gain settings
  247                                                  * for TXHI output
  248                                                  */
  249 #define SA2400_TX_LOGAIN_MASK   __BITS(3,0)     /* Transmitter gain settings
  250                                                  * for TXLO output
  251                                                  */
  252 
  253 #define SA2400_VCO      8                       /* VCO settings */
  254 #define SA2400_VCO_ZERO         __BITS(6,5)     /* always zero */
  255 #define SA2400_VCO_VCERR        __BIT(4)/* VCO calibration error flag---no
  256                                          * band with low enough frequency
  257                                          * could be found
  258                                          */
  259 #define SA2400_VCO_VCOBAND_MASK __BITS(3,0)     /* VCO band,
  260                                                  * write: in test mode, sets
  261                                                  *        VCO band
  262                                                  * read:  in normal mode,
  263                                                  *        the result of
  264                                                  *        calibration (VCOCAL).
  265                                                  *        0 = highest
  266                                                  *        frequencies
  267                                                  */
  268 #endif /* _DEV_IC_SA2400REG_H_ */

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