Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/sa2400reg.h
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1 /* $OpenBSD: sa2400reg.h,v 1.2 2009/08/16 18:21:57 jsg Exp $ */ 2 /* $NetBSD: sa2400reg.h,v 1.2 2004/12/12 06:37:59 dyoung Exp $ */ 3 4 /* 5 * Copyright (c) 2005 David Young. All rights reserved. 6 * 7 * This code was written by David Young. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY David Young ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 23 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 24 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL David 25 * Young BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 26 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 27 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 29 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 * OF SUCH DAMAGE. 33 */ 34 35 #ifndef _DEV_IC_SA2400REG_H_ 36 #define _DEV_IC_SA2400REG_H_ 37 38 /* 39 * Serial bus format for Philips SA2400 Single-chip Transceiver. 40 */ 41 #define SA2400_TWI_DATA_MASK 0xffffff00 42 #define SA2400_TWI_WREN (1<<7) /* enable write */ 43 #define SA2400_TWI_ADDR_MASK 0x7f 44 45 /* 46 * Registers for Philips SA2400 Single-chip Transceiver. 47 */ 48 #define SA2400_SYNA 0 /* Synthesizer Register A */ 49 #define SA2400_SYNA_FM (1<<21) /* fractional modulus select, 50 * 0: /8 (default) 51 * 1: /5 52 */ 53 #define SA2400_SYNA_NF_MASK 0x1c0000 /* fractional increment value, 54 * 0 to 7, default 4 55 */ 56 #define SA2400_SYNA_N_MASK 0x3fffc /* main divider division ratio, 57 * 512 to 65535, default 615 58 */ 59 60 #define SA2400_SYNB 1 /* Synthesizer Register B */ 61 #define SA2400_SYNB_R_MASK 0x3ff000 /* reference divider ratio, 62 * 4 to 1023, default 11 63 */ 64 #define SA2400_SYNB_L_MASK 0xc00 /* lock detect mode */ 65 #define SA2400_SYNB_L_INACTIVE0 LSHIFT(0, SA2400_SYNB_L_MASK) 66 #define SA2400_SYNB_L_INACTIVE1 LSHIFT(1, SA2400_SYNB_L_MASK) 67 #define SA2400_SYNB_L_NORMAL LSHIFT(2, SA2400_SYNB_L_MASK) 68 #define SA2400_SYNB_L_INACTIVE2 LSHIFT(3, SA2400_SYNB_L_MASK) 69 70 #define SA2400_SYNB_ON (1<<9) /* power on/off, 71 * 0: inverted chip mode control 72 * 1: as defined by chip mode 73 * (see SA2400_OPMODE) 74 */ 75 #define SA2400_SYNB_ONE (1<<8) /* always 1 */ 76 #define SA2400_SYNB_FC_MASK 0xff /* fractional compensation 77 * charge pump current DAC, 78 * 0 to 255, default 80. 79 */ 80 81 #define SA2400_SYNC 2 /* Synthesizer Register C */ 82 #define SA2400_SYNC_CP_MASK 0xc0 /* charge pump current 83 * setting 84 */ 85 #define SA2400_SYNC_CP_NORMAL_ LSHIFT(0, SA2400_SYNC_CP_MASK) 86 #define SA2400_SYNC_CP_THIRD_ LSHIFT(1, SA2400_SYNC_CP_MASK) 87 #define SA2400_SYNC_CP_NORMAL LSHIFT(2, SA2400_SYNC_CP_MASK) /* recommended */ 88 #define SA2400_SYNC_CP_THIRD LSHIFT(3, SA2400_SYNC_CP_MASK) 89 90 #define SA2400_SYNC_SM_MASK 0x38 /* comparison divider select, 91 * 0 to 4, extra division 92 * ratio is 2**SM. 93 */ 94 #define SA2400_SYNC_ZERO (1<<2) /* always 0 */ 95 96 #define SA2400_SYND 3 /* Synthesizer Register D */ 97 #define SA2400_SYND_ZERO1_MASK 0x3e0000 /* always 0 */ 98 #define SA2400_SYND_TPHPSU (1<<16) /* T[phpsu], 1: disable 99 * PHP speedup pump, 100 * overrides SA2400_SYND_TSPU 101 */ 102 #define SA2400_SYND_TPSU (1<<15) /* T[spu], 1: speedup on, 103 * 0: speedup off 104 */ 105 #define SA2400_SYND_ZERO2_MASK 0x7ff8 /* always 0 */ 106 107 #define SA2400_OPMODE 4 /* Operating mode, filter tuner, 108 * other controls 109 */ 110 #define SA2400_OPMODE_ADC (1<<19) /* 1: in Rx mode, RSSI-ADC always on 111 * 0: RSSI-ADC only on during AGC 112 */ 113 #define SA2400_OPMODE_FTERR (1<<18) /* read-only filter tuner error: 114 * 1 if tuner out of range 115 */ 116 /* Rx & Tx filter tuning, write tuning value (test mode only) or 117 * read tuner setting (in normal mode). 118 */ 119 #define SA2400_OPMODE_FILTTUNE_MASK 0x38000 120 121 #define SA2400_OPMODE_V2P5 (1<<14) /* external reference voltage 122 * (pad v2p5) on 123 */ 124 #define SA2400_OPMODE_I1M (1<<13) /* external reference current ... */ 125 #define SA2400_OPMODE_I0P3 (1<<12) /* external reference current ... */ 126 #define SA2400_OPMODE_IN22 (1<<10) /* xtal input frequency, 127 * 0: 44 MHz 128 * 1: 22 MHz 129 */ 130 #define SA2400_OPMODE_CLK (1<<9) /* reference clock output on */ 131 #define SA2400_OPMODE_XO (1<<8) /* xtal oscillator on */ 132 #define SA2400_OPMODE_DIGIN (1<<7) /* use digital Tx inputs (FIRDAC) */ 133 #define SA2400_OPMODE_RXLV (1<<6) /* Rx output common mode voltage, 134 * 0: V[DD]/2 135 * 1: 1.25V 136 */ 137 #define SA2400_OPMODE_VEO (1<<5) /* make internal vco 138 * available at vco pads (vcoextout) 139 */ 140 #define SA2400_OPMODE_VEI (1<<4) /* use external vco input (vcoextin) */ 141 /* main operating mode */ 142 #define SA2400_OPMODE_MODE_MASK 0xf 143 #define SA2400_OPMODE_MODE_SLEEP LSHIFT(0, SA2400_OPMODE_MODE_MASK) 144 #define SA2400_OPMODE_MODE_TXRX LSHIFT(1, SA2400_OPMODE_MODE_MASK) 145 #define SA2400_OPMODE_MODE_WAIT LSHIFT(2, SA2400_OPMODE_MODE_MASK) 146 #define SA2400_OPMODE_MODE_RXMGC LSHIFT(3, SA2400_OPMODE_MODE_MASK) 147 #define SA2400_OPMODE_MODE_FCALIB LSHIFT(4, SA2400_OPMODE_MODE_MASK) 148 #define SA2400_OPMODE_MODE_DCALIB LSHIFT(5, SA2400_OPMODE_MODE_MASK) 149 #define SA2400_OPMODE_MODE_FASTTXRXMGC LSHIFT(6, SA2400_OPMODE_MODE_MASK) 150 #define SA2400_OPMODE_MODE_RESET LSHIFT(7, SA2400_OPMODE_MODE_MASK) 151 #define SA2400_OPMODE_MODE_VCOCALIB LSHIFT(8, SA2400_OPMODE_MODE_MASK) 152 153 #define SA2400_OPMODE_DEFAULTS \ 154 (SA2400_OPMODE_XO | SA2400_OPMODE_RXLV | SA2400_OPMODE_CLK | \ 155 SA2400_OPMODE_I0P3 | LSHIFT(3, SA2400_OPMODE_FILTTUNE_MASK)) 156 157 #define SA2400_AGC 5 /* AGC adjustment */ 158 #define SA2400_AGC_TARGETSIGN (1<<23) /* fine-tune AGC target: 159 * -7dB to 7dB, sign bit ... */ 160 #define SA2400_AGC_TARGET_MASK 0x700000 /* ... plus 0dB - 7dB */ 161 #define SA2400_AGC_MAXGAIN_MASK 0xf8000 /* maximum AGC gain, 0 to 31, 162 * (yields 54dB to 85dB) 163 */ 164 /* write: settling time after baseband gain switching, units of 165 * 182 nanoseconds. 166 * read: output of RSSI/Tx-peak detector's ADC in 5-bit Gray code. 167 */ 168 #define SA2400_AGC_BBPDELAY_MASK 0x7c00 169 #define SA2400_AGC_ADCVAL_MASK SA2400_AGC_BBPDELAY_MASK 170 171 /* write: settling time after LNA gain switching, units of 172 * 182 nanoseconds 173 * read: 2nd sample of RSSI in AGC cycle 174 */ 175 #define SA2400_AGC_LNADELAY_MASK 0x3e0 176 #define SA2400_AGC_SAMPLE2_MASK SA2400_AGC_LNADELAY_MASK 177 178 /* write: time between turning on Rx and AGCSET, units of 179 * 182 nanoseconds 180 * read: 1st sample of RSSI in AGC cycle 181 */ 182 #define SA2400_AGC_RXONDELAY_MASK 0x1f 183 #define SA2400_AGC_SAMPLE1_MASK SA2400_AGC_RXONDELAY_MASK 184 185 #define SA2400_MANRX 6 /* Manual receiver control settings */ 186 #define SA2400_MANRX_AHSN (1<<23) /* 1: AGC w/ high S/N---switch LNA at 187 * step 52 (recommended) 188 * 0: switch LNA at step 60 189 */ 190 191 /* If _RXOSQON, Q offset is 192 * (_RXOSQSIGN ? -1 : 1) * (1 + _RXOSQ_MASK) * 8 millivolts, 193 * otherwise, Q offset is 0. 194 * 195 * Ditto I offset. 196 */ 197 #define SA2400_MANRX_RXOSQON (1<<22) /* Rx Q-channel correction. */ 198 #define SA2400_MANRX_RXOSQSIGN (1<<21) 199 #define SA2400_MANRX_RXOSQ_MASK 0x1c0000 200 201 #define SA2400_MANRX_RXOSION (1<<17) /* Rx I-channel correction. */ 202 #define SA2400_MANRX_RXOSISIGN (1<<16) 203 #define SA2400_MANRX_RXOSI_MASK 0xe000 204 #define SA2400_MANRX_TEN (1<<12) /* use 10MHz offset cancellation 205 * cornerpoint for brief period 206 * after each gain change 207 */ 208 209 /* DC offset cancellation cornerpoint select 210 * write: in RXMGC, set the cornerpoint 211 * read: in other modes, read AGC-controlled cornerpoint 212 */ 213 #define SA2400_MANRX_CORNERFREQ_MASK 0xc00 214 215 /* write: in RXMGC mode, sets receiver gain 216 * read: in other modes, read AGC-controlled gain 217 */ 218 #define SA2400_MANRX_RXGAIN_MASK 0x3ff 219 220 #define SA2400_TX 7 /* Transmitter settings */ 221 /* Tx offsets 222 * 223 * write: in test mode, sets the offsets 224 * read: in normal mode, returns automatic settings 225 */ 226 #define SA2400_TX_TXOSQON (1<<19) 227 #define SA2400_TX_TXOSQSIGN (1<<18) 228 #define SA2400_TX_TXOSQ_MASK 0x38000 229 #define SA2400_TX_TXOSION (1<<14) 230 #define SA2400_TX_TXOSISIGN (1<<13) 231 #define SA2400_TX_TXOSI_MASK 0x1c00 232 233 #define SA2400_TX_RAMP_MASK 0x300 /* Ramp-up delay, 234 * 0: 1us 235 * 1: 2us 236 * 2: 3us 237 * 3: 4us 238 * datasheet says, "ramp-up 239 * time always 1us". huh? 240 */ 241 #define SA2400_TX_HIGAIN_MASK 0xf0 /* Transmitter gain settings 242 * for TXHI output 243 */ 244 #define SA2400_TX_LOGAIN_MASK 0xf /* Transmitter gain settings 245 * for TXLO output 246 */ 247 248 #define SA2400_VCO 8 /* VCO settings */ 249 #define SA2400_VCO_ZERO 0x60 /* always zero */ 250 #define SA2400_VCO_VCERR (1<<4) /* VCO calibration error flag---no 251 * band with low enough frequency 252 * could be found 253 */ 254 #define SA2400_VCO_VCOBAND_MASK 0xf /* VCO band, 255 * write: in test mode, sets 256 * VCO band 257 * read: in normal mode, 258 * the result of 259 * calibration (VCOCAL). 260 * 0 = highest 261 * frequencies 262 */ 263 #endif /* _DEV_IC_SA2400REG_H_ */
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