The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/sab82532.h

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*      $OpenBSD: sab82532reg.h,v 1.2 2002/04/08 17:49:42 jason Exp $   */
    2 
    3 /*-
    4  * Copyright (c) 2001 Jason L. Wright (jason@thought.net)
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  * 3. All advertising materials mentioning features or use of this software
   16  *    must display the following acknowledgement:
   17  *      This product includes software developed by Jason L. Wright
   18  * 4. The name of the author may not be used to endorse or promote products
   19  *    derived from this software without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   22  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
   24  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
   25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   29  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
   30  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   31  * POSSIBILITY OF SUCH DAMAGE.
   32  *
   33  * Effort sponsored in part by the Defense Advanced Research Projects
   34  * Agency (DARPA) and Air Force Research Laboratory, Air Force
   35  * Materiel Command, USAF, under agreement number F30602-01-2-0537.
   36  *
   37  * $FreeBSD: releng/6.3/sys/dev/ic/sab82532.h 139749 2005-01-06 01:43:34Z imp $
   38  */
   39 
   40 #ifndef _DEV_IC_SAB82532_H_
   41 #define _DEV_IC_SAB82532_H_
   42 
   43 /*
   44  * Register definitions for SAB82532 based on "Enhanced Serial Communication
   45  * Controller ESCC2 Version 3.2 User's Manual 07.96" from:
   46  * http://www.infineon.com
   47  */
   48 
   49 #define SAB_NCHAN       2       /* number of channels */
   50 #define SAB_CHANLEN     0x40    /* length of channel register set */
   51 
   52 #define SAB_CHAN_A      0x00    /* channel A register offset */
   53 #define SAB_CHAN_B      0x40    /* channel B register offset */
   54 
   55 #define SAB_RFIFO       0x00    /* r: rx fifo */
   56 #define SAB_XFIFO       0x00    /* w: tx fifo */
   57 #define SAB_STAR        0x20    /* r: status register */
   58 #define SAB_CMDR        0x20    /* w: command register */
   59 #define SAB_MODE        0x22    /* rw: mode register */
   60 #define SAB_TIMR        0x23    /* rw: timer register */
   61 #define SAB_XON         0x24    /* rw: xon character */
   62 #define SAB_XOFF        0x25    /* rw: xoff character */
   63 #define SAB_TCR         0x26    /* rw: termination character */
   64 #define SAB_DAFO        0x27    /* rw: data format */
   65 #define SAB_RFC         0x28    /* rw: rfifo control register */
   66 #define SAB_RBCL        0x2a    /* r: rx byte count low */
   67 #define SAB_TBCL        0x2a    /* w: tx byte count low */
   68 #define SAB_RBCH        0x2b    /* r: rx byte count high */
   69 #define SAB_XBCH        0x2b    /* w: tx byte count high */
   70 #define SAB_CCR0        0x2c    /* rw: channel configuration register 0 */
   71 #define SAB_CCR1        0x2d    /* rw: channel configuration register 1 */
   72 #define SAB_CCR2        0x2e    /* rw: channel configuration register 2 */
   73 #define SAB_CCR3        0x2f    /* rw: channel configuration register 3 */
   74 #define SAB_TSAX        0x30    /* w: time-slot assignment register tx */
   75 #define SAB_TSAR        0x31    /* w: time-slot assignment register rx */
   76 #define SAB_XCCR        0x32    /* w: tx channel capacity register */
   77 #define SAB_RCCR        0x33    /* w: receive channel capacity register */
   78 #define SAB_VSTR        0x34    /* r: version status */
   79 #define SAB_BGR         0x34    /* w: baud rate generator */
   80 #define SAB_TIC         0x35    /* w: transmit immediate character */
   81 #define SAB_MXN         0x36    /* w: mask xon character */
   82 #define SAB_MXF         0x37    /* w: mask xoff character */
   83 #define SAB_GIS         0x38    /* r: global interrupt status */
   84 #define SAB_IVA         0x38    /* w: interrupt vector address */
   85 #define SAB_IPC         0x39    /* rw: interrupt port configuration */
   86 #define SAB_ISR0        0x3a    /* r: interrupt status 0 */
   87 #define SAB_IMR0        0x3a    /* w: interrupt mask 0 */
   88 #define SAB_ISR1        0x3b    /* r: interrupt status 1 */
   89 #define SAB_IMR1        0x3b    /* w: interrupt mask 1 */
   90 #define SAB_PVR         0x3c    /* rw: port value register */
   91 #define SAB_PIS         0x3d    /* r: port interrupt status */
   92 #define SAB_PIM         0x3d    /* w: port interrupt mask */
   93 #define SAB_PCR         0x3e    /* w: port configuration register */
   94 #define SAB_CCR4        0x3f    /* rw: channel configuration register 4 */
   95 
   96 /* SAB_STAR: status register */
   97 #define SAB_STAR_XDOV   0x80    /* transmit data overflow */
   98 #define SAB_STAR_XFW    0x40    /* transmit fifo write enable */
   99 #define SAB_STAR_RFNE   0x20    /* rfifo not empty */
  100 #define SAB_STAR_FCS    0x10    /* flow control status */
  101 #define SAB_STAR_TEC    0x08    /* tx immediate char is executing */
  102 #define SAB_STAR_CEC    0x04    /* command is executing */
  103 #define SAB_STAR_CTS    0x02    /* cts status: 0:inactive/high,1:active/low */
  104 
  105 /* SAB_CMDR: command register */
  106 #define SAB_CMDR_RMC    0x80    /* receive message complete */
  107 #define SAB_CMDR_RRES   0x40    /* receiver reset */
  108 #define SAB_CMDR_RFRD   0x20    /* receive fifo read enable */
  109 #define SAB_CMDR_STI    0x10    /* start timer */
  110 #define SAB_CMDR_XF     0x08    /* transmit frame */
  111 #define SAB_CMDR_XRES   0x01    /* transmit reset */
  112 
  113 /* SAB_MODE: mode register */
  114 #define SAB_MODE_FRTS   0x40    /* flow control using rts */
  115 #define SAB_MODE_FCTS   0x20    /* flow control using cts */
  116 #define SAB_MODE_FLON   0x10    /* flow control on */
  117 #define SAB_MODE_RAC    0x08    /* receiver active */
  118 #define SAB_MODE_RTS    0x04    /* request to send */
  119 #define SAB_MODE_TRS    0x02    /* timer resolution */
  120 #define SAB_MODE_TLP    0x01    /* test loop */
  121 
  122 /* SAB_TIMR: timer register */
  123 #define SAB_TIMR_CNT    0xe0    /* count mask */
  124 #define SAB_TIMR_VAL    0x1f    /* value mask */
  125 
  126 /* SAB_DAFO: data format */
  127 #define SAB_DAFO_XBRK   0x40    /* transmit break */
  128 #define SAB_DAFO_STOP   0x20    /* stop bit: 0:1 bit, 1:2 bits */
  129 #define SAB_DAFO_PAR1   0x10    /* parity 1, see below */
  130 #define SAB_DAFO_PAR0   0x08    /* parity 0, see below */
  131 #define SAB_DAFO_PARE   0x04    /* parity enable */
  132 #define SAB_DAFO_CHL1   0x02    /* character length 1, see below */
  133 #define SAB_DAFO_CHL0   0x01    /* character length 0, see below */
  134 
  135 #define SAB_DAFO_CHL_CSIZE      (SAB_DAFO_CHL1|SAB_DAFO_CHL0)
  136 #define SAB_DAFO_CHL_CS5        (SAB_DAFO_CHL1|SAB_DAFO_CHL0)
  137 #define SAB_DAFO_CHL_CS6        (SAB_DAFO_CHL1)
  138 #define SAB_DAFO_CHL_CS7        (SAB_DAFO_CHL0)
  139 #define SAB_DAFO_CHL_CS8        (0)
  140 
  141 #define SAB_DAFO_PARMASK        (SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE)
  142 #define SAB_DAFO_PAR_MARK       (SAB_DAFO_PAR1|SAB_DAFO_PAR0|SAB_DAFO_PARE)
  143 #define SAB_DAFO_PAR_EVEN       (SAB_DAFO_PAR1|SAB_DAFO_PARE)
  144 #define SAB_DAFO_PAR_ODD        (SAB_DAFO_PAR0|SAB_DAFO_PARE)
  145 #define SAB_DAFO_PAR_SPACE      (SAB_DAFO_PARE)
  146 #define SAB_DAFO_PAR_NONE       (0)
  147 
  148 /* SAB_RFC: rfifo control register */
  149 #define SAB_RFC_DPS     0x40    /* disable parity storage */
  150 #define SAB_RFC_DXS     0x20    /* disable storage of xon/xoff characters */
  151 #define SAB_RFC_RFDF    0x10    /* rfifo data format: 0 data,1 data+stat */
  152 #define SAB_RFC_RFTH1   0x08    /* rfifo threshold level 1, see below */
  153 #define SAB_RFC_RFTH0   0x04    /* rfifo threshold level 0, see below */
  154 #define SAB_RFC_TCDE    0x01    /* termination character detection enable */
  155 
  156 #define SAB_RFC_RFTH_MASK       (SAB_RFC_RFTH1|SAB_RFC_RFTH0)
  157 #define SAB_RFC_RFTH_32CHAR     (SAB_RFC_RFTH1|SAB_RFC_RFTH0)
  158 #define SAB_RFC_RFTH_16CHAR     (SAB_RFC_RFTH1)
  159 #define SAB_RFC_RFTH_4CHAR      (SAB_RFC_RFTH0)
  160 #define SAB_RFC_RFTH_1CHAR      (0)
  161 
  162 /* SAB_RBCH: received byte count high */
  163 #define SAB_RBCH_DMA    0x80    /* read back of XBCH DMA bit */
  164 #define SAB_RBCH_CAS    0x20    /* read back of XBCH CAS bit */
  165 #define SAB_RBCH_CNT    0x0f    /* ms 4 bits of rx byte count (not used) */
  166 
  167 /* SAB_XBCH: transmit byte count high */
  168 #define SAB_XBCH_DMA    0x80    /* dma mode: 1:dma, 0:interrupt */
  169 #define SAB_XBCH_CAS    0x20    /* carrier detect auto-start */
  170 #define SAB_XBCH_XC     0x10    /* transmit continuously */
  171 #define SAB_XBCH_CNT    0x0f    /* ms 4 bits of tx byte count */
  172 
  173 /* SAB_CCR0: channel configuration register 0 */
  174 #define SAB_CCR0_PU     0x80    /* 0:power-down, 1:power-up */
  175 #define SAB_CCR0_MCE    0x40    /* master clock enable */
  176 #define SAB_CCR0_SC2    0x10    /* serial port config 2, see below */
  177 #define SAB_CCR0_SC1    0x08    /* serial port config 1, see below */
  178 #define SAB_CCR0_SC0    0x04    /* serial port config 0, see below */
  179 #define SAB_CCR0_SM1    0x02    /* serial mode 1, see below */
  180 #define SAB_CCR0_SM0    0x01    /* serial mode 0, see below */
  181 
  182 #define SAB_CCR0_SC_MASK        (SAB_CCR0_SC2|SAB_CCR0_SC1|SAB_CCR0_SC0)
  183 #define SAB_CCR0_SC_NRZ         (0)
  184 #define SAB_CCR0_SC_NRZI        (SAB_CCR0_SC1)
  185 #define SAB_CCR0_SC_FM0         (SAB_CCR0_SC2)
  186 #define SAB_CCR0_SC_FM1         (SAB_CCR0_SC2|SAB_CCR0_SC0)
  187 #define SAB_CCR0_SC_MANCHESTER  (SAB_CCR0_SC2|SAB_CCR0_SC1)
  188 
  189 #define SAB_CCR0_SM_MASK        (SAB_CCR0_SM1|SAB_CCR0_SM0)
  190 #define SAB_CCR0_SM_DLC         (0)
  191 #define SAB_CCR0_SM_DLCLOOP     (SAB_CCR0_SM0)
  192 #define SAB_CCR0_SM_BISYNC      (SAB_CCR0_SM1)
  193 #define SAB_CCR0_SM_ASYNC       (SAB_CCR0_SM1|SAB_CCR0_SM0)
  194 
  195 /* SAB_CCR1: channel configuration register 1 */
  196 #define SAB_CCR1_ODS    0x10    /* Output driver select:1:pushpull,0:odrain */
  197 #define SAB_CCR1_BCR    0x08    /* bit clock rate: 1:async, 0:isochronous */
  198 #define SAB_CCR1_CM2    0x04    /* clock mode 2, see below */
  199 #define SAB_CCR1_CM1    0x02    /* clock mode 1, see below */
  200 #define SAB_CCR1_CM0    0x01    /* clock mode 0, see below */
  201 
  202 #define SAB_CCR1_CM_MASK        (SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0)
  203 #define SAB_CCR1_CM_7           (SAB_CCR1_CM2|SAB_CCR1_CM1|SAB_CCR1_CM0)
  204 
  205 /* SAB_CCR2: channel configuration register 2, depends on clock mode above */
  206 /* clock mode 0a, 1, 4, 5 */
  207 #define SAB_CCR2_SOC1   0x80    /* special output 1, below */
  208 #define SAB_CCR2_SOC0   0x40    /* special output 0, below */
  209 #define SAB_CCR2_SOC_MASK       (SAB_CCR2_SOC1|SAB_CCR2_SOC0)
  210 #define SAB_CCR2_SOC_RTSHIGH    (SAB_CCR2_SOC1)
  211 #define SAB_CCR2_SOC_RTSNORM    (0)
  212 #define SAB_CCR2_SOC_RTSRX      (SAB_CCR2_SOC1|SAB_CCR2_SOC0)
  213 /* clock mode 0b, 2, 3, 6, 7 */
  214 #define SAB_CCR2_BR9    0x80    /* baud rate bit 9 */
  215 #define SAB_CCR2_BR8    0x40    /* baud rate bit 8 */
  216 #define SAB_CCR2_BDF    0x20    /* baud rate division factor: 0:1: 1:BRG */
  217 #define SAB_CCR2_SSEL   0x10    /* clock source select */
  218 /* clock mode 5 */
  219 #define SAB_CCR2_XCS0   0x20    /* tx clock shift, bit 0 */
  220 #define SAB_CCR2_RCS0   0x10    /* rx clock shift, bit 0 */
  221 /* clock mode 0b, 2, 3, 4, 5, 6, 7 */
  222 #define SAB_CCR2_TOE    0x08    /* tx clock output enable */
  223 /* clock mode 0a, 0b, 1, 2, 3, 4, 5, 6, 7 */
  224 #define SAB_CCR2_RWX    0x04    /* read/write exchange (dma mode only) */
  225 #define SAB_CCR2_DIV    0x01    /* data inversion (nrz) */
  226 
  227 /* SAB_CCR3: channel configuration register 3 (v2 or greater) */
  228 #define SAB_CCR3_PSD    0x01    /* dpll phase shift disable (nrz/nrzi) */
  229 
  230 /* SAB_TSAX: time-slot assignment register transmit (clock mode 5 only) */
  231 #define SAB_TSAX_TSNX   0xfc    /* time-slot number transmit */
  232 #define SAB_TSAX_XCS2   0x02    /* transmit clock shift bit 2 */
  233 #define SAB_TSAX_XCS1   0x01    /* transmit clock shift bit 1 */
  234 
  235 /* SAB_TSAR: time-slot assignment register receive (clock mode 5 only) */
  236 #define SAB_TSAR_TSNR   0xfc    /* time-slot number receive */
  237 #define SAB_TSAR_RCS2   0x02    /* receive clock shift bit 2 */
  238 #define SAB_TSAR_RCS1   0x01    /* receive clock shift bit 1 */
  239 
  240 /* SAB_VSTR: version status register */
  241 #define SAB_VSTR_CD     0x80    /* carrier detect status */
  242 #define SAB_VSTR_DPLA   0x40    /* dpll asynchronous */
  243 #define SAB_VSTR_VMASK  0x0f    /* chip version mask: */
  244 #define SAB_VSTR_V_1    0x00    /*   version 1 */
  245 #define SAB_VSTR_V_2    0x01    /*   version 2 */
  246 #define SAB_VSTR_V_32   0x02    /*   version 3.2 */
  247 
  248 /* SAB_GIS: global interrupt status register */
  249 #define SAB_GIS_PI      0x80    /* universal port interrupt */
  250 #define SAB_GIS_ISA1    0x08    /* interrupt status a1 */
  251 #define SAB_GIS_ISA0    0x04    /* interrupt status a0 */
  252 #define SAB_GIS_ISB1    0x02    /* interrupt status b1 */
  253 #define SAB_GIS_ISB0    0x01    /* interrupt status b0 */
  254 
  255 /* SAB_IVA: interrupt vector address */
  256 #define SAB_IVA_MASK    0xf8    /* interrupt vector address mask */
  257 
  258 /* SAB_IPC: interrupt port configuration */
  259 #define SAB_IPC_VIS     0x80    /* masked interrupt bits visible */
  260 #define SAB_IPC_SLAMASK 0x18    /* slave address mask */
  261 #define SAB_IPC_CASM    0x04    /* cascading mode */
  262 #define SAB_IPC_ICMASK  0x03    /* port config mask: */
  263 #define SAB_IPC_ICOD    0x00    /*   open drain output */
  264 #define SAB_IPC_ICPL    0x01    /*   push/pull active low output */
  265 #define SAB_IPC_ICPH    0x03    /*   push/pull active high output */
  266 
  267 /* SAB_ISR0: interrupt status 0 */
  268 #define SAB_ISR0_TCD    0x80    /* termination character detected */
  269 #define SAB_ISR0_TIME   0x40    /* time-out limit exceeded */
  270 #define SAB_ISR0_PERR   0x20    /* parity error */
  271 #define SAB_ISR0_FERR   0x10    /* framing error */
  272 #define SAB_ISR0_PLLA   0x08    /* dpll asynchronous */
  273 #define SAB_ISR0_CDSC   0x04    /* carrier detect status change */
  274 #define SAB_ISR0_RFO    0x02    /* rfifo overflow */
  275 #define SAB_ISR0_RPF    0x01    /* receive pool full */
  276 
  277 /* SAB_ISR1: interrupt status 1 */
  278 #define SAB_ISR1_BRK    0x80    /* break detected */
  279 #define SAB_ISR1_BRKT   0x40    /* break terminated */
  280 #define SAB_ISR1_ALLS   0x20    /* all sent */
  281 #define SAB_ISR1_XOFF   0x10    /* xoff detected */
  282 #define SAB_ISR1_TIN    0x08    /* timer interrupt */
  283 #define SAB_ISR1_CSC    0x04    /* clear to send status change */
  284 #define SAB_ISR1_XON    0x02    /* xon detected */
  285 #define SAB_ISR1_XPR    0x01    /* transmit pool ready */
  286 
  287 /* SAB_IMR0: interrupt mask 0 */
  288 #define SAB_IMR0_TCD    0x80    /* termination character detected */
  289 #define SAB_IMR0_TIME   0x40    /* time-out limit exceeded */
  290 #define SAB_IMR0_PERR   0x20    /* parity error */
  291 #define SAB_IMR0_FERR   0x10    /* framing error */
  292 #define SAB_IMR0_PLLA   0x08    /* dpll asynchronous */
  293 #define SAB_IMR0_CDSC   0x04    /* carrier detect status change */
  294 #define SAB_IMR0_RFO    0x02    /* rfifo overflow */
  295 #define SAB_IMR0_RPF    0x01    /* receive pool full */
  296 
  297 /* SAB_ISR1: interrupt mask 1 */
  298 #define SAB_IMR1_BRK    0x80    /* break detected */
  299 #define SAB_IMR1_BRKT   0x40    /* break terminated */
  300 #define SAB_IMR1_ALLS   0x20    /* all sent */
  301 #define SAB_IMR1_XDU    0x10    /* xoff detected */
  302 #define SAB_IMR1_TIN    0x08    /* timer interrupt */
  303 #define SAB_IMR1_CSC    0x04    /* clear to send status change */
  304 #define SAB_IMR1_XMR    0x02    /* xon detected */
  305 #define SAB_IMR1_XPR    0x01    /* transmit pool ready */
  306 
  307 /* SAB_PVR: port value register */
  308 #define SAB_PVR_DSR_A   0x01    /* port A DSR */
  309 #define SAB_PVR_DTR_A   0x02    /* port A DTR */
  310 #define SAB_PVR_DTR_B   0x04    /* port B DTR */
  311 #define SAB_PVR_DSR_B   0x08    /* port B DSR */
  312 #define SAB_PVR_MAGIC   0x10    /* dunno... */
  313 
  314 /* SAB_CCR4: channel configuration register 4 */
  315 #define SAB_CCR4_MCK4   0x80    /* master clock divide by 4 */
  316 #define SAB_CCR4_EBRG   0x40    /* enhanced baud rate generator mode */
  317 #define SAB_CCR4_TST1   0x20    /* test pin */
  318 #define SAB_CCR4_ICD    0x10    /* invert polarity of carrier detect */
  319 
  320 /* Receive status byte */
  321 #define SAB_RSTAT_PE    0x80    /* parity error */
  322 #define SAB_RSTAT_FE    0x40    /* framing error */
  323 #define SAB_RSTAT_PAR   0x01    /* parity bit */
  324 
  325 #endif /* _DEV_IC_SAB82532_H_ */

Cache object: 0dd93384867584f43360c033975dedfa


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.