The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/silireg.h

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    1 /*      $OpenBSD: silireg.h,v 1.22 2013/11/26 20:33:16 deraadt Exp $ */
    2 
    3 /*
    4  * Copyright (c) 2007 David Gwynne <dlg@openbsd.org>
    5  * Copyright (c) 2010 Conformal Systems LLC <info@conformal.com>
    6  * Copyright (c) 2010 Jonathan Matthew <jonathan@d14n.org>
    7  *
    8  * Permission to use, copy, modify, and distribute this software for any
    9  * purpose with or without fee is hereby granted, provided that the above
   10  * copyright notice and this permission notice appear in all copies.
   11  *
   12  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   13  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
   14  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
   15  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
   16  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
   17  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
   18  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
   19  */
   20 
   21 /* PCI Registers */
   22 #define SILI_PCI_BAR_GLOBAL     0x10 /* Global Registers address */
   23 #define SILI_PCI_BAR_PORT       0x18 /* Port Registers address */
   24 #define SILI_PCI_BAR_INDIRECT   0x20 /* Indirect IO Registers address */
   25 
   26 /* Global Registers */
   27 #define SILI_REG_PORT0_STATUS   0x00 /* Port 0 Slot Status */
   28 #define SILI_REG_PORT1_STATUS   0x04 /* Port 1 Slot Status */
   29 #define SILI_REG_PORT2_STATUS   0x08 /* Port 2 Slot Status */
   30 #define SILI_REG_PORT3_STATUS   0x0c /* Port 3 Slot Status */
   31 #define SILI_REG_GC             0x40 /* Global Control */
   32 #define  SILI_REG_GC_GR                 (1<<31) /* Global Reset */
   33 #define  SILI_REG_GC_MSIACK             (1<<30) /* MSI Acknowledge */
   34 #define  SILI_REG_GC_I2CINT             (1<<29) /* I2C Interrupt Enable */
   35 #define  SILI_REG_GC_PERRDIS            (1<<28) /* PCI Error Report Disable */
   36 #define  SILI_REG_GC_REQ64              (1<<20) /* latched PCI REQ64 */
   37 #define  SILI_REG_GC_DEVSEL             (1<<19) /* latched PCI DEVSEL */
   38 #define  SILI_REG_GC_STOP               (1<<18) /* latched PCI STOP */
   39 #define  SILI_REG_GC_TRDY               (1<<17) /* latched PCI TRDY */
   40 #define  SILI_REG_GC_M66EN              (1<<16) /* M66EN PCI bus signal */
   41 #define  SILI_REG_GC_PIE_MASK           0x0f
   42 #define SILI_FMT_GC             "\020" "\040GR" "\037MSIACK" "\036I2CINT" \
   43                                     "\035PERRDIS" "\025REQ64" "\024DEVSEL" \
   44                                     "\023STOP" "\022TRDY" "\021M66EN" \
   45                                     "\004P3IE" "\003P2IE" "\002P1IE" "\001P0IE"
   46 #define SILI_REG_GIS            0x44 /* Global Interrupt Status */
   47 #define  SILI_REG_GIS_I2C               (1 << 29)
   48 #define  SILI_REG_GIS_PIS_MASK          0x0f
   49 #define SILI_REG_PHYCONF        0x48 /* PHY Configuration */
   50 #define SILI_REG_BISTCTL        0x50 /* BIST Control */
   51 #define SILI_REG_BISTPATTERN    0x54 /* BIST Pattern */
   52 #define SILI_REG_BISTSTAT       0x58 /* BIST Status */
   53 #define SILI_REG_FLASHADDR      0x70 /* Flash Address */
   54 #define SILI_REG_FLASHDATA      0x74 /* Flash Memory Data / GPIO Control */
   55 #define SILI_REG_GPIOCTL        SILI_REG_FLASHDATA
   56 #define SILI_REG_IICADDR        0x78 /* I2C Address */
   57 #define SILI_REG_IIC            0x7c /* I2C Data / Control */
   58 
   59 #define SILI_PORT_SIZE          0x2000
   60 #define SILI_PORT_OFFSET(_p)    ((_p) * SILI_PORT_SIZE)
   61 
   62 /* Port Registers */
   63 #define SILI_PREG_LRAM          0x0000 /* Port LRAM */
   64 #define SILI_PREG_SLOT_WIDTH    0x80
   65 #define SILI_PREG_SLOT(_s)      (SILI_PREG_LRAM + (_s) * SILI_PREG_SLOT_WIDTH)
   66 #define SILI_PREG_RX_COUNT(_s)  (SILI_PREG_SLOT(_s) + 0x04)
   67 #define SILI_PREG_SIG_HI(_s)    (SILI_PREG_SLOT(_s) + 0x0c)
   68 #define SILI_PREG_SIG_HI_SHIFT  8
   69 #define SILI_PREG_SIG_LO(_s)    (SILI_PREG_SLOT(_s) + 0x14)
   70 #define SILI_PREG_SIG_LO_MASK   0xff
   71 
   72 #define SILI_PREG_PMP_BASE      0xF80   /* PMP Device Status/QActive Registers */
   73 #define SILI_PREG_PMP_STATUS(_p) (SILI_PREG_PMP_BASE + (_p * 8))
   74 #define SILI_PREG_PMP_QACTIVE(_p) (SILI_PREG_PMP_BASE + 4 + (_p * 8))
   75 #define  SILI_PREG_PMP_STATUS_PIO       0x000000FF
   76 #define  SILI_PREG_PMP_STATUS_ACTIVE    0x00000F00
   77 #define  SILI_PREG_PMP_STATUS_BUSY      (1 << 13)
   78 #define  SILI_PREG_PMP_STATUS_NCQ       (1 << 14)
   79 #define  SILI_PREG_PMP_STATUS_LEGACY_Q  (1 << 15)
   80 #define  SILI_PREG_PMP_STATUS_PENDING   (1 << 16)
   81 
   82 #define SILI_PREG_PCS           0x1000 /* Port Control Set / Status */
   83 #define  SILI_PREG_PCS_PORTRDY          (1<<31) /* Port Ready */
   84 #define  SILI_PREG_PCS_OOBB             (1<<25) /* OOB Bypass */
   85 #define  SILI_PREG_PCS_ACTIVE(_x)       (((_x)>>16) & 0x1f) /* Active Slot */
   86 #define  SILI_PREG_PCS_LED_ON           (1<<15) /* LED On */
   87 #define  SILI_PREG_PCS_AIA              (1<<14) /* Auto Interlock Accept */
   88 #define  SILI_PREG_PCS_PMEN             (1<<13) /* Port Mult Enable */
   89 #define  SILI_PREG_PCS_IA               (1<<12) /* Interlock Accept */
   90 #define  SILI_PREG_PCS_IR               (1<<11) /* Interlock Reject */
   91 #define  SILI_PREG_PCS_A32B             (1<<10) /* 32-bit Activation */
   92 #define  SILI_PREG_PCS_SD               (1<<9) /* Scrambler Disable */
   93 #define  SILI_PREG_PCS_CD               (1<<8) /* CONT Disable */
   94 #define  SILI_PREG_PCS_TB               (1<<7) /* Transmit BIST */
   95 #define  SILI_PREG_PCS_RESUME           (1<<6) /* Resume */
   96 #define  SILI_PREG_PCS_PLEN             (1<<5) /* Packet Length */
   97 #define  SILI_PREG_PCS_LEDDISABLE       (1<<4) /* LED Disable */
   98 #define  SILI_PREG_PCS_NOINTCLR         (1<<3) /* No Intr Clear on Read */
   99 #define  SILI_PREG_PCS_PORTINIT         (1<<2) /* Port Initialize */
  100 #define  SILI_PREG_PCS_DEVRESET         (1<<1) /* Device Reset */
  101 #define  SILI_PREG_PCS_PORTRESET        (1<<0) /* Port Reset */
  102 #define SILI_PFMT_PCS           "\020" "\032OOBB" "\020LED_ON" "\017AIA" \
  103                                     "\016PMEN" "\015IA" "\014IR" "\013A32B" \
  104                                     "\012SD" "\011CD" "\010TB" "\007RESUME" \
  105                                     "\006PLEN" "\005LEDDISABLE" \
  106                                     "\004NOINTCLR" "\003PORTINIT" \
  107                                     "\002PORTINIT" "\001PORTRESET"
  108 #define SILI_PREG_PCC           0x1004 /* Port Control Clear */
  109 #define  SILI_PREG_PCC_OOBB             (1<<25) /* OOB Bypass */
  110 #define  SILI_PREG_PCC_LED_ON           (1<<15) /* LED On */
  111 #define  SILI_PREG_PCC_AIA              (1<<14) /* Auto Interlock Accept */
  112 #define  SILI_PREG_PCC_PMEN             (1<<13) /* Port Mult Enable */
  113 #define  SILI_PREG_PCC_IA               (1<<12) /* Interlock Accept */
  114 #define  SILI_PREG_PCC_IR               (1<<11) /* Interlock Reject */
  115 #define  SILI_PREG_PCC_A32B             (1<<10) /* 32-bit Activation */
  116 #define  SILI_PREG_PCC_SD               (1<<9) /* Scrambler Disable */
  117 #define  SILI_PREG_PCC_CD               (1<<8) /* CONT Disable */
  118 #define  SILI_PREG_PCC_TB               (1<<7) /* Transmit BIST */
  119 #define  SILI_PREG_PCC_RESUME           (1<<6) /* Resume */
  120 #define  SILI_PREG_PCC_PLEN             (1<<5) /* Packet Length */
  121 #define  SILI_PREG_PCC_LEDDISABLE       (1<<4) /* LED Disable */
  122 #define  SILI_PREG_PCC_NOINTCLR         (1<<3) /* No Intr Clear on Read */
  123 #define  SILI_PREG_PCC_PORTINIT         (1<<2) /* Port Initialize */
  124 #define  SILI_PREG_PCC_DEVRESET         (1<<1) /* Device Reset */
  125 #define  SILI_PREG_PCC_PORTRESET        (1<<0) /* Port Reset */
  126 #define SILI_PREG_IS            0x1008 /* Interrupt Status */
  127 #define  SILI_PREG_IS_SDB               (1<<11) /* SDB Notify */
  128 #define  SILI_PREG_IS_HANDSHAKE         (1<<10) /* Handshake error threshold */
  129 #define  SILI_PREG_IS_CRC               (1<<9) /* CRC error threshold */
  130 #define  SILI_PREG_IS_DEC               (1<<8) /* 8b/10b decode error thresh */
  131 #define  SILI_PREG_IS_DEVXCHG           (1<<7) /* Device Exchanged */
  132 #define  SILI_PREG_IS_UNRECFIS          (1<<6) /* Unrecognized FIS Type */
  133 #define  SILI_PREG_IS_COMWAKE           (1<<5) /* ComWake */
  134 #define  SILI_PREG_IS_PHYRDYCHG         (1<<4) /* Phy Ready Change */
  135 #define  SILI_PREG_IS_PMCHG             (1<<3) /* Power Mmgt Change */
  136 #define  SILI_PREG_IS_PORTRDY           (1<<2) /* Port Ready */
  137 #define  SILI_PREG_IS_CMDERR            (1<<1) /* Command Error */
  138 #define  SILI_PREG_IS_CMDCOMP           (1<<0) /* Command Completion */
  139 #define SILI_PFMT_IS            "\020" "\014SDB" "\013HANDSHAKE" \
  140                                     "\012CRC" "\011DECODE" \
  141                                     "\010DEVXCHG" "\007UNRECFIS" \
  142                                     "\006COMWAKE" "\005PHYRDYCHG" \
  143                                     "\004PMCHG" "\003PORTRDY" \
  144                                     "\002CMDERR" "\001CMDCOMP"
  145 #define SILI_PREG_IES           0x1010 /* Interrupt Enable Set */
  146 #define SILI_PREG_IEC           0x1014 /* Interrupt Enable Clear */
  147 #define  SILI_PREG_IE_SDB               (1<<11) /* SDB Notify */
  148 #define  SILI_PREG_IE_DEVXCHG           (1<<7) /* Device Exchange */
  149 #define  SILI_PREG_IE_UNRECFIS          (1<<6) /* Unrecognized FIS Type */
  150 #define  SILI_PREG_IE_COMWAKE           (1<<5) /* ComWake */
  151 #define  SILI_PREG_IE_PHYRDYCHG         (1<<4) /* Phy Ready Change */
  152 #define  SILI_PREG_IE_PMCHG             (1<<3) /* Power Mmgt Change */
  153 #define  SILI_PREG_IE_PORTRDY           (1<<2) /* Port Ready */
  154 #define  SILI_PREG_IE_CMDERR            (1<<1) /* Command Error */
  155 #define  SILI_PREG_IE_CMDCOMP           (1<<0) /* Command Completion */
  156 #define  SILI_PREG_IE_ALL               0x08ff
  157 #define SILI_PREG_AUA           0x101c /* Activation Upper Address */
  158 #define SILI_PREG_FIFO          0x1020 /* Command Execution FIFO */
  159 #define SILI_PREG_CE            0x1024 /* Command Error */
  160 #define  SILI_PREG_CE_DEVICEERROR               1
  161 #define  SILI_PREG_CE_SDBERROR                  2
  162 #define  SILI_PREG_CE_DATAFISERROR              3
  163 #define SILI_PREG_FC            0x1028 /* FIS Configuration */
  164 #define SILI_PREG_RFT           0x102c /* Request FIFO Threshold */
  165 #define SILI_PREG_DEC           0x1040 /* 8b/10b Decode Error Counter */
  166 #define SILI_PREG_CEC           0x1044 /* CRC Error Counter */
  167 #define SILI_PREG_HEC           0x1048 /* Handshake Error Counter */
  168 #define SILI_PREG_PHYCONF       0x1050 /* Port PHY Configuration */
  169 #define SILI_PREG_PSS           0x1800 /* Port Slot Status */
  170 #define SILI_PREG_PSS_ATTENTION         (1U << 31)
  171 #define SILI_PREG_PSS_ALL_SLOTS         0x7fffffff
  172 #define SILI_PREG_CAR_LO(_s)    (0x1c00 + ((_s) * 0x8)) /* Cmd Activate Reg */
  173 #define SILI_PREG_CAR_HI(_s)    (0x1c00 + ((_s) * 0x8) + 0x4)
  174 #define SILI_PREG_CONTEXT       0x1e04 /* Port Context Register */
  175 #define  SILI_PREG_CONTEXT_SLOT_MASK    0x1F
  176 #define  SILI_PREG_CONTEXT_PMPORT_MASK  0x0F
  177 #define  SILI_PREG_CONTEXT_SLOT_SHIFT   0
  178 #define  SILI_PREG_CONTEXT_PMPORT_SHIFT 5
  179 #define SILI_PREG_SCTL          0x1f00 /* SControl */
  180 #define  SILI_PREG_SCTL_PMP             0x000F0000
  181 #define  SILI_PREG_SCTL_PMP_SHIFT       16
  182 #define SILI_PREG_SSTS          0x1f04 /* SStatus */
  183 #define SILI_PREG_SERR          0x1f08 /* SError */
  184 #define SILI_PREG_SACT          0x1f0c /* SActive */
  185 #define SILI_PREG_SNOT          0x1f10 /* SNotification */
  186 
  187 
  188 
  189 
  190 struct sili_sge {
  191         u_int32_t               addr_lo;
  192         u_int32_t               addr_hi;
  193         u_int32_t               data_count;
  194         u_int32_t               flags;
  195 #define SILI_SGE_TRM                    (1<<31)
  196 #define SILI_SGE_LNK                    (1<<30)
  197 #define SILI_SGE_DRD                    (1<<29)
  198 #define SILI_SGE_XCF                    (1<<28)
  199 } __packed;
  200 
  201 #define SILI_SGT_SGLLEN         4
  202 
  203 struct sili_sgt {
  204         struct sili_sge         sgl[SILI_SGT_SGLLEN];
  205 } __packed;
  206 
  207 #define SILI_PRB_PROTOCOL_OVERRIDE      (1<<0)
  208 #define SILI_PRB_RETRANSMIT             (1<<1)
  209 #define SILI_PRB_EXTERNAL_COMMAND       (1<<2)
  210 #define SILI_PRB_RECEIVE                (1<<3)
  211 #define SILI_PRB_PACKET_READ            (1<<4)
  212 #define SILI_PRB_PACKET_WRITE           (1<<5)
  213 #define SILI_PRB_INTERRUPT_MASK         (1<<6)
  214 #define SILI_PRB_SOFT_RESET             (1<<7)
  215 
  216 struct sili_prb { /* this is just a useful template */
  217         u_int16_t               control;
  218         u_int16_t               reserved1;
  219         u_int32_t               reserved2;
  220 
  221         u_int8_t                fis[ATA_FIS_LENGTH];
  222 
  223         u_int32_t               reserved3[9];
  224 } __packed;
  225 
  226 struct sili_prb_ata {
  227         u_int16_t               control;
  228         u_int16_t               protocol_override;
  229         u_int32_t               rx_count;
  230 
  231         u_int8_t                fis[ATA_FIS_LENGTH];
  232 
  233         u_int32_t               reserved;
  234 
  235         struct sili_sge         sgl[2];
  236 } __packed;
  237 
  238 struct sili_prb_packet {
  239         u_int16_t               control;
  240         u_int16_t               protocol_override;
  241         u_int32_t               rx_count;
  242 
  243         u_int8_t                fis[ATA_FIS_LENGTH];
  244 
  245         u_int32_t               reserved;
  246 
  247         u_int8_t                cdb[16];
  248 
  249         struct sili_sge         sgl[1];
  250 } __packed;
  251 
  252 struct sili_prb_softreset {
  253         u_int16_t               control;
  254         u_int16_t               reserved1;
  255         u_int32_t               reserved2;
  256 
  257         u_int8_t                fis[ATA_FIS_LENGTH];
  258 
  259         u_int32_t               reserved3[9];
  260 } __packed;
  261 
  262 #define SILI_MAX_CMDS           31
  263 #define SILI_PRB_LENGTH         64
  264 #define SILI_PRB_ALIGN          8
  265 #define SILI_SGT_LENGTH         64

Cache object: 9177ccee3a8d79676c938583e12e06bc


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