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sys/dev/ic/smc83c170.c
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1 /* $NetBSD: smc83c170.c,v 1.55 2003/11/08 16:08:13 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for the Standard Microsystems Corp. 83C170 42 * Ethernet PCI Integrated Controller (EPIC/100). 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.55 2003/11/08 16:08:13 tsutsui Exp $"); 47 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/callout.h> 53 #include <sys/mbuf.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/socket.h> 57 #include <sys/ioctl.h> 58 #include <sys/errno.h> 59 #include <sys/device.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/miivar.h> 76 #include <dev/mii/lxtphyreg.h> 77 78 #include <dev/ic/smc83c170reg.h> 79 #include <dev/ic/smc83c170var.h> 80 81 void epic_start __P((struct ifnet *)); 82 void epic_watchdog __P((struct ifnet *)); 83 int epic_ioctl __P((struct ifnet *, u_long, caddr_t)); 84 int epic_init __P((struct ifnet *)); 85 void epic_stop __P((struct ifnet *, int)); 86 87 void epic_shutdown __P((void *)); 88 89 void epic_reset __P((struct epic_softc *)); 90 void epic_rxdrain __P((struct epic_softc *)); 91 int epic_add_rxbuf __P((struct epic_softc *, int)); 92 void epic_read_eeprom __P((struct epic_softc *, int, int, u_int16_t *)); 93 void epic_set_mchash __P((struct epic_softc *)); 94 void epic_fixup_clock_source __P((struct epic_softc *)); 95 int epic_mii_read __P((struct device *, int, int)); 96 void epic_mii_write __P((struct device *, int, int, int)); 97 int epic_mii_wait __P((struct epic_softc *, u_int32_t)); 98 void epic_tick __P((void *)); 99 100 void epic_statchg __P((struct device *)); 101 int epic_mediachange __P((struct ifnet *)); 102 void epic_mediastatus __P((struct ifnet *, struct ifmediareq *)); 103 104 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 105 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 106 107 int epic_copy_small = 0; 108 109 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 110 111 /* 112 * Attach an EPIC interface to the system. 113 */ 114 void 115 epic_attach(sc) 116 struct epic_softc *sc; 117 { 118 bus_space_tag_t st = sc->sc_st; 119 bus_space_handle_t sh = sc->sc_sh; 120 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 121 int rseg, error, miiflags; 122 u_int i; 123 bus_dma_segment_t seg; 124 u_int8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 125 u_int16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 126 char *nullbuf; 127 128 callout_init(&sc->sc_mii_callout); 129 130 /* 131 * Allocate the control data structures, and create and load the 132 * DMA map for it. 133 */ 134 if ((error = bus_dmamem_alloc(sc->sc_dmat, 135 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 136 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 137 aprint_error( 138 "%s: unable to allocate control data, error = %d\n", 139 sc->sc_dev.dv_xname, error); 140 goto fail_0; 141 } 142 143 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 144 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 145 (caddr_t *)&sc->sc_control_data, 146 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 147 aprint_error("%s: unable to map control data, error = %d\n", 148 sc->sc_dev.dv_xname, error); 149 goto fail_1; 150 } 151 nullbuf = 152 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 153 memset(nullbuf, 0, ETHER_PAD_LEN); 154 155 if ((error = bus_dmamap_create(sc->sc_dmat, 156 sizeof(struct epic_control_data), 1, 157 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 158 &sc->sc_cddmamap)) != 0) { 159 aprint_error("%s: unable to create control data DMA map, " 160 "error = %d\n", sc->sc_dev.dv_xname, error); 161 goto fail_2; 162 } 163 164 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 165 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 166 BUS_DMA_NOWAIT)) != 0) { 167 aprint_error( 168 "%s: unable to load control data DMA map, error = %d\n", 169 sc->sc_dev.dv_xname, error); 170 goto fail_3; 171 } 172 173 /* 174 * Create the transmit buffer DMA maps. 175 */ 176 for (i = 0; i < EPIC_NTXDESC; i++) { 177 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 178 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 179 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 180 aprint_error("%s: unable to create tx DMA map %d, " 181 "error = %d\n", sc->sc_dev.dv_xname, i, error); 182 goto fail_4; 183 } 184 } 185 186 /* 187 * Create the receive buffer DMA maps. 188 */ 189 for (i = 0; i < EPIC_NRXDESC; i++) { 190 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 191 MCLBYTES, 0, BUS_DMA_NOWAIT, 192 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 193 aprint_error("%s: unable to create rx DMA map %d, " 194 "error = %d\n", sc->sc_dev.dv_xname, i, error); 195 goto fail_5; 196 } 197 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 198 } 199 200 /* 201 * create and map the pad buffer 202 */ 203 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 204 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 205 printf("%s: unable to create pad buffer DMA map, " 206 "error = %d\n", sc->sc_dev.dv_xname, error); 207 goto fail_5; 208 } 209 210 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 211 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 212 printf("%s: unable to load pad buffer DMA map, " 213 "error = %d\n", sc->sc_dev.dv_xname, error); 214 goto fail_6; 215 } 216 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 217 BUS_DMASYNC_PREWRITE); 218 219 /* 220 * Bring the chip out of low-power mode and reset it to a known state. 221 */ 222 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 223 epic_reset(sc); 224 225 /* 226 * Read the Ethernet address from the EEPROM. 227 */ 228 epic_read_eeprom(sc, 0, (sizeof(myea) / sizeof(myea[0])), myea); 229 for (i = 0; i < sizeof(myea)/ sizeof(myea[0]); i++) { 230 enaddr[i * 2] = myea[i] & 0xff; 231 enaddr[i * 2 + 1] = myea[i] >> 8; 232 } 233 234 /* 235 * ...and the device name. 236 */ 237 epic_read_eeprom(sc, 0x2c, (sizeof(mydevname) / sizeof(mydevname[0])), 238 mydevname); 239 for (i = 0; i < sizeof(mydevname) / sizeof(mydevname[0]); i++) { 240 devname[i * 2] = mydevname[i] & 0xff; 241 devname[i * 2 + 1] = mydevname[i] >> 8; 242 } 243 244 devname[sizeof(mydevname)] = '\0'; 245 for (i = sizeof(mydevname) - 1; i >= 0; i--) { 246 if (devname[i] == ' ') 247 devname[i] = '\0'; 248 else 249 break; 250 } 251 252 aprint_normal("%s: %s, Ethernet address %s\n", sc->sc_dev.dv_xname, 253 devname, ether_sprintf(enaddr)); 254 255 miiflags = 0; 256 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 257 miiflags |= MIIF_HAVEFIBER; 258 259 /* 260 * Initialize our media structures and probe the MII. 261 */ 262 sc->sc_mii.mii_ifp = ifp; 263 sc->sc_mii.mii_readreg = epic_mii_read; 264 sc->sc_mii.mii_writereg = epic_mii_write; 265 sc->sc_mii.mii_statchg = epic_statchg; 266 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epic_mediachange, 267 epic_mediastatus); 268 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 269 MII_OFFSET_ANY, miiflags); 270 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 271 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 272 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 273 } else 274 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 275 276 if (sc->sc_hwflags & EPIC_HAS_BNC) { 277 /* use the next free media instance */ 278 sc->sc_serinst = sc->sc_mii.mii_instance++; 279 ifmedia_add(&sc->sc_mii.mii_media, 280 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, 281 sc->sc_serinst), 282 0, NULL); 283 aprint_normal("%s: 10base2/BNC\n", sc->sc_dev.dv_xname); 284 } else 285 sc->sc_serinst = -1; 286 287 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 288 ifp->if_softc = sc; 289 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 290 ifp->if_ioctl = epic_ioctl; 291 ifp->if_start = epic_start; 292 ifp->if_watchdog = epic_watchdog; 293 ifp->if_init = epic_init; 294 ifp->if_stop = epic_stop; 295 IFQ_SET_READY(&ifp->if_snd); 296 297 /* 298 * We can support 802.1Q VLAN-sized frames. 299 */ 300 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 301 302 /* 303 * Attach the interface. 304 */ 305 if_attach(ifp); 306 ether_ifattach(ifp, enaddr); 307 308 /* 309 * Make sure the interface is shutdown during reboot. 310 */ 311 sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc); 312 if (sc->sc_sdhook == NULL) 313 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 314 sc->sc_dev.dv_xname); 315 return; 316 317 /* 318 * Free any resources we've allocated during the failed attach 319 * attempt. Do this in reverse order and fall through. 320 */ 321 fail_6: 322 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 323 fail_5: 324 for (i = 0; i < EPIC_NRXDESC; i++) { 325 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 326 bus_dmamap_destroy(sc->sc_dmat, 327 EPIC_DSRX(sc, i)->ds_dmamap); 328 } 329 fail_4: 330 for (i = 0; i < EPIC_NTXDESC; i++) { 331 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 332 bus_dmamap_destroy(sc->sc_dmat, 333 EPIC_DSTX(sc, i)->ds_dmamap); 334 } 335 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 336 fail_3: 337 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 338 fail_2: 339 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 340 sizeof(struct epic_control_data)); 341 fail_1: 342 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 343 fail_0: 344 return; 345 } 346 347 /* 348 * Shutdown hook. Make sure the interface is stopped at reboot. 349 */ 350 void 351 epic_shutdown(arg) 352 void *arg; 353 { 354 struct epic_softc *sc = arg; 355 356 epic_stop(&sc->sc_ethercom.ec_if, 1); 357 } 358 359 /* 360 * Start packet transmission on the interface. 361 * [ifnet interface function] 362 */ 363 void 364 epic_start(ifp) 365 struct ifnet *ifp; 366 { 367 struct epic_softc *sc = ifp->if_softc; 368 struct mbuf *m0, *m; 369 struct epic_txdesc *txd; 370 struct epic_descsoft *ds; 371 struct epic_fraglist *fr; 372 bus_dmamap_t dmamap; 373 int error, firsttx, nexttx, opending, seg; 374 u_int len; 375 376 /* 377 * Remember the previous txpending and the first transmit 378 * descriptor we use. 379 */ 380 opending = sc->sc_txpending; 381 firsttx = EPIC_NEXTTX(sc->sc_txlast); 382 383 /* 384 * Loop through the send queue, setting up transmit descriptors 385 * until we drain the queue, or use up all available transmit 386 * descriptors. 387 */ 388 while (sc->sc_txpending < EPIC_NTXDESC) { 389 /* 390 * Grab a packet off the queue. 391 */ 392 IFQ_POLL(&ifp->if_snd, m0); 393 if (m0 == NULL) 394 break; 395 m = NULL; 396 397 /* 398 * Get the last and next available transmit descriptor. 399 */ 400 nexttx = EPIC_NEXTTX(sc->sc_txlast); 401 txd = EPIC_CDTX(sc, nexttx); 402 fr = EPIC_CDFL(sc, nexttx); 403 ds = EPIC_DSTX(sc, nexttx); 404 dmamap = ds->ds_dmamap; 405 406 /* 407 * Load the DMA map. If this fails, the packet either 408 * didn't fit in the alloted number of frags, or we were 409 * short on resources. In this case, we'll copy and try 410 * again. 411 */ 412 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 413 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 414 (m0->m_pkthdr.len < ETHER_PAD_LEN && 415 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 416 if (error == 0) 417 bus_dmamap_unload(sc->sc_dmat, dmamap); 418 419 MGETHDR(m, M_DONTWAIT, MT_DATA); 420 if (m == NULL) { 421 printf("%s: unable to allocate Tx mbuf\n", 422 sc->sc_dev.dv_xname); 423 break; 424 } 425 if (m0->m_pkthdr.len > MHLEN) { 426 MCLGET(m, M_DONTWAIT); 427 if ((m->m_flags & M_EXT) == 0) { 428 printf("%s: unable to allocate Tx " 429 "cluster\n", sc->sc_dev.dv_xname); 430 m_freem(m); 431 break; 432 } 433 } 434 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 435 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 436 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 437 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 438 if (error) { 439 printf("%s: unable to load Tx buffer, " 440 "error = %d\n", sc->sc_dev.dv_xname, error); 441 break; 442 } 443 } 444 IFQ_DEQUEUE(&ifp->if_snd, m0); 445 if (m != NULL) { 446 m_freem(m0); 447 m0 = m; 448 } 449 450 /* Initialize the fraglist. */ 451 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 452 fr->ef_frags[seg].ef_addr = 453 dmamap->dm_segs[seg].ds_addr; 454 fr->ef_frags[seg].ef_length = 455 dmamap->dm_segs[seg].ds_len; 456 } 457 len = m0->m_pkthdr.len; 458 if (len < ETHER_PAD_LEN) { 459 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 460 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 461 len = ETHER_PAD_LEN; 462 seg++; 463 } 464 fr->ef_nfrags = seg; 465 466 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 467 468 /* Sync the DMA map. */ 469 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 470 BUS_DMASYNC_PREWRITE); 471 472 /* 473 * Store a pointer to the packet so we can free it later. 474 */ 475 ds->ds_mbuf = m0; 476 477 /* 478 * Fill in the transmit descriptor. 479 */ 480 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 481 482 /* 483 * If this is the first descriptor we're enqueueing, 484 * don't give it to the EPIC yet. That could cause 485 * a race condition. We'll do it below. 486 */ 487 if (nexttx == firsttx) 488 txd->et_txstatus = TXSTAT_TXLENGTH(len); 489 else 490 txd->et_txstatus = 491 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 492 493 EPIC_CDTXSYNC(sc, nexttx, 494 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 495 496 /* Advance the tx pointer. */ 497 sc->sc_txpending++; 498 sc->sc_txlast = nexttx; 499 500 #if NBPFILTER > 0 501 /* 502 * Pass the packet to any BPF listeners. 503 */ 504 if (ifp->if_bpf) 505 bpf_mtap(ifp->if_bpf, m0); 506 #endif 507 } 508 509 if (sc->sc_txpending == EPIC_NTXDESC) { 510 /* No more slots left; notify upper layer. */ 511 ifp->if_flags |= IFF_OACTIVE; 512 } 513 514 if (sc->sc_txpending != opending) { 515 /* 516 * We enqueued packets. If the transmitter was idle, 517 * reset the txdirty pointer. 518 */ 519 if (opending == 0) 520 sc->sc_txdirty = firsttx; 521 522 /* 523 * Cause a transmit interrupt to happen on the 524 * last packet we enqueued. 525 */ 526 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 527 EPIC_CDTXSYNC(sc, sc->sc_txlast, 528 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 529 530 /* 531 * The entire packet chain is set up. Give the 532 * first descriptor to the EPIC now. 533 */ 534 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 535 EPIC_CDTXSYNC(sc, firsttx, 536 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 537 538 /* Start the transmitter. */ 539 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 540 COMMAND_TXQUEUED); 541 542 /* Set a watchdog timer in case the chip flakes out. */ 543 ifp->if_timer = 5; 544 } 545 } 546 547 /* 548 * Watchdog timer handler. 549 * [ifnet interface function] 550 */ 551 void 552 epic_watchdog(ifp) 553 struct ifnet *ifp; 554 { 555 struct epic_softc *sc = ifp->if_softc; 556 557 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 558 ifp->if_oerrors++; 559 560 (void) epic_init(ifp); 561 } 562 563 /* 564 * Handle control requests from the operator. 565 * [ifnet interface function] 566 */ 567 int 568 epic_ioctl(ifp, cmd, data) 569 struct ifnet *ifp; 570 u_long cmd; 571 caddr_t data; 572 { 573 struct epic_softc *sc = ifp->if_softc; 574 struct ifreq *ifr = (struct ifreq *)data; 575 int s, error; 576 577 s = splnet(); 578 579 switch (cmd) { 580 case SIOCSIFMEDIA: 581 case SIOCGIFMEDIA: 582 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 583 break; 584 585 default: 586 error = ether_ioctl(ifp, cmd, data); 587 if (error == ENETRESET) { 588 /* 589 * Multicast list has changed; set the hardware filter 590 * accordingly. Update our idea of the current media; 591 * epic_set_mchash() needs to know what it is. 592 */ 593 mii_pollstat(&sc->sc_mii); 594 epic_set_mchash(sc); 595 error = 0; 596 } 597 break; 598 } 599 600 splx(s); 601 return (error); 602 } 603 604 /* 605 * Interrupt handler. 606 */ 607 int 608 epic_intr(arg) 609 void *arg; 610 { 611 struct epic_softc *sc = arg; 612 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 613 struct epic_rxdesc *rxd; 614 struct epic_txdesc *txd; 615 struct epic_descsoft *ds; 616 struct mbuf *m; 617 u_int32_t intstat, rxstatus, txstatus; 618 int i, claimed = 0; 619 u_int len; 620 621 top: 622 /* 623 * Get the interrupt status from the EPIC. 624 */ 625 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 626 if ((intstat & INTSTAT_INT_ACTV) == 0) 627 return (claimed); 628 629 claimed = 1; 630 631 /* 632 * Acknowledge the interrupt. 633 */ 634 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 635 intstat & INTMASK); 636 637 /* 638 * Check for receive interrupts. 639 */ 640 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 641 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 642 rxd = EPIC_CDRX(sc, i); 643 ds = EPIC_DSRX(sc, i); 644 645 EPIC_CDRXSYNC(sc, i, 646 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 647 648 rxstatus = rxd->er_rxstatus; 649 if (rxstatus & ER_RXSTAT_OWNER) { 650 /* 651 * We have processed all of the 652 * receive buffers. 653 */ 654 break; 655 } 656 657 /* 658 * Make sure the packet arrived intact. If an error 659 * occurred, update stats and reset the descriptor. 660 * The buffer will be reused the next time the 661 * descriptor comes up in the ring. 662 */ 663 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 664 if (rxstatus & ER_RXSTAT_CRCERROR) 665 printf("%s: CRC error\n", 666 sc->sc_dev.dv_xname); 667 if (rxstatus & ER_RXSTAT_ALIGNERROR) 668 printf("%s: alignment error\n", 669 sc->sc_dev.dv_xname); 670 ifp->if_ierrors++; 671 EPIC_INIT_RXDESC(sc, i); 672 continue; 673 } 674 675 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 676 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 677 678 /* 679 * The EPIC includes the CRC with every packet. 680 */ 681 len = RXSTAT_RXLENGTH(rxstatus); 682 683 if (len < sizeof(struct ether_header)) { 684 /* 685 * Runt packet; drop it now. 686 */ 687 ifp->if_ierrors++; 688 EPIC_INIT_RXDESC(sc, i); 689 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 690 ds->ds_dmamap->dm_mapsize, 691 BUS_DMASYNC_PREREAD); 692 continue; 693 } 694 695 /* 696 * If the packet is small enough to fit in a 697 * single header mbuf, allocate one and copy 698 * the data into it. This greatly reduces 699 * memory consumption when we receive lots 700 * of small packets. 701 * 702 * Otherwise, we add a new buffer to the receive 703 * chain. If this fails, we drop the packet and 704 * recycle the old buffer. 705 */ 706 if (epic_copy_small != 0 && len <= MHLEN) { 707 MGETHDR(m, M_DONTWAIT, MT_DATA); 708 if (m == NULL) 709 goto dropit; 710 memcpy(mtod(m, caddr_t), 711 mtod(ds->ds_mbuf, caddr_t), len); 712 EPIC_INIT_RXDESC(sc, i); 713 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 714 ds->ds_dmamap->dm_mapsize, 715 BUS_DMASYNC_PREREAD); 716 } else { 717 m = ds->ds_mbuf; 718 if (epic_add_rxbuf(sc, i) != 0) { 719 dropit: 720 ifp->if_ierrors++; 721 EPIC_INIT_RXDESC(sc, i); 722 bus_dmamap_sync(sc->sc_dmat, 723 ds->ds_dmamap, 0, 724 ds->ds_dmamap->dm_mapsize, 725 BUS_DMASYNC_PREREAD); 726 continue; 727 } 728 } 729 730 m->m_flags |= M_HASFCS; 731 m->m_pkthdr.rcvif = ifp; 732 m->m_pkthdr.len = m->m_len = len; 733 734 #if NBPFILTER > 0 735 /* 736 * Pass this up to any BPF listeners, but only 737 * pass it up the stack if its for us. 738 */ 739 if (ifp->if_bpf) 740 bpf_mtap(ifp->if_bpf, m); 741 #endif 742 743 /* Pass it on. */ 744 (*ifp->if_input)(ifp, m); 745 ifp->if_ipackets++; 746 } 747 748 /* Update the receive pointer. */ 749 sc->sc_rxptr = i; 750 751 /* 752 * Check for receive queue underflow. 753 */ 754 if (intstat & INTSTAT_RQE) { 755 printf("%s: receiver queue empty\n", 756 sc->sc_dev.dv_xname); 757 /* 758 * Ring is already built; just restart the 759 * receiver. 760 */ 761 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 762 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 763 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 764 COMMAND_RXQUEUED | COMMAND_START_RX); 765 } 766 } 767 768 /* 769 * Check for transmission complete interrupts. 770 */ 771 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 772 ifp->if_flags &= ~IFF_OACTIVE; 773 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 774 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 775 txd = EPIC_CDTX(sc, i); 776 ds = EPIC_DSTX(sc, i); 777 778 EPIC_CDTXSYNC(sc, i, 779 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 780 781 txstatus = txd->et_txstatus; 782 if (txstatus & ET_TXSTAT_OWNER) 783 break; 784 785 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 786 787 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 788 0, ds->ds_dmamap->dm_mapsize, 789 BUS_DMASYNC_POSTWRITE); 790 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 791 m_freem(ds->ds_mbuf); 792 ds->ds_mbuf = NULL; 793 794 /* 795 * Check for errors and collisions. 796 */ 797 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 798 ifp->if_oerrors++; 799 else 800 ifp->if_opackets++; 801 ifp->if_collisions += 802 TXSTAT_COLLISIONS(txstatus); 803 if (txstatus & ET_TXSTAT_CARSENSELOST) 804 printf("%s: lost carrier\n", 805 sc->sc_dev.dv_xname); 806 } 807 808 /* Update the dirty transmit buffer pointer. */ 809 sc->sc_txdirty = i; 810 811 /* 812 * Cancel the watchdog timer if there are no pending 813 * transmissions. 814 */ 815 if (sc->sc_txpending == 0) 816 ifp->if_timer = 0; 817 818 /* 819 * Kick the transmitter after a DMA underrun. 820 */ 821 if (intstat & INTSTAT_TXU) { 822 printf("%s: transmit underrun\n", sc->sc_dev.dv_xname); 823 bus_space_write_4(sc->sc_st, sc->sc_sh, 824 EPIC_COMMAND, COMMAND_TXUGO); 825 if (sc->sc_txpending) 826 bus_space_write_4(sc->sc_st, sc->sc_sh, 827 EPIC_COMMAND, COMMAND_TXQUEUED); 828 } 829 830 /* 831 * Try to get more packets going. 832 */ 833 epic_start(ifp); 834 } 835 836 /* 837 * Check for fatal interrupts. 838 */ 839 if (intstat & INTSTAT_FATAL_INT) { 840 if (intstat & INTSTAT_PTA) 841 printf("%s: PCI target abort error\n", 842 sc->sc_dev.dv_xname); 843 else if (intstat & INTSTAT_PMA) 844 printf("%s: PCI master abort error\n", 845 sc->sc_dev.dv_xname); 846 else if (intstat & INTSTAT_APE) 847 printf("%s: PCI address parity error\n", 848 sc->sc_dev.dv_xname); 849 else if (intstat & INTSTAT_DPE) 850 printf("%s: PCI data parity error\n", 851 sc->sc_dev.dv_xname); 852 else 853 printf("%s: unknown fatal error\n", 854 sc->sc_dev.dv_xname); 855 (void) epic_init(ifp); 856 } 857 858 /* 859 * Check for more interrupts. 860 */ 861 goto top; 862 } 863 864 /* 865 * One second timer, used to tick the MII. 866 */ 867 void 868 epic_tick(arg) 869 void *arg; 870 { 871 struct epic_softc *sc = arg; 872 int s; 873 874 s = splnet(); 875 mii_tick(&sc->sc_mii); 876 splx(s); 877 878 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 879 } 880 881 /* 882 * Fixup the clock source on the EPIC. 883 */ 884 void 885 epic_fixup_clock_source(sc) 886 struct epic_softc *sc; 887 { 888 int i; 889 890 /* 891 * According to SMC Application Note 7-15, the EPIC's clock 892 * source is incorrect following a reset. This manifests itself 893 * as failure to recognize when host software has written to 894 * a register on the EPIC. The appnote recommends issuing at 895 * least 16 consecutive writes to the CLOCK TEST bit to correctly 896 * configure the clock source. 897 */ 898 for (i = 0; i < 16; i++) 899 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 900 TEST_CLOCKTEST); 901 } 902 903 /* 904 * Perform a soft reset on the EPIC. 905 */ 906 void 907 epic_reset(sc) 908 struct epic_softc *sc; 909 { 910 911 epic_fixup_clock_source(sc); 912 913 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 914 delay(100); 915 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 916 delay(100); 917 918 epic_fixup_clock_source(sc); 919 } 920 921 /* 922 * Initialize the interface. Must be called at splnet(). 923 */ 924 int 925 epic_init(ifp) 926 struct ifnet *ifp; 927 { 928 struct epic_softc *sc = ifp->if_softc; 929 bus_space_tag_t st = sc->sc_st; 930 bus_space_handle_t sh = sc->sc_sh; 931 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 932 struct epic_txdesc *txd; 933 struct epic_descsoft *ds; 934 u_int32_t genctl, reg0; 935 int i, error = 0; 936 937 /* 938 * Cancel any pending I/O. 939 */ 940 epic_stop(ifp, 0); 941 942 /* 943 * Reset the EPIC to a known state. 944 */ 945 epic_reset(sc); 946 947 /* 948 * Magical mystery initialization. 949 */ 950 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 951 952 /* 953 * Initialize the EPIC genctl register: 954 * 955 * - 64 byte receive FIFO threshold 956 * - automatic advance to next receive frame 957 */ 958 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 959 #if BYTE_ORDER == BIG_ENDIAN 960 genctl |= GENCTL_BIG_ENDIAN; 961 #endif 962 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 963 964 /* 965 * Reset the MII bus and PHY. 966 */ 967 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 968 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 969 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 970 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 971 delay(100); 972 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 973 delay(1000); 974 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 975 976 /* 977 * Initialize Ethernet address. 978 */ 979 reg0 = enaddr[1] << 8 | enaddr[0]; 980 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 981 reg0 = enaddr[3] << 8 | enaddr[2]; 982 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 983 reg0 = enaddr[5] << 8 | enaddr[4]; 984 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 985 986 /* 987 * Initialize receive control. Remember the external buffer 988 * size setting. 989 */ 990 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 991 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 992 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 993 if (ifp->if_flags & IFF_PROMISC) 994 reg0 |= RXCON_PROMISCMODE; 995 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 996 997 /* Set the current media. */ 998 epic_mediachange(ifp); 999 1000 /* Set up the multicast hash table. */ 1001 epic_set_mchash(sc); 1002 1003 /* 1004 * Initialize the transmit descriptor ring. txlast is initialized 1005 * to the end of the list so that it will wrap around to the first 1006 * descriptor when the first packet is transmitted. 1007 */ 1008 for (i = 0; i < EPIC_NTXDESC; i++) { 1009 txd = EPIC_CDTX(sc, i); 1010 memset(txd, 0, sizeof(struct epic_txdesc)); 1011 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 1012 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 1013 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1014 } 1015 sc->sc_txpending = 0; 1016 sc->sc_txdirty = 0; 1017 sc->sc_txlast = EPIC_NTXDESC - 1; 1018 1019 /* 1020 * Initialize the receive descriptor ring. 1021 */ 1022 for (i = 0; i < EPIC_NRXDESC; i++) { 1023 ds = EPIC_DSRX(sc, i); 1024 if (ds->ds_mbuf == NULL) { 1025 if ((error = epic_add_rxbuf(sc, i)) != 0) { 1026 printf("%s: unable to allocate or map rx " 1027 "buffer %d error = %d\n", 1028 sc->sc_dev.dv_xname, i, error); 1029 /* 1030 * XXX Should attempt to run with fewer receive 1031 * XXX buffers instead of just failing. 1032 */ 1033 epic_rxdrain(sc); 1034 goto out; 1035 } 1036 } else 1037 EPIC_INIT_RXDESC(sc, i); 1038 } 1039 sc->sc_rxptr = 0; 1040 1041 /* 1042 * Initialize the interrupt mask and enable interrupts. 1043 */ 1044 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1045 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1046 1047 /* 1048 * Give the transmit and receive rings to the EPIC. 1049 */ 1050 bus_space_write_4(st, sh, EPIC_PTCDAR, 1051 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1052 bus_space_write_4(st, sh, EPIC_PRCDAR, 1053 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1054 1055 /* 1056 * Set the EPIC in motion. 1057 */ 1058 bus_space_write_4(st, sh, EPIC_COMMAND, 1059 COMMAND_RXQUEUED | COMMAND_START_RX); 1060 1061 /* 1062 * ...all done! 1063 */ 1064 ifp->if_flags |= IFF_RUNNING; 1065 ifp->if_flags &= ~IFF_OACTIVE; 1066 1067 /* 1068 * Start the one second clock. 1069 */ 1070 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 1071 1072 /* 1073 * Attempt to start output on the interface. 1074 */ 1075 epic_start(ifp); 1076 1077 out: 1078 if (error) 1079 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1080 return (error); 1081 } 1082 1083 /* 1084 * Drain the receive queue. 1085 */ 1086 void 1087 epic_rxdrain(sc) 1088 struct epic_softc *sc; 1089 { 1090 struct epic_descsoft *ds; 1091 int i; 1092 1093 for (i = 0; i < EPIC_NRXDESC; i++) { 1094 ds = EPIC_DSRX(sc, i); 1095 if (ds->ds_mbuf != NULL) { 1096 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1097 m_freem(ds->ds_mbuf); 1098 ds->ds_mbuf = NULL; 1099 } 1100 } 1101 } 1102 1103 /* 1104 * Stop transmission on the interface. 1105 */ 1106 void 1107 epic_stop(ifp, disable) 1108 struct ifnet *ifp; 1109 int disable; 1110 { 1111 struct epic_softc *sc = ifp->if_softc; 1112 bus_space_tag_t st = sc->sc_st; 1113 bus_space_handle_t sh = sc->sc_sh; 1114 struct epic_descsoft *ds; 1115 u_int32_t reg; 1116 int i; 1117 1118 /* 1119 * Stop the one second clock. 1120 */ 1121 callout_stop(&sc->sc_mii_callout); 1122 1123 /* Down the MII. */ 1124 mii_down(&sc->sc_mii); 1125 1126 /* Paranoia... */ 1127 epic_fixup_clock_source(sc); 1128 1129 /* 1130 * Disable interrupts. 1131 */ 1132 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1133 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1134 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1135 1136 /* 1137 * Stop the DMA engine and take the receiver off-line. 1138 */ 1139 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1140 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1141 1142 /* 1143 * Release any queued transmit buffers. 1144 */ 1145 for (i = 0; i < EPIC_NTXDESC; i++) { 1146 ds = EPIC_DSTX(sc, i); 1147 if (ds->ds_mbuf != NULL) { 1148 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1149 m_freem(ds->ds_mbuf); 1150 ds->ds_mbuf = NULL; 1151 } 1152 } 1153 1154 if (disable) 1155 epic_rxdrain(sc); 1156 1157 /* 1158 * Mark the interface down and cancel the watchdog timer. 1159 */ 1160 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1161 ifp->if_timer = 0; 1162 } 1163 1164 /* 1165 * Read the EPIC Serial EEPROM. 1166 */ 1167 void 1168 epic_read_eeprom(sc, word, wordcnt, data) 1169 struct epic_softc *sc; 1170 int word, wordcnt; 1171 u_int16_t *data; 1172 { 1173 bus_space_tag_t st = sc->sc_st; 1174 bus_space_handle_t sh = sc->sc_sh; 1175 u_int16_t reg; 1176 int i, x; 1177 1178 #define EEPROM_WAIT_READY(st, sh) \ 1179 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1180 /* nothing */ 1181 1182 /* 1183 * Enable the EEPROM. 1184 */ 1185 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1186 EEPROM_WAIT_READY(st, sh); 1187 1188 for (i = 0; i < wordcnt; i++) { 1189 /* Send CHIP SELECT for one clock tick. */ 1190 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1191 EEPROM_WAIT_READY(st, sh); 1192 1193 /* Shift in the READ opcode. */ 1194 for (x = 3; x > 0; x--) { 1195 reg = EECTL_ENABLE|EECTL_EECS; 1196 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1197 reg |= EECTL_EEDI; 1198 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1199 EEPROM_WAIT_READY(st, sh); 1200 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1201 EEPROM_WAIT_READY(st, sh); 1202 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1203 EEPROM_WAIT_READY(st, sh); 1204 } 1205 1206 /* Shift in address. */ 1207 for (x = 6; x > 0; x--) { 1208 reg = EECTL_ENABLE|EECTL_EECS; 1209 if ((word + i) & (1 << (x - 1))) 1210 reg |= EECTL_EEDI; 1211 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1212 EEPROM_WAIT_READY(st, sh); 1213 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1214 EEPROM_WAIT_READY(st, sh); 1215 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1216 EEPROM_WAIT_READY(st, sh); 1217 } 1218 1219 /* Shift out data. */ 1220 reg = EECTL_ENABLE|EECTL_EECS; 1221 data[i] = 0; 1222 for (x = 16; x > 0; x--) { 1223 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1224 EEPROM_WAIT_READY(st, sh); 1225 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1226 data[i] |= (1 << (x - 1)); 1227 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1228 EEPROM_WAIT_READY(st, sh); 1229 } 1230 1231 /* Clear CHIP SELECT. */ 1232 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1233 EEPROM_WAIT_READY(st, sh); 1234 } 1235 1236 /* 1237 * Disable the EEPROM. 1238 */ 1239 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1240 1241 #undef EEPROM_WAIT_READY 1242 } 1243 1244 /* 1245 * Add a receive buffer to the indicated descriptor. 1246 */ 1247 int 1248 epic_add_rxbuf(sc, idx) 1249 struct epic_softc *sc; 1250 int idx; 1251 { 1252 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1253 struct mbuf *m; 1254 int error; 1255 1256 MGETHDR(m, M_DONTWAIT, MT_DATA); 1257 if (m == NULL) 1258 return (ENOBUFS); 1259 1260 MCLGET(m, M_DONTWAIT); 1261 if ((m->m_flags & M_EXT) == 0) { 1262 m_freem(m); 1263 return (ENOBUFS); 1264 } 1265 1266 if (ds->ds_mbuf != NULL) 1267 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1268 1269 ds->ds_mbuf = m; 1270 1271 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1272 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1273 BUS_DMA_READ|BUS_DMA_NOWAIT); 1274 if (error) { 1275 printf("%s: can't load rx DMA map %d, error = %d\n", 1276 sc->sc_dev.dv_xname, idx, error); 1277 panic("epic_add_rxbuf"); /* XXX */ 1278 } 1279 1280 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1281 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1282 1283 EPIC_INIT_RXDESC(sc, idx); 1284 1285 return (0); 1286 } 1287 1288 /* 1289 * Set the EPIC multicast hash table. 1290 * 1291 * NOTE: We rely on a recently-updated mii_media_active here! 1292 */ 1293 void 1294 epic_set_mchash(sc) 1295 struct epic_softc *sc; 1296 { 1297 struct ethercom *ec = &sc->sc_ethercom; 1298 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1299 struct ether_multi *enm; 1300 struct ether_multistep step; 1301 u_int32_t hash, mchash[4]; 1302 1303 /* 1304 * Set up the multicast address filter by passing all multicast 1305 * addresses through a CRC generator, and then using the low-order 1306 * 6 bits as an index into the 64 bit multicast hash table (only 1307 * the lower 16 bits of each 32 bit multicast hash register are 1308 * valid). The high order bits select the register, while the 1309 * rest of the bits select the bit within the register. 1310 */ 1311 1312 if (ifp->if_flags & IFF_PROMISC) 1313 goto allmulti; 1314 1315 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1316 /* XXX hardware bug in 10Mbps mode. */ 1317 goto allmulti; 1318 } 1319 1320 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1321 1322 ETHER_FIRST_MULTI(step, ec, enm); 1323 while (enm != NULL) { 1324 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1325 /* 1326 * We must listen to a range of multicast addresses. 1327 * For now, just accept all multicasts, rather than 1328 * trying to set only those filter bits needed to match 1329 * the range. (At this time, the only use of address 1330 * ranges is for IP multicast routing, for which the 1331 * range is big enough to require all bits set.) 1332 */ 1333 goto allmulti; 1334 } 1335 1336 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1337 hash >>= 26; 1338 1339 /* Set the corresponding bit in the hash table. */ 1340 mchash[hash >> 4] |= 1 << (hash & 0xf); 1341 1342 ETHER_NEXT_MULTI(step, enm); 1343 } 1344 1345 ifp->if_flags &= ~IFF_ALLMULTI; 1346 goto sethash; 1347 1348 allmulti: 1349 ifp->if_flags |= IFF_ALLMULTI; 1350 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1351 1352 sethash: 1353 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1354 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1355 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1356 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1357 } 1358 1359 /* 1360 * Wait for the MII to become ready. 1361 */ 1362 int 1363 epic_mii_wait(sc, rw) 1364 struct epic_softc *sc; 1365 u_int32_t rw; 1366 { 1367 int i; 1368 1369 for (i = 0; i < 50; i++) { 1370 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1371 == 0) 1372 break; 1373 delay(2); 1374 } 1375 if (i == 50) { 1376 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1377 return (1); 1378 } 1379 1380 return (0); 1381 } 1382 1383 /* 1384 * Read from the MII. 1385 */ 1386 int 1387 epic_mii_read(self, phy, reg) 1388 struct device *self; 1389 int phy, reg; 1390 { 1391 struct epic_softc *sc = (struct epic_softc *)self; 1392 1393 if (epic_mii_wait(sc, MMCTL_WRITE)) 1394 return (0); 1395 1396 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1397 MMCTL_ARG(phy, reg, MMCTL_READ)); 1398 1399 if (epic_mii_wait(sc, MMCTL_READ)) 1400 return (0); 1401 1402 return (bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1403 MMDATA_MASK); 1404 } 1405 1406 /* 1407 * Write to the MII. 1408 */ 1409 void 1410 epic_mii_write(self, phy, reg, val) 1411 struct device *self; 1412 int phy, reg, val; 1413 { 1414 struct epic_softc *sc = (struct epic_softc *)self; 1415 1416 if (epic_mii_wait(sc, MMCTL_WRITE)) 1417 return; 1418 1419 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1420 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1421 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1422 } 1423 1424 /* 1425 * Callback from PHY when media changes. 1426 */ 1427 void 1428 epic_statchg(self) 1429 struct device *self; 1430 { 1431 struct epic_softc *sc = (struct epic_softc *)self; 1432 u_int32_t txcon, miicfg; 1433 1434 /* 1435 * Update loopback bits in TXCON to reflect duplex mode. 1436 */ 1437 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1438 if (sc->sc_mii.mii_media_active & IFM_FDX) 1439 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1440 else 1441 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1442 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1443 1444 /* On some cards we need manualy set fullduplex led */ 1445 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1446 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1447 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1448 miicfg |= MIICFG_ENABLE; 1449 else 1450 miicfg &= ~MIICFG_ENABLE; 1451 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1452 } 1453 1454 /* 1455 * There is a multicast filter bug in 10Mbps mode. Kick the 1456 * multicast filter in case the speed changed. 1457 */ 1458 epic_set_mchash(sc); 1459 } 1460 1461 /* 1462 * Callback from ifmedia to request current media status. 1463 */ 1464 void 1465 epic_mediastatus(ifp, ifmr) 1466 struct ifnet *ifp; 1467 struct ifmediareq *ifmr; 1468 { 1469 struct epic_softc *sc = ifp->if_softc; 1470 1471 mii_pollstat(&sc->sc_mii); 1472 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1473 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1474 } 1475 1476 /* 1477 * Callback from ifmedia to request new media setting. 1478 */ 1479 int 1480 epic_mediachange(ifp) 1481 struct ifnet *ifp; 1482 { 1483 struct epic_softc *sc = ifp->if_softc; 1484 struct mii_data *mii = &sc->sc_mii; 1485 struct ifmedia *ifm = &mii->mii_media; 1486 int media = ifm->ifm_cur->ifm_media; 1487 u_int32_t miicfg; 1488 struct mii_softc *miisc; 1489 int cfg; 1490 1491 if (!(ifp->if_flags & IFF_UP)) 1492 return (0); 1493 1494 if (IFM_INST(media) != sc->sc_serinst) { 1495 /* If we're not selecting serial interface, select MII mode */ 1496 #ifdef EPICMEDIADEBUG 1497 printf("%s: parallel mode\n", ifp->if_xname); 1498 #endif 1499 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1500 miicfg &= ~MIICFG_SERMODEENA; 1501 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1502 } 1503 1504 mii_mediachg(mii); 1505 1506 if (IFM_INST(media) == sc->sc_serinst) { 1507 /* select serial interface */ 1508 #ifdef EPICMEDIADEBUG 1509 printf("%s: serial mode\n", ifp->if_xname); 1510 #endif 1511 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1512 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1513 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1514 1515 /* There is no driver to fill this */ 1516 mii->mii_media_active = media; 1517 mii->mii_media_status = 0; 1518 1519 epic_statchg(&sc->sc_dev); 1520 return (0); 1521 } 1522 1523 /* Lookup selected PHY */ 1524 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1525 miisc = LIST_NEXT(miisc, mii_list)) { 1526 if (IFM_INST(media) == miisc->mii_inst) 1527 break; 1528 } 1529 if (!miisc) { 1530 printf("epic_mediachange: can't happen\n"); /* ??? panic */ 1531 return (0); 1532 } 1533 #ifdef EPICMEDIADEBUG 1534 printf("%s: using phy %s\n", ifp->if_xname, 1535 miisc->mii_dev.dv_xname); 1536 #endif 1537 1538 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1539 /* XXX XXX assume it's a Level1 - should check */ 1540 1541 /* We have to powerup fiber transceivers */ 1542 cfg = PHY_READ(miisc, MII_LXTPHY_CONFIG); 1543 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1544 #ifdef EPICMEDIADEBUG 1545 printf("%s: power up fiber\n", ifp->if_xname); 1546 #endif 1547 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1548 } else { 1549 #ifdef EPICMEDIADEBUG 1550 printf("%s: power down fiber\n", ifp->if_xname); 1551 #endif 1552 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1553 } 1554 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1555 } 1556 1557 return (0); 1558 }
Cache object: adbb9ef7d1b2b060e787fc338ff7540c
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