FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/smc83c170.c
1 /* $NetBSD: smc83c170.c,v 1.63 2006/04/16 00:38:59 tsutsui Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * Device driver for the Standard Microsystems Corp. 83C170
42 * Ethernet PCI Integrated Controller (EPIC/100).
43 */
44
45 #include <sys/cdefs.h>
46 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.63 2006/04/16 00:38:59 tsutsui Exp $");
47
48 #include "bpfilter.h"
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/callout.h>
53 #include <sys/mbuf.h>
54 #include <sys/malloc.h>
55 #include <sys/kernel.h>
56 #include <sys/socket.h>
57 #include <sys/ioctl.h>
58 #include <sys/errno.h>
59 #include <sys/device.h>
60
61 #include <uvm/uvm_extern.h>
62
63 #include <net/if.h>
64 #include <net/if_dl.h>
65 #include <net/if_media.h>
66 #include <net/if_ether.h>
67
68 #if NBPFILTER > 0
69 #include <net/bpf.h>
70 #endif
71
72 #include <machine/bus.h>
73 #include <machine/intr.h>
74
75 #include <dev/mii/miivar.h>
76 #include <dev/mii/lxtphyreg.h>
77
78 #include <dev/ic/smc83c170reg.h>
79 #include <dev/ic/smc83c170var.h>
80
81 void epic_start(struct ifnet *);
82 void epic_watchdog(struct ifnet *);
83 int epic_ioctl(struct ifnet *, u_long, caddr_t);
84 int epic_init(struct ifnet *);
85 void epic_stop(struct ifnet *, int);
86
87 void epic_shutdown(void *);
88
89 void epic_reset(struct epic_softc *);
90 void epic_rxdrain(struct epic_softc *);
91 int epic_add_rxbuf(struct epic_softc *, int);
92 void epic_read_eeprom(struct epic_softc *, int, int, uint16_t *);
93 void epic_set_mchash(struct epic_softc *);
94 void epic_fixup_clock_source(struct epic_softc *);
95 int epic_mii_read(struct device *, int, int);
96 void epic_mii_write(struct device *, int, int, int);
97 int epic_mii_wait(struct epic_softc *, uint32_t);
98 void epic_tick(void *);
99
100 void epic_statchg(struct device *);
101 int epic_mediachange(struct ifnet *);
102 void epic_mediastatus(struct ifnet *, struct ifmediareq *);
103
104 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \
105 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC)
106
107 int epic_copy_small = 0;
108
109 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
110
111 /*
112 * Attach an EPIC interface to the system.
113 */
114 void
115 epic_attach(sc)
116 struct epic_softc *sc;
117 {
118 bus_space_tag_t st = sc->sc_st;
119 bus_space_handle_t sh = sc->sc_sh;
120 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
121 int rseg, error, miiflags;
122 u_int i;
123 bus_dma_segment_t seg;
124 uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1];
125 uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6];
126 char *nullbuf;
127
128 callout_init(&sc->sc_mii_callout);
129
130 /*
131 * Allocate the control data structures, and create and load the
132 * DMA map for it.
133 */
134 if ((error = bus_dmamem_alloc(sc->sc_dmat,
135 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0,
136 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
137 aprint_error(
138 "%s: unable to allocate control data, error = %d\n",
139 sc->sc_dev.dv_xname, error);
140 goto fail_0;
141 }
142
143 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
144 sizeof(struct epic_control_data) + ETHER_PAD_LEN,
145 (caddr_t *)&sc->sc_control_data,
146 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
147 aprint_error("%s: unable to map control data, error = %d\n",
148 sc->sc_dev.dv_xname, error);
149 goto fail_1;
150 }
151 nullbuf =
152 (char *)sc->sc_control_data + sizeof(struct epic_control_data);
153 memset(nullbuf, 0, ETHER_PAD_LEN);
154
155 if ((error = bus_dmamap_create(sc->sc_dmat,
156 sizeof(struct epic_control_data), 1,
157 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT,
158 &sc->sc_cddmamap)) != 0) {
159 aprint_error("%s: unable to create control data DMA map, "
160 "error = %d\n", sc->sc_dev.dv_xname, error);
161 goto fail_2;
162 }
163
164 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
165 sc->sc_control_data, sizeof(struct epic_control_data), NULL,
166 BUS_DMA_NOWAIT)) != 0) {
167 aprint_error(
168 "%s: unable to load control data DMA map, error = %d\n",
169 sc->sc_dev.dv_xname, error);
170 goto fail_3;
171 }
172
173 /*
174 * Create the transmit buffer DMA maps.
175 */
176 for (i = 0; i < EPIC_NTXDESC; i++) {
177 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
178 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
179 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) {
180 aprint_error("%s: unable to create tx DMA map %d, "
181 "error = %d\n", sc->sc_dev.dv_xname, i, error);
182 goto fail_4;
183 }
184 }
185
186 /*
187 * Create the receive buffer DMA maps.
188 */
189 for (i = 0; i < EPIC_NRXDESC; i++) {
190 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
191 MCLBYTES, 0, BUS_DMA_NOWAIT,
192 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) {
193 aprint_error("%s: unable to create rx DMA map %d, "
194 "error = %d\n", sc->sc_dev.dv_xname, i, error);
195 goto fail_5;
196 }
197 EPIC_DSRX(sc, i)->ds_mbuf = NULL;
198 }
199
200 /*
201 * create and map the pad buffer
202 */
203 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1,
204 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) {
205 printf("%s: unable to create pad buffer DMA map, "
206 "error = %d\n", sc->sc_dev.dv_xname, error);
207 goto fail_5;
208 }
209
210 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap,
211 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) {
212 printf("%s: unable to load pad buffer DMA map, "
213 "error = %d\n", sc->sc_dev.dv_xname, error);
214 goto fail_6;
215 }
216 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN,
217 BUS_DMASYNC_PREWRITE);
218
219 /*
220 * Bring the chip out of low-power mode and reset it to a known state.
221 */
222 bus_space_write_4(st, sh, EPIC_GENCTL, 0);
223 epic_reset(sc);
224
225 /*
226 * Read the Ethernet address from the EEPROM.
227 */
228 epic_read_eeprom(sc, 0, __arraycount(myea), myea);
229 for (i = 0; i < __arraycount(myea); i++) {
230 enaddr[i * 2] = myea[i] & 0xff;
231 enaddr[i * 2 + 1] = myea[i] >> 8;
232 }
233
234 /*
235 * ...and the device name.
236 */
237 epic_read_eeprom(sc, 0x2c, __arraycount(mydevname), mydevname);
238 for (i = 0; i < __arraycount(mydevname); i++) {
239 devname[i * 2] = mydevname[i] & 0xff;
240 devname[i * 2 + 1] = mydevname[i] >> 8;
241 }
242
243 devname[sizeof(mydevname)] = '\0';
244 for (i = sizeof(mydevname) ; i > 0; i--) {
245 if (devname[i - 1] == ' ')
246 devname[i - 1] = '\0';
247 else
248 break;
249 }
250
251 aprint_normal("%s: %s, Ethernet address %s\n", sc->sc_dev.dv_xname,
252 devname, ether_sprintf(enaddr));
253
254 miiflags = 0;
255 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER)
256 miiflags |= MIIF_HAVEFIBER;
257
258 /*
259 * Initialize our media structures and probe the MII.
260 */
261 sc->sc_mii.mii_ifp = ifp;
262 sc->sc_mii.mii_readreg = epic_mii_read;
263 sc->sc_mii.mii_writereg = epic_mii_write;
264 sc->sc_mii.mii_statchg = epic_statchg;
265 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epic_mediachange,
266 epic_mediastatus);
267 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
268 MII_OFFSET_ANY, miiflags);
269 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
270 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
271 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
272 } else
273 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
274
275 if (sc->sc_hwflags & EPIC_HAS_BNC) {
276 /* use the next free media instance */
277 sc->sc_serinst = sc->sc_mii.mii_instance++;
278 ifmedia_add(&sc->sc_mii.mii_media,
279 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0,
280 sc->sc_serinst),
281 0, NULL);
282 aprint_normal("%s: 10base2/BNC\n", sc->sc_dev.dv_xname);
283 } else
284 sc->sc_serinst = -1;
285
286 strcpy(ifp->if_xname, sc->sc_dev.dv_xname);
287 ifp->if_softc = sc;
288 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
289 ifp->if_ioctl = epic_ioctl;
290 ifp->if_start = epic_start;
291 ifp->if_watchdog = epic_watchdog;
292 ifp->if_init = epic_init;
293 ifp->if_stop = epic_stop;
294 IFQ_SET_READY(&ifp->if_snd);
295
296 /*
297 * We can support 802.1Q VLAN-sized frames.
298 */
299 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
300
301 /*
302 * Attach the interface.
303 */
304 if_attach(ifp);
305 ether_ifattach(ifp, enaddr);
306
307 /*
308 * Make sure the interface is shutdown during reboot.
309 */
310 sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc);
311 if (sc->sc_sdhook == NULL)
312 aprint_error("%s: WARNING: unable to establish shutdown hook\n",
313 sc->sc_dev.dv_xname);
314 return;
315
316 /*
317 * Free any resources we've allocated during the failed attach
318 * attempt. Do this in reverse order and fall through.
319 */
320 fail_6:
321 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap);
322 fail_5:
323 for (i = 0; i < EPIC_NRXDESC; i++) {
324 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL)
325 bus_dmamap_destroy(sc->sc_dmat,
326 EPIC_DSRX(sc, i)->ds_dmamap);
327 }
328 fail_4:
329 for (i = 0; i < EPIC_NTXDESC; i++) {
330 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL)
331 bus_dmamap_destroy(sc->sc_dmat,
332 EPIC_DSTX(sc, i)->ds_dmamap);
333 }
334 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
335 fail_3:
336 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
337 fail_2:
338 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data,
339 sizeof(struct epic_control_data));
340 fail_1:
341 bus_dmamem_free(sc->sc_dmat, &seg, rseg);
342 fail_0:
343 return;
344 }
345
346 /*
347 * Shutdown hook. Make sure the interface is stopped at reboot.
348 */
349 void
350 epic_shutdown(arg)
351 void *arg;
352 {
353 struct epic_softc *sc = arg;
354
355 epic_stop(&sc->sc_ethercom.ec_if, 1);
356 }
357
358 /*
359 * Start packet transmission on the interface.
360 * [ifnet interface function]
361 */
362 void
363 epic_start(ifp)
364 struct ifnet *ifp;
365 {
366 struct epic_softc *sc = ifp->if_softc;
367 struct mbuf *m0, *m;
368 struct epic_txdesc *txd;
369 struct epic_descsoft *ds;
370 struct epic_fraglist *fr;
371 bus_dmamap_t dmamap;
372 int error, firsttx, nexttx, opending, seg;
373 u_int len;
374
375 /*
376 * Remember the previous txpending and the first transmit
377 * descriptor we use.
378 */
379 opending = sc->sc_txpending;
380 firsttx = EPIC_NEXTTX(sc->sc_txlast);
381
382 /*
383 * Loop through the send queue, setting up transmit descriptors
384 * until we drain the queue, or use up all available transmit
385 * descriptors.
386 */
387 while (sc->sc_txpending < EPIC_NTXDESC) {
388 /*
389 * Grab a packet off the queue.
390 */
391 IFQ_POLL(&ifp->if_snd, m0);
392 if (m0 == NULL)
393 break;
394 m = NULL;
395
396 /*
397 * Get the last and next available transmit descriptor.
398 */
399 nexttx = EPIC_NEXTTX(sc->sc_txlast);
400 txd = EPIC_CDTX(sc, nexttx);
401 fr = EPIC_CDFL(sc, nexttx);
402 ds = EPIC_DSTX(sc, nexttx);
403 dmamap = ds->ds_dmamap;
404
405 /*
406 * Load the DMA map. If this fails, the packet either
407 * didn't fit in the alloted number of frags, or we were
408 * short on resources. In this case, we'll copy and try
409 * again.
410 */
411 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
412 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 ||
413 (m0->m_pkthdr.len < ETHER_PAD_LEN &&
414 dmamap-> dm_nsegs == EPIC_NFRAGS)) {
415 if (error == 0)
416 bus_dmamap_unload(sc->sc_dmat, dmamap);
417
418 MGETHDR(m, M_DONTWAIT, MT_DATA);
419 if (m == NULL) {
420 printf("%s: unable to allocate Tx mbuf\n",
421 sc->sc_dev.dv_xname);
422 break;
423 }
424 if (m0->m_pkthdr.len > MHLEN) {
425 MCLGET(m, M_DONTWAIT);
426 if ((m->m_flags & M_EXT) == 0) {
427 printf("%s: unable to allocate Tx "
428 "cluster\n", sc->sc_dev.dv_xname);
429 m_freem(m);
430 break;
431 }
432 }
433 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t));
434 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
435 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
436 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
437 if (error) {
438 printf("%s: unable to load Tx buffer, "
439 "error = %d\n", sc->sc_dev.dv_xname, error);
440 break;
441 }
442 }
443 IFQ_DEQUEUE(&ifp->if_snd, m0);
444 if (m != NULL) {
445 m_freem(m0);
446 m0 = m;
447 }
448
449 /* Initialize the fraglist. */
450 for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
451 fr->ef_frags[seg].ef_addr =
452 dmamap->dm_segs[seg].ds_addr;
453 fr->ef_frags[seg].ef_length =
454 dmamap->dm_segs[seg].ds_len;
455 }
456 len = m0->m_pkthdr.len;
457 if (len < ETHER_PAD_LEN) {
458 fr->ef_frags[seg].ef_addr = sc->sc_nulldma;
459 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len;
460 len = ETHER_PAD_LEN;
461 seg++;
462 }
463 fr->ef_nfrags = seg;
464
465 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE);
466
467 /* Sync the DMA map. */
468 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
469 BUS_DMASYNC_PREWRITE);
470
471 /*
472 * Store a pointer to the packet so we can free it later.
473 */
474 ds->ds_mbuf = m0;
475
476 /*
477 * Fill in the transmit descriptor.
478 */
479 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST;
480
481 /*
482 * If this is the first descriptor we're enqueueing,
483 * don't give it to the EPIC yet. That could cause
484 * a race condition. We'll do it below.
485 */
486 if (nexttx == firsttx)
487 txd->et_txstatus = TXSTAT_TXLENGTH(len);
488 else
489 txd->et_txstatus =
490 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER;
491
492 EPIC_CDTXSYNC(sc, nexttx,
493 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
494
495 /* Advance the tx pointer. */
496 sc->sc_txpending++;
497 sc->sc_txlast = nexttx;
498
499 #if NBPFILTER > 0
500 /*
501 * Pass the packet to any BPF listeners.
502 */
503 if (ifp->if_bpf)
504 bpf_mtap(ifp->if_bpf, m0);
505 #endif
506 }
507
508 if (sc->sc_txpending == EPIC_NTXDESC) {
509 /* No more slots left; notify upper layer. */
510 ifp->if_flags |= IFF_OACTIVE;
511 }
512
513 if (sc->sc_txpending != opending) {
514 /*
515 * We enqueued packets. If the transmitter was idle,
516 * reset the txdirty pointer.
517 */
518 if (opending == 0)
519 sc->sc_txdirty = firsttx;
520
521 /*
522 * Cause a transmit interrupt to happen on the
523 * last packet we enqueued.
524 */
525 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF;
526 EPIC_CDTXSYNC(sc, sc->sc_txlast,
527 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
528
529 /*
530 * The entire packet chain is set up. Give the
531 * first descriptor to the EPIC now.
532 */
533 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER;
534 EPIC_CDTXSYNC(sc, firsttx,
535 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
536
537 /* Start the transmitter. */
538 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND,
539 COMMAND_TXQUEUED);
540
541 /* Set a watchdog timer in case the chip flakes out. */
542 ifp->if_timer = 5;
543 }
544 }
545
546 /*
547 * Watchdog timer handler.
548 * [ifnet interface function]
549 */
550 void
551 epic_watchdog(ifp)
552 struct ifnet *ifp;
553 {
554 struct epic_softc *sc = ifp->if_softc;
555
556 printf("%s: device timeout\n", sc->sc_dev.dv_xname);
557 ifp->if_oerrors++;
558
559 (void) epic_init(ifp);
560 }
561
562 /*
563 * Handle control requests from the operator.
564 * [ifnet interface function]
565 */
566 int
567 epic_ioctl(ifp, cmd, data)
568 struct ifnet *ifp;
569 u_long cmd;
570 caddr_t data;
571 {
572 struct epic_softc *sc = ifp->if_softc;
573 struct ifreq *ifr = (struct ifreq *)data;
574 int s, error;
575
576 s = splnet();
577
578 switch (cmd) {
579 case SIOCSIFMEDIA:
580 case SIOCGIFMEDIA:
581 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd);
582 break;
583
584 default:
585 error = ether_ioctl(ifp, cmd, data);
586 if (error == ENETRESET) {
587 /*
588 * Multicast list has changed; set the hardware filter
589 * accordingly. Update our idea of the current media;
590 * epic_set_mchash() needs to know what it is.
591 */
592 if (ifp->if_flags & IFF_RUNNING) {
593 mii_pollstat(&sc->sc_mii);
594 epic_set_mchash(sc);
595 }
596 error = 0;
597 }
598 break;
599 }
600
601 splx(s);
602 return (error);
603 }
604
605 /*
606 * Interrupt handler.
607 */
608 int
609 epic_intr(arg)
610 void *arg;
611 {
612 struct epic_softc *sc = arg;
613 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
614 struct epic_rxdesc *rxd;
615 struct epic_txdesc *txd;
616 struct epic_descsoft *ds;
617 struct mbuf *m;
618 uint32_t intstat, rxstatus, txstatus;
619 int i, claimed = 0;
620 u_int len;
621
622 top:
623 /*
624 * Get the interrupt status from the EPIC.
625 */
626 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT);
627 if ((intstat & INTSTAT_INT_ACTV) == 0)
628 return (claimed);
629
630 claimed = 1;
631
632 /*
633 * Acknowledge the interrupt.
634 */
635 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT,
636 intstat & INTMASK);
637
638 /*
639 * Check for receive interrupts.
640 */
641 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) {
642 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) {
643 rxd = EPIC_CDRX(sc, i);
644 ds = EPIC_DSRX(sc, i);
645
646 EPIC_CDRXSYNC(sc, i,
647 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
648
649 rxstatus = rxd->er_rxstatus;
650 if (rxstatus & ER_RXSTAT_OWNER) {
651 /*
652 * We have processed all of the
653 * receive buffers.
654 */
655 break;
656 }
657
658 /*
659 * Make sure the packet arrived intact. If an error
660 * occurred, update stats and reset the descriptor.
661 * The buffer will be reused the next time the
662 * descriptor comes up in the ring.
663 */
664 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) {
665 if (rxstatus & ER_RXSTAT_CRCERROR)
666 printf("%s: CRC error\n",
667 sc->sc_dev.dv_xname);
668 if (rxstatus & ER_RXSTAT_ALIGNERROR)
669 printf("%s: alignment error\n",
670 sc->sc_dev.dv_xname);
671 ifp->if_ierrors++;
672 EPIC_INIT_RXDESC(sc, i);
673 continue;
674 }
675
676 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
677 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
678
679 /*
680 * The EPIC includes the CRC with every packet;
681 * trim it.
682 */
683 len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN;
684
685 if (len < sizeof(struct ether_header)) {
686 /*
687 * Runt packet; drop it now.
688 */
689 ifp->if_ierrors++;
690 EPIC_INIT_RXDESC(sc, i);
691 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
692 ds->ds_dmamap->dm_mapsize,
693 BUS_DMASYNC_PREREAD);
694 continue;
695 }
696
697 /*
698 * If the packet is small enough to fit in a
699 * single header mbuf, allocate one and copy
700 * the data into it. This greatly reduces
701 * memory consumption when we receive lots
702 * of small packets.
703 *
704 * Otherwise, we add a new buffer to the receive
705 * chain. If this fails, we drop the packet and
706 * recycle the old buffer.
707 */
708 if (epic_copy_small != 0 && len <= MHLEN) {
709 MGETHDR(m, M_DONTWAIT, MT_DATA);
710 if (m == NULL)
711 goto dropit;
712 memcpy(mtod(m, caddr_t),
713 mtod(ds->ds_mbuf, caddr_t), len);
714 EPIC_INIT_RXDESC(sc, i);
715 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
716 ds->ds_dmamap->dm_mapsize,
717 BUS_DMASYNC_PREREAD);
718 } else {
719 m = ds->ds_mbuf;
720 if (epic_add_rxbuf(sc, i) != 0) {
721 dropit:
722 ifp->if_ierrors++;
723 EPIC_INIT_RXDESC(sc, i);
724 bus_dmamap_sync(sc->sc_dmat,
725 ds->ds_dmamap, 0,
726 ds->ds_dmamap->dm_mapsize,
727 BUS_DMASYNC_PREREAD);
728 continue;
729 }
730 }
731
732 m->m_pkthdr.rcvif = ifp;
733 m->m_pkthdr.len = m->m_len = len;
734
735 #if NBPFILTER > 0
736 /*
737 * Pass this up to any BPF listeners, but only
738 * pass it up the stack if its for us.
739 */
740 if (ifp->if_bpf)
741 bpf_mtap(ifp->if_bpf, m);
742 #endif
743
744 /* Pass it on. */
745 (*ifp->if_input)(ifp, m);
746 ifp->if_ipackets++;
747 }
748
749 /* Update the receive pointer. */
750 sc->sc_rxptr = i;
751
752 /*
753 * Check for receive queue underflow.
754 */
755 if (intstat & INTSTAT_RQE) {
756 printf("%s: receiver queue empty\n",
757 sc->sc_dev.dv_xname);
758 /*
759 * Ring is already built; just restart the
760 * receiver.
761 */
762 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR,
763 EPIC_CDRXADDR(sc, sc->sc_rxptr));
764 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND,
765 COMMAND_RXQUEUED | COMMAND_START_RX);
766 }
767 }
768
769 /*
770 * Check for transmission complete interrupts.
771 */
772 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) {
773 ifp->if_flags &= ~IFF_OACTIVE;
774 for (i = sc->sc_txdirty; sc->sc_txpending != 0;
775 i = EPIC_NEXTTX(i), sc->sc_txpending--) {
776 txd = EPIC_CDTX(sc, i);
777 ds = EPIC_DSTX(sc, i);
778
779 EPIC_CDTXSYNC(sc, i,
780 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
781
782 txstatus = txd->et_txstatus;
783 if (txstatus & ET_TXSTAT_OWNER)
784 break;
785
786 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE);
787
788 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap,
789 0, ds->ds_dmamap->dm_mapsize,
790 BUS_DMASYNC_POSTWRITE);
791 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
792 m_freem(ds->ds_mbuf);
793 ds->ds_mbuf = NULL;
794
795 /*
796 * Check for errors and collisions.
797 */
798 if ((txstatus & ET_TXSTAT_PACKETTX) == 0)
799 ifp->if_oerrors++;
800 else
801 ifp->if_opackets++;
802 ifp->if_collisions +=
803 TXSTAT_COLLISIONS(txstatus);
804 if (txstatus & ET_TXSTAT_CARSENSELOST)
805 printf("%s: lost carrier\n",
806 sc->sc_dev.dv_xname);
807 }
808
809 /* Update the dirty transmit buffer pointer. */
810 sc->sc_txdirty = i;
811
812 /*
813 * Cancel the watchdog timer if there are no pending
814 * transmissions.
815 */
816 if (sc->sc_txpending == 0)
817 ifp->if_timer = 0;
818
819 /*
820 * Kick the transmitter after a DMA underrun.
821 */
822 if (intstat & INTSTAT_TXU) {
823 printf("%s: transmit underrun\n", sc->sc_dev.dv_xname);
824 bus_space_write_4(sc->sc_st, sc->sc_sh,
825 EPIC_COMMAND, COMMAND_TXUGO);
826 if (sc->sc_txpending)
827 bus_space_write_4(sc->sc_st, sc->sc_sh,
828 EPIC_COMMAND, COMMAND_TXQUEUED);
829 }
830
831 /*
832 * Try to get more packets going.
833 */
834 epic_start(ifp);
835 }
836
837 /*
838 * Check for fatal interrupts.
839 */
840 if (intstat & INTSTAT_FATAL_INT) {
841 if (intstat & INTSTAT_PTA)
842 printf("%s: PCI target abort error\n",
843 sc->sc_dev.dv_xname);
844 else if (intstat & INTSTAT_PMA)
845 printf("%s: PCI master abort error\n",
846 sc->sc_dev.dv_xname);
847 else if (intstat & INTSTAT_APE)
848 printf("%s: PCI address parity error\n",
849 sc->sc_dev.dv_xname);
850 else if (intstat & INTSTAT_DPE)
851 printf("%s: PCI data parity error\n",
852 sc->sc_dev.dv_xname);
853 else
854 printf("%s: unknown fatal error\n",
855 sc->sc_dev.dv_xname);
856 (void) epic_init(ifp);
857 }
858
859 /*
860 * Check for more interrupts.
861 */
862 goto top;
863 }
864
865 /*
866 * One second timer, used to tick the MII.
867 */
868 void
869 epic_tick(arg)
870 void *arg;
871 {
872 struct epic_softc *sc = arg;
873 int s;
874
875 s = splnet();
876 mii_tick(&sc->sc_mii);
877 splx(s);
878
879 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc);
880 }
881
882 /*
883 * Fixup the clock source on the EPIC.
884 */
885 void
886 epic_fixup_clock_source(sc)
887 struct epic_softc *sc;
888 {
889 int i;
890
891 /*
892 * According to SMC Application Note 7-15, the EPIC's clock
893 * source is incorrect following a reset. This manifests itself
894 * as failure to recognize when host software has written to
895 * a register on the EPIC. The appnote recommends issuing at
896 * least 16 consecutive writes to the CLOCK TEST bit to correctly
897 * configure the clock source.
898 */
899 for (i = 0; i < 16; i++)
900 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST,
901 TEST_CLOCKTEST);
902 }
903
904 /*
905 * Perform a soft reset on the EPIC.
906 */
907 void
908 epic_reset(sc)
909 struct epic_softc *sc;
910 {
911
912 epic_fixup_clock_source(sc);
913
914 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0);
915 delay(100);
916 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET);
917 delay(100);
918
919 epic_fixup_clock_source(sc);
920 }
921
922 /*
923 * Initialize the interface. Must be called at splnet().
924 */
925 int
926 epic_init(ifp)
927 struct ifnet *ifp;
928 {
929 struct epic_softc *sc = ifp->if_softc;
930 bus_space_tag_t st = sc->sc_st;
931 bus_space_handle_t sh = sc->sc_sh;
932 uint8_t *enaddr = LLADDR(ifp->if_sadl);
933 struct epic_txdesc *txd;
934 struct epic_descsoft *ds;
935 uint32_t genctl, reg0;
936 int i, error = 0;
937
938 /*
939 * Cancel any pending I/O.
940 */
941 epic_stop(ifp, 0);
942
943 /*
944 * Reset the EPIC to a known state.
945 */
946 epic_reset(sc);
947
948 /*
949 * Magical mystery initialization.
950 */
951 bus_space_write_4(st, sh, EPIC_TXTEST, 0);
952
953 /*
954 * Initialize the EPIC genctl register:
955 *
956 * - 64 byte receive FIFO threshold
957 * - automatic advance to next receive frame
958 */
959 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY;
960 #if BYTE_ORDER == BIG_ENDIAN
961 genctl |= GENCTL_BIG_ENDIAN;
962 #endif
963 bus_space_write_4(st, sh, EPIC_GENCTL, genctl);
964
965 /*
966 * Reset the MII bus and PHY.
967 */
968 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL);
969 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1);
970 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER);
971 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY);
972 delay(100);
973 bus_space_write_4(st, sh, EPIC_GENCTL, genctl);
974 delay(1000);
975 bus_space_write_4(st, sh, EPIC_NVCTL, reg0);
976
977 /*
978 * Initialize Ethernet address.
979 */
980 reg0 = enaddr[1] << 8 | enaddr[0];
981 bus_space_write_4(st, sh, EPIC_LAN0, reg0);
982 reg0 = enaddr[3] << 8 | enaddr[2];
983 bus_space_write_4(st, sh, EPIC_LAN1, reg0);
984 reg0 = enaddr[5] << 8 | enaddr[4];
985 bus_space_write_4(st, sh, EPIC_LAN2, reg0);
986
987 /*
988 * Initialize receive control. Remember the external buffer
989 * size setting.
990 */
991 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) &
992 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0);
993 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST);
994 if (ifp->if_flags & IFF_PROMISC)
995 reg0 |= RXCON_PROMISCMODE;
996 bus_space_write_4(st, sh, EPIC_RXCON, reg0);
997
998 /* Set the current media. */
999 epic_mediachange(ifp);
1000
1001 /* Set up the multicast hash table. */
1002 epic_set_mchash(sc);
1003
1004 /*
1005 * Initialize the transmit descriptor ring. txlast is initialized
1006 * to the end of the list so that it will wrap around to the first
1007 * descriptor when the first packet is transmitted.
1008 */
1009 for (i = 0; i < EPIC_NTXDESC; i++) {
1010 txd = EPIC_CDTX(sc, i);
1011 memset(txd, 0, sizeof(struct epic_txdesc));
1012 txd->et_bufaddr = EPIC_CDFLADDR(sc, i);
1013 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i));
1014 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
1015 }
1016 sc->sc_txpending = 0;
1017 sc->sc_txdirty = 0;
1018 sc->sc_txlast = EPIC_NTXDESC - 1;
1019
1020 /*
1021 * Initialize the receive descriptor ring.
1022 */
1023 for (i = 0; i < EPIC_NRXDESC; i++) {
1024 ds = EPIC_DSRX(sc, i);
1025 if (ds->ds_mbuf == NULL) {
1026 if ((error = epic_add_rxbuf(sc, i)) != 0) {
1027 printf("%s: unable to allocate or map rx "
1028 "buffer %d error = %d\n",
1029 sc->sc_dev.dv_xname, i, error);
1030 /*
1031 * XXX Should attempt to run with fewer receive
1032 * XXX buffers instead of just failing.
1033 */
1034 epic_rxdrain(sc);
1035 goto out;
1036 }
1037 } else
1038 EPIC_INIT_RXDESC(sc, i);
1039 }
1040 sc->sc_rxptr = 0;
1041
1042 /*
1043 * Initialize the interrupt mask and enable interrupts.
1044 */
1045 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK);
1046 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA);
1047
1048 /*
1049 * Give the transmit and receive rings to the EPIC.
1050 */
1051 bus_space_write_4(st, sh, EPIC_PTCDAR,
1052 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast)));
1053 bus_space_write_4(st, sh, EPIC_PRCDAR,
1054 EPIC_CDRXADDR(sc, sc->sc_rxptr));
1055
1056 /*
1057 * Set the EPIC in motion.
1058 */
1059 bus_space_write_4(st, sh, EPIC_COMMAND,
1060 COMMAND_RXQUEUED | COMMAND_START_RX);
1061
1062 /*
1063 * ...all done!
1064 */
1065 ifp->if_flags |= IFF_RUNNING;
1066 ifp->if_flags &= ~IFF_OACTIVE;
1067
1068 /*
1069 * Start the one second clock.
1070 */
1071 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc);
1072
1073 /*
1074 * Attempt to start output on the interface.
1075 */
1076 epic_start(ifp);
1077
1078 out:
1079 if (error)
1080 printf("%s: interface not running\n", sc->sc_dev.dv_xname);
1081 return (error);
1082 }
1083
1084 /*
1085 * Drain the receive queue.
1086 */
1087 void
1088 epic_rxdrain(sc)
1089 struct epic_softc *sc;
1090 {
1091 struct epic_descsoft *ds;
1092 int i;
1093
1094 for (i = 0; i < EPIC_NRXDESC; i++) {
1095 ds = EPIC_DSRX(sc, i);
1096 if (ds->ds_mbuf != NULL) {
1097 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
1098 m_freem(ds->ds_mbuf);
1099 ds->ds_mbuf = NULL;
1100 }
1101 }
1102 }
1103
1104 /*
1105 * Stop transmission on the interface.
1106 */
1107 void
1108 epic_stop(ifp, disable)
1109 struct ifnet *ifp;
1110 int disable;
1111 {
1112 struct epic_softc *sc = ifp->if_softc;
1113 bus_space_tag_t st = sc->sc_st;
1114 bus_space_handle_t sh = sc->sc_sh;
1115 struct epic_descsoft *ds;
1116 uint32_t reg;
1117 int i;
1118
1119 /*
1120 * Stop the one second clock.
1121 */
1122 callout_stop(&sc->sc_mii_callout);
1123
1124 /* Down the MII. */
1125 mii_down(&sc->sc_mii);
1126
1127 /* Paranoia... */
1128 epic_fixup_clock_source(sc);
1129
1130 /*
1131 * Disable interrupts.
1132 */
1133 reg = bus_space_read_4(st, sh, EPIC_GENCTL);
1134 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA);
1135 bus_space_write_4(st, sh, EPIC_INTMASK, 0);
1136
1137 /*
1138 * Stop the DMA engine and take the receiver off-line.
1139 */
1140 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA |
1141 COMMAND_STOP_TDMA | COMMAND_STOP_RX);
1142
1143 /*
1144 * Release any queued transmit buffers.
1145 */
1146 for (i = 0; i < EPIC_NTXDESC; i++) {
1147 ds = EPIC_DSTX(sc, i);
1148 if (ds->ds_mbuf != NULL) {
1149 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
1150 m_freem(ds->ds_mbuf);
1151 ds->ds_mbuf = NULL;
1152 }
1153 }
1154
1155 if (disable)
1156 epic_rxdrain(sc);
1157
1158 /*
1159 * Mark the interface down and cancel the watchdog timer.
1160 */
1161 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1162 ifp->if_timer = 0;
1163 }
1164
1165 /*
1166 * Read the EPIC Serial EEPROM.
1167 */
1168 void
1169 epic_read_eeprom(sc, word, wordcnt, data)
1170 struct epic_softc *sc;
1171 int word, wordcnt;
1172 uint16_t *data;
1173 {
1174 bus_space_tag_t st = sc->sc_st;
1175 bus_space_handle_t sh = sc->sc_sh;
1176 uint16_t reg;
1177 int i, x;
1178
1179 #define EEPROM_WAIT_READY(st, sh) \
1180 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \
1181 /* nothing */
1182
1183 /*
1184 * Enable the EEPROM.
1185 */
1186 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE);
1187 EEPROM_WAIT_READY(st, sh);
1188
1189 for (i = 0; i < wordcnt; i++) {
1190 /* Send CHIP SELECT for one clock tick. */
1191 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS);
1192 EEPROM_WAIT_READY(st, sh);
1193
1194 /* Shift in the READ opcode. */
1195 for (x = 3; x > 0; x--) {
1196 reg = EECTL_ENABLE|EECTL_EECS;
1197 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1)))
1198 reg |= EECTL_EEDI;
1199 bus_space_write_4(st, sh, EPIC_EECTL, reg);
1200 EEPROM_WAIT_READY(st, sh);
1201 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
1202 EEPROM_WAIT_READY(st, sh);
1203 bus_space_write_4(st, sh, EPIC_EECTL, reg);
1204 EEPROM_WAIT_READY(st, sh);
1205 }
1206
1207 /* Shift in address. */
1208 for (x = 6; x > 0; x--) {
1209 reg = EECTL_ENABLE|EECTL_EECS;
1210 if ((word + i) & (1 << (x - 1)))
1211 reg |= EECTL_EEDI;
1212 bus_space_write_4(st, sh, EPIC_EECTL, reg);
1213 EEPROM_WAIT_READY(st, sh);
1214 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
1215 EEPROM_WAIT_READY(st, sh);
1216 bus_space_write_4(st, sh, EPIC_EECTL, reg);
1217 EEPROM_WAIT_READY(st, sh);
1218 }
1219
1220 /* Shift out data. */
1221 reg = EECTL_ENABLE|EECTL_EECS;
1222 data[i] = 0;
1223 for (x = 16; x > 0; x--) {
1224 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
1225 EEPROM_WAIT_READY(st, sh);
1226 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO)
1227 data[i] |= (1 << (x - 1));
1228 bus_space_write_4(st, sh, EPIC_EECTL, reg);
1229 EEPROM_WAIT_READY(st, sh);
1230 }
1231
1232 /* Clear CHIP SELECT. */
1233 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE);
1234 EEPROM_WAIT_READY(st, sh);
1235 }
1236
1237 /*
1238 * Disable the EEPROM.
1239 */
1240 bus_space_write_4(st, sh, EPIC_EECTL, 0);
1241
1242 #undef EEPROM_WAIT_READY
1243 }
1244
1245 /*
1246 * Add a receive buffer to the indicated descriptor.
1247 */
1248 int
1249 epic_add_rxbuf(sc, idx)
1250 struct epic_softc *sc;
1251 int idx;
1252 {
1253 struct epic_descsoft *ds = EPIC_DSRX(sc, idx);
1254 struct mbuf *m;
1255 int error;
1256
1257 MGETHDR(m, M_DONTWAIT, MT_DATA);
1258 if (m == NULL)
1259 return (ENOBUFS);
1260
1261 MCLGET(m, M_DONTWAIT);
1262 if ((m->m_flags & M_EXT) == 0) {
1263 m_freem(m);
1264 return (ENOBUFS);
1265 }
1266
1267 if (ds->ds_mbuf != NULL)
1268 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
1269
1270 ds->ds_mbuf = m;
1271
1272 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap,
1273 m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
1274 BUS_DMA_READ|BUS_DMA_NOWAIT);
1275 if (error) {
1276 printf("%s: can't load rx DMA map %d, error = %d\n",
1277 sc->sc_dev.dv_xname, idx, error);
1278 panic("epic_add_rxbuf"); /* XXX */
1279 }
1280
1281 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
1282 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
1283
1284 EPIC_INIT_RXDESC(sc, idx);
1285
1286 return (0);
1287 }
1288
1289 /*
1290 * Set the EPIC multicast hash table.
1291 *
1292 * NOTE: We rely on a recently-updated mii_media_active here!
1293 */
1294 void
1295 epic_set_mchash(sc)
1296 struct epic_softc *sc;
1297 {
1298 struct ethercom *ec = &sc->sc_ethercom;
1299 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
1300 struct ether_multi *enm;
1301 struct ether_multistep step;
1302 uint32_t hash, mchash[4];
1303
1304 /*
1305 * Set up the multicast address filter by passing all multicast
1306 * addresses through a CRC generator, and then using the low-order
1307 * 6 bits as an index into the 64 bit multicast hash table (only
1308 * the lower 16 bits of each 32 bit multicast hash register are
1309 * valid). The high order bits select the register, while the
1310 * rest of the bits select the bit within the register.
1311 */
1312
1313 if (ifp->if_flags & IFF_PROMISC)
1314 goto allmulti;
1315
1316 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) {
1317 /* XXX hardware bug in 10Mbps mode. */
1318 goto allmulti;
1319 }
1320
1321 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0;
1322
1323 ETHER_FIRST_MULTI(step, ec, enm);
1324 while (enm != NULL) {
1325 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
1326 /*
1327 * We must listen to a range of multicast addresses.
1328 * For now, just accept all multicasts, rather than
1329 * trying to set only those filter bits needed to match
1330 * the range. (At this time, the only use of address
1331 * ranges is for IP multicast routing, for which the
1332 * range is big enough to require all bits set.)
1333 */
1334 goto allmulti;
1335 }
1336
1337 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
1338 hash >>= 26;
1339
1340 /* Set the corresponding bit in the hash table. */
1341 mchash[hash >> 4] |= 1 << (hash & 0xf);
1342
1343 ETHER_NEXT_MULTI(step, enm);
1344 }
1345
1346 ifp->if_flags &= ~IFF_ALLMULTI;
1347 goto sethash;
1348
1349 allmulti:
1350 ifp->if_flags |= IFF_ALLMULTI;
1351 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff;
1352
1353 sethash:
1354 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]);
1355 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]);
1356 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]);
1357 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]);
1358 }
1359
1360 /*
1361 * Wait for the MII to become ready.
1362 */
1363 int
1364 epic_mii_wait(sc, rw)
1365 struct epic_softc *sc;
1366 uint32_t rw;
1367 {
1368 int i;
1369
1370 for (i = 0; i < 50; i++) {
1371 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw)
1372 == 0)
1373 break;
1374 delay(2);
1375 }
1376 if (i == 50) {
1377 printf("%s: MII timed out\n", sc->sc_dev.dv_xname);
1378 return (1);
1379 }
1380
1381 return (0);
1382 }
1383
1384 /*
1385 * Read from the MII.
1386 */
1387 int
1388 epic_mii_read(self, phy, reg)
1389 struct device *self;
1390 int phy, reg;
1391 {
1392 struct epic_softc *sc = (struct epic_softc *)self;
1393
1394 if (epic_mii_wait(sc, MMCTL_WRITE))
1395 return (0);
1396
1397 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL,
1398 MMCTL_ARG(phy, reg, MMCTL_READ));
1399
1400 if (epic_mii_wait(sc, MMCTL_READ))
1401 return (0);
1402
1403 return (bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) &
1404 MMDATA_MASK);
1405 }
1406
1407 /*
1408 * Write to the MII.
1409 */
1410 void
1411 epic_mii_write(self, phy, reg, val)
1412 struct device *self;
1413 int phy, reg, val;
1414 {
1415 struct epic_softc *sc = (struct epic_softc *)self;
1416
1417 if (epic_mii_wait(sc, MMCTL_WRITE))
1418 return;
1419
1420 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val);
1421 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL,
1422 MMCTL_ARG(phy, reg, MMCTL_WRITE));
1423 }
1424
1425 /*
1426 * Callback from PHY when media changes.
1427 */
1428 void
1429 epic_statchg(self)
1430 struct device *self;
1431 {
1432 struct epic_softc *sc = (struct epic_softc *)self;
1433 uint32_t txcon, miicfg;
1434
1435 /*
1436 * Update loopback bits in TXCON to reflect duplex mode.
1437 */
1438 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON);
1439 if (sc->sc_mii.mii_media_active & IFM_FDX)
1440 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2);
1441 else
1442 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2);
1443 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon);
1444
1445 /* On some cards we need manualy set fullduplex led */
1446 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) {
1447 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG);
1448 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX)
1449 miicfg |= MIICFG_ENABLE;
1450 else
1451 miicfg &= ~MIICFG_ENABLE;
1452 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg);
1453 }
1454
1455 /*
1456 * There is a multicast filter bug in 10Mbps mode. Kick the
1457 * multicast filter in case the speed changed.
1458 */
1459 epic_set_mchash(sc);
1460 }
1461
1462 /*
1463 * Callback from ifmedia to request current media status.
1464 */
1465 void
1466 epic_mediastatus(ifp, ifmr)
1467 struct ifnet *ifp;
1468 struct ifmediareq *ifmr;
1469 {
1470 struct epic_softc *sc = ifp->if_softc;
1471
1472 mii_pollstat(&sc->sc_mii);
1473 ifmr->ifm_status = sc->sc_mii.mii_media_status;
1474 ifmr->ifm_active = sc->sc_mii.mii_media_active;
1475 }
1476
1477 /*
1478 * Callback from ifmedia to request new media setting.
1479 */
1480 int
1481 epic_mediachange(ifp)
1482 struct ifnet *ifp;
1483 {
1484 struct epic_softc *sc = ifp->if_softc;
1485 struct mii_data *mii = &sc->sc_mii;
1486 struct ifmedia *ifm = &mii->mii_media;
1487 int media = ifm->ifm_cur->ifm_media;
1488 uint32_t miicfg;
1489 struct mii_softc *miisc;
1490 int cfg;
1491
1492 if (!(ifp->if_flags & IFF_UP))
1493 return (0);
1494
1495 if (IFM_INST(media) != sc->sc_serinst) {
1496 /* If we're not selecting serial interface, select MII mode */
1497 #ifdef EPICMEDIADEBUG
1498 printf("%s: parallel mode\n", ifp->if_xname);
1499 #endif
1500 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG);
1501 miicfg &= ~MIICFG_SERMODEENA;
1502 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg);
1503 }
1504
1505 mii_mediachg(mii);
1506
1507 if (IFM_INST(media) == sc->sc_serinst) {
1508 /* select serial interface */
1509 #ifdef EPICMEDIADEBUG
1510 printf("%s: serial mode\n", ifp->if_xname);
1511 #endif
1512 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG);
1513 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE);
1514 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg);
1515
1516 /* There is no driver to fill this */
1517 mii->mii_media_active = media;
1518 mii->mii_media_status = 0;
1519
1520 epic_statchg(&sc->sc_dev);
1521 return (0);
1522 }
1523
1524 /* Lookup selected PHY */
1525 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1526 miisc = LIST_NEXT(miisc, mii_list)) {
1527 if (IFM_INST(media) == miisc->mii_inst)
1528 break;
1529 }
1530 if (!miisc) {
1531 printf("epic_mediachange: can't happen\n"); /* ??? panic */
1532 return (0);
1533 }
1534 #ifdef EPICMEDIADEBUG
1535 printf("%s: using phy %s\n", ifp->if_xname,
1536 miisc->mii_dev.dv_xname);
1537 #endif
1538
1539 if (miisc->mii_flags & MIIF_HAVEFIBER) {
1540 /* XXX XXX assume it's a Level1 - should check */
1541
1542 /* We have to powerup fiber transceivers */
1543 cfg = PHY_READ(miisc, MII_LXTPHY_CONFIG);
1544 if (IFM_SUBTYPE(media) == IFM_100_FX) {
1545 #ifdef EPICMEDIADEBUG
1546 printf("%s: power up fiber\n", ifp->if_xname);
1547 #endif
1548 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0);
1549 } else {
1550 #ifdef EPICMEDIADEBUG
1551 printf("%s: power down fiber\n", ifp->if_xname);
1552 #endif
1553 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
1554 }
1555 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg);
1556 }
1557
1558 return (0);
1559 }
Cache object: 540f67eb9dc7ea5f15f3c55907ff5295
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