The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/dev/ic/smc83c170.c

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    1 /*      $NetBSD: smc83c170.c,v 1.76 2008/07/06 14:32:56 tsutsui Exp $   */
    2 
    3 /*-
    4  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
    9  * NASA Ames Research Center.
   10  *
   11  * Redistribution and use in source and binary forms, with or without
   12  * modification, are permitted provided that the following conditions
   13  * are met:
   14  * 1. Redistributions of source code must retain the above copyright
   15  *    notice, this list of conditions and the following disclaimer.
   16  * 2. Redistributions in binary form must reproduce the above copyright
   17  *    notice, this list of conditions and the following disclaimer in the
   18  *    documentation and/or other materials provided with the distribution.
   19  *
   20  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   22  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   23  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   30  * POSSIBILITY OF SUCH DAMAGE.
   31  */
   32 
   33 /*
   34  * Device driver for the Standard Microsystems Corp. 83C170
   35  * Ethernet PCI Integrated Controller (EPIC/100).
   36  */
   37 
   38 #include <sys/cdefs.h>
   39 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.76 2008/07/06 14:32:56 tsutsui Exp $");
   40 
   41 #include "bpfilter.h"
   42 
   43 #include <sys/param.h>
   44 #include <sys/systm.h>
   45 #include <sys/callout.h>
   46 #include <sys/mbuf.h>
   47 #include <sys/malloc.h>
   48 #include <sys/kernel.h>
   49 #include <sys/socket.h>
   50 #include <sys/ioctl.h>
   51 #include <sys/errno.h>
   52 #include <sys/device.h>
   53 
   54 #include <uvm/uvm_extern.h>
   55 
   56 #include <net/if.h>
   57 #include <net/if_dl.h>
   58 #include <net/if_media.h>
   59 #include <net/if_ether.h>
   60 
   61 #if NBPFILTER > 0
   62 #include <net/bpf.h>
   63 #endif
   64 
   65 #include <sys/bus.h>
   66 #include <sys/intr.h>
   67 
   68 #include <dev/mii/miivar.h>
   69 #include <dev/mii/lxtphyreg.h>
   70 
   71 #include <dev/ic/smc83c170reg.h>
   72 #include <dev/ic/smc83c170var.h>
   73 
   74 void    epic_start(struct ifnet *);
   75 void    epic_watchdog(struct ifnet *);
   76 int     epic_ioctl(struct ifnet *, u_long, void *);
   77 int     epic_init(struct ifnet *);
   78 void    epic_stop(struct ifnet *, int);
   79 
   80 void    epic_shutdown(void *);
   81 
   82 void    epic_reset(struct epic_softc *);
   83 void    epic_rxdrain(struct epic_softc *);
   84 int     epic_add_rxbuf(struct epic_softc *, int);
   85 void    epic_read_eeprom(struct epic_softc *, int, int, uint16_t *);
   86 void    epic_set_mchash(struct epic_softc *);
   87 void    epic_fixup_clock_source(struct epic_softc *);
   88 int     epic_mii_read(device_t, int, int);
   89 void    epic_mii_write(device_t, int, int, int);
   90 int     epic_mii_wait(struct epic_softc *, uint32_t);
   91 void    epic_tick(void *);
   92 
   93 void    epic_statchg(device_t);
   94 int     epic_mediachange(struct ifnet *);
   95 
   96 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \
   97             INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC)
   98 
   99 int     epic_copy_small = 0;
  100 
  101 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)
  102 
  103 /*
  104  * Attach an EPIC interface to the system.
  105  */
  106 void
  107 epic_attach(struct epic_softc *sc)
  108 {
  109         bus_space_tag_t st = sc->sc_st;
  110         bus_space_handle_t sh = sc->sc_sh;
  111         struct ifnet *ifp = &sc->sc_ethercom.ec_if;
  112         int rseg, error, miiflags;
  113         u_int i;
  114         bus_dma_segment_t seg;
  115         uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1];
  116         uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6];
  117         char *nullbuf;
  118 
  119         callout_init(&sc->sc_mii_callout, 0);
  120 
  121         /*
  122          * Allocate the control data structures, and create and load the
  123          * DMA map for it.
  124          */
  125         if ((error = bus_dmamem_alloc(sc->sc_dmat,
  126             sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0,
  127             &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) {
  128                 aprint_error_dev(sc->sc_dev, 
  129                     "unable to allocate control data, error = %d\n", error);
  130                 goto fail_0;
  131         }
  132 
  133         if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg,
  134             sizeof(struct epic_control_data) + ETHER_PAD_LEN,
  135             (void **)&sc->sc_control_data,
  136             BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
  137                 aprint_error_dev(sc->sc_dev,
  138                     "unable to map control data, error = %d\n", error);
  139                 goto fail_1;
  140         }
  141         nullbuf =
  142             (char *)sc->sc_control_data + sizeof(struct epic_control_data);
  143         memset(nullbuf, 0, ETHER_PAD_LEN);
  144 
  145         if ((error = bus_dmamap_create(sc->sc_dmat,
  146             sizeof(struct epic_control_data), 1,
  147             sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT,
  148             &sc->sc_cddmamap)) != 0) {
  149                 aprint_error_dev(sc->sc_dev,
  150                     "unable to create control data DMA map, error = %d\n",
  151                     error);
  152                 goto fail_2;
  153         }
  154 
  155         if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap,
  156             sc->sc_control_data, sizeof(struct epic_control_data), NULL,
  157             BUS_DMA_NOWAIT)) != 0) {
  158                 aprint_error_dev(sc->sc_dev, 
  159                     "unable to load control data DMA map, error = %d\n",
  160                     error);
  161                 goto fail_3;
  162         }
  163 
  164         /*
  165          * Create the transmit buffer DMA maps.
  166          */
  167         for (i = 0; i < EPIC_NTXDESC; i++) {
  168                 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES,
  169                     EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT,
  170                     &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) {
  171                         aprint_error_dev(sc->sc_dev,
  172                             "unable to create tx DMA map %d, error = %d\n",
  173                             i, error);
  174                         goto fail_4;
  175                 }
  176         }
  177 
  178         /*
  179          * Create the receive buffer DMA maps.
  180          */
  181         for (i = 0; i < EPIC_NRXDESC; i++) {
  182                 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1,
  183                     MCLBYTES, 0, BUS_DMA_NOWAIT,
  184                     &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) {
  185                         aprint_error_dev(sc->sc_dev,
  186                             "unable to create rx DMA map %d, error = %d\n",
  187                             i, error);
  188                         goto fail_5;
  189                 }
  190                 EPIC_DSRX(sc, i)->ds_mbuf = NULL;
  191         }
  192 
  193         /*
  194          * create and map the pad buffer
  195          */
  196         if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1,
  197             ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) {
  198                 aprint_error_dev(sc->sc_dev,
  199                     "unable to create pad buffer DMA map, error = %d\n", error);
  200                 goto fail_5;
  201         }
  202 
  203         if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap,
  204             nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) {
  205                 aprint_error_dev(sc->sc_dev,
  206                     "unable to load pad buffer DMA map, error = %d\n", error);
  207                 goto fail_6;
  208         }
  209         bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN,
  210             BUS_DMASYNC_PREWRITE);
  211 
  212         /*
  213          * Bring the chip out of low-power mode and reset it to a known state.
  214          */
  215         bus_space_write_4(st, sh, EPIC_GENCTL, 0);
  216         epic_reset(sc);
  217 
  218         /*
  219          * Read the Ethernet address from the EEPROM.
  220          */
  221         epic_read_eeprom(sc, 0, __arraycount(myea), myea);
  222         for (i = 0; i < __arraycount(myea); i++) {
  223                 enaddr[i * 2]     = myea[i] & 0xff;
  224                 enaddr[i * 2 + 1] = myea[i] >> 8;
  225         }
  226 
  227         /*
  228          * ...and the device name.
  229          */
  230         epic_read_eeprom(sc, 0x2c, __arraycount(mydevname), mydevname);
  231         for (i = 0; i < __arraycount(mydevname); i++) {
  232                 devname[i * 2]     = mydevname[i] & 0xff;
  233                 devname[i * 2 + 1] = mydevname[i] >> 8;
  234         }
  235 
  236         devname[sizeof(mydevname)] = '\0';
  237         for (i = sizeof(mydevname) ; i > 0; i--) {
  238                 if (devname[i - 1] == ' ')
  239                         devname[i - 1] = '\0';
  240                 else
  241                         break;
  242         }
  243 
  244         aprint_normal_dev(sc->sc_dev, "%s, Ethernet address %s\n",
  245             devname, ether_sprintf(enaddr));
  246 
  247         miiflags = 0;
  248         if (sc->sc_hwflags & EPIC_HAS_MII_FIBER)
  249                 miiflags |= MIIF_HAVEFIBER;
  250 
  251         /*
  252          * Initialize our media structures and probe the MII.
  253          */
  254         sc->sc_mii.mii_ifp = ifp;
  255         sc->sc_mii.mii_readreg = epic_mii_read;
  256         sc->sc_mii.mii_writereg = epic_mii_write;
  257         sc->sc_mii.mii_statchg = epic_statchg;
  258 
  259         sc->sc_ethercom.ec_mii = &sc->sc_mii;
  260         ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epic_mediachange,
  261             ether_mediastatus);
  262         mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
  263             MII_OFFSET_ANY, miiflags);
  264         if (LIST_EMPTY(&sc->sc_mii.mii_phys)) {
  265                 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
  266                 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
  267         } else
  268                 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
  269 
  270         if (sc->sc_hwflags & EPIC_HAS_BNC) {
  271                 /* use the next free media instance */
  272                 sc->sc_serinst = sc->sc_mii.mii_instance++;
  273                 ifmedia_add(&sc->sc_mii.mii_media,
  274                     IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->sc_serinst),
  275                     0, NULL);
  276                 aprint_normal_dev(sc->sc_dev, "10base2/BNC\n");
  277         } else
  278                 sc->sc_serinst = -1;
  279 
  280         strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
  281         ifp->if_softc = sc;
  282         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
  283         ifp->if_ioctl = epic_ioctl;
  284         ifp->if_start = epic_start;
  285         ifp->if_watchdog = epic_watchdog;
  286         ifp->if_init = epic_init;
  287         ifp->if_stop = epic_stop;
  288         IFQ_SET_READY(&ifp->if_snd);
  289 
  290         /*
  291          * We can support 802.1Q VLAN-sized frames.
  292          */
  293         sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
  294 
  295         /*
  296          * Attach the interface.
  297          */
  298         if_attach(ifp);
  299         ether_ifattach(ifp, enaddr);
  300 
  301         /*
  302          * Make sure the interface is shutdown during reboot.
  303          */
  304         sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc);
  305         if (sc->sc_sdhook == NULL)
  306                 aprint_error_dev(sc->sc_dev,
  307                     "WARNING: unable to establish shutdown hook\n");
  308         return;
  309 
  310         /*
  311          * Free any resources we've allocated during the failed attach
  312          * attempt.  Do this in reverse order and fall through.
  313          */
  314  fail_6:
  315         bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap);
  316  fail_5:
  317         for (i = 0; i < EPIC_NRXDESC; i++) {
  318                 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL)
  319                         bus_dmamap_destroy(sc->sc_dmat,
  320                             EPIC_DSRX(sc, i)->ds_dmamap);
  321         }
  322  fail_4:
  323         for (i = 0; i < EPIC_NTXDESC; i++) {
  324                 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL)
  325                         bus_dmamap_destroy(sc->sc_dmat,
  326                             EPIC_DSTX(sc, i)->ds_dmamap);
  327         }
  328         bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap);
  329  fail_3:
  330         bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap);
  331  fail_2:
  332         bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data,
  333             sizeof(struct epic_control_data));
  334  fail_1:
  335         bus_dmamem_free(sc->sc_dmat, &seg, rseg);
  336  fail_0:
  337         return;
  338 }
  339 
  340 /*
  341  * Shutdown hook.  Make sure the interface is stopped at reboot.
  342  */
  343 void
  344 epic_shutdown(void *arg)
  345 {
  346         struct epic_softc *sc = arg;
  347 
  348         epic_stop(&sc->sc_ethercom.ec_if, 1);
  349 }
  350 
  351 /*
  352  * Start packet transmission on the interface.
  353  * [ifnet interface function]
  354  */
  355 void
  356 epic_start(struct ifnet *ifp)
  357 {
  358         struct epic_softc *sc = ifp->if_softc;
  359         struct mbuf *m0, *m;
  360         struct epic_txdesc *txd;
  361         struct epic_descsoft *ds;
  362         struct epic_fraglist *fr;
  363         bus_dmamap_t dmamap;
  364         int error, firsttx, nexttx, opending, seg;
  365         u_int len;
  366 
  367         /*
  368          * Remember the previous txpending and the first transmit
  369          * descriptor we use.
  370          */
  371         opending = sc->sc_txpending;
  372         firsttx = EPIC_NEXTTX(sc->sc_txlast);
  373 
  374         /*
  375          * Loop through the send queue, setting up transmit descriptors
  376          * until we drain the queue, or use up all available transmit
  377          * descriptors.
  378          */
  379         while (sc->sc_txpending < EPIC_NTXDESC) {
  380                 /*
  381                  * Grab a packet off the queue.
  382                  */
  383                 IFQ_POLL(&ifp->if_snd, m0);
  384                 if (m0 == NULL)
  385                         break;
  386                 m = NULL;
  387 
  388                 /*
  389                  * Get the last and next available transmit descriptor.
  390                  */
  391                 nexttx = EPIC_NEXTTX(sc->sc_txlast);
  392                 txd = EPIC_CDTX(sc, nexttx);
  393                 fr = EPIC_CDFL(sc, nexttx);
  394                 ds = EPIC_DSTX(sc, nexttx);
  395                 dmamap = ds->ds_dmamap;
  396 
  397                 /*
  398                  * Load the DMA map.  If this fails, the packet either
  399                  * didn't fit in the alloted number of frags, or we were
  400                  * short on resources.  In this case, we'll copy and try
  401                  * again.
  402                  */
  403                 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0,
  404                     BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 ||
  405                     (m0->m_pkthdr.len < ETHER_PAD_LEN &&
  406                     dmamap-> dm_nsegs == EPIC_NFRAGS)) {
  407                         if (error == 0)
  408                                 bus_dmamap_unload(sc->sc_dmat, dmamap);
  409 
  410                         MGETHDR(m, M_DONTWAIT, MT_DATA);
  411                         if (m == NULL) {
  412                                 printf("%s: unable to allocate Tx mbuf\n",
  413                                     device_xname(sc->sc_dev));
  414                                 break;
  415                         }
  416                         if (m0->m_pkthdr.len > MHLEN) {
  417                                 MCLGET(m, M_DONTWAIT);
  418                                 if ((m->m_flags & M_EXT) == 0) {
  419                                         printf("%s: unable to allocate Tx "
  420                                             "cluster\n",
  421                                             device_xname(sc->sc_dev));
  422                                         m_freem(m);
  423                                         break;
  424                                 }
  425                         }
  426                         m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *));
  427                         m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len;
  428                         error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap,
  429                             m, BUS_DMA_WRITE|BUS_DMA_NOWAIT);
  430                         if (error) {
  431                                 printf("%s: unable to load Tx buffer, "
  432                                     "error = %d\n", device_xname(sc->sc_dev),
  433                                     error);
  434                                 break;
  435                         }
  436                 }
  437                 IFQ_DEQUEUE(&ifp->if_snd, m0);
  438                 if (m != NULL) {
  439                         m_freem(m0);
  440                         m0 = m;
  441                 }
  442 
  443                 /* Initialize the fraglist. */
  444                 for (seg = 0; seg < dmamap->dm_nsegs; seg++) {
  445                         fr->ef_frags[seg].ef_addr =
  446                             dmamap->dm_segs[seg].ds_addr;
  447                         fr->ef_frags[seg].ef_length =
  448                             dmamap->dm_segs[seg].ds_len;
  449                 }
  450                 len = m0->m_pkthdr.len;
  451                 if (len < ETHER_PAD_LEN) {
  452                         fr->ef_frags[seg].ef_addr = sc->sc_nulldma;
  453                         fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len;
  454                         len = ETHER_PAD_LEN;
  455                         seg++;
  456                 }
  457                 fr->ef_nfrags = seg;
  458 
  459                 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE);
  460 
  461                 /* Sync the DMA map. */
  462                 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize,
  463                     BUS_DMASYNC_PREWRITE);
  464 
  465                 /*
  466                  * Store a pointer to the packet so we can free it later.
  467                  */
  468                 ds->ds_mbuf = m0;
  469 
  470                 /*
  471                  * Fill in the transmit descriptor.
  472                  */
  473                 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST;
  474 
  475                 /*
  476                  * If this is the first descriptor we're enqueueing,
  477                  * don't give it to the EPIC yet.  That could cause
  478                  * a race condition.  We'll do it below.
  479                  */
  480                 if (nexttx == firsttx)
  481                         txd->et_txstatus = TXSTAT_TXLENGTH(len);
  482                 else
  483                         txd->et_txstatus =
  484                             TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER;
  485 
  486                 EPIC_CDTXSYNC(sc, nexttx,
  487                     BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  488 
  489                 /* Advance the tx pointer. */
  490                 sc->sc_txpending++;
  491                 sc->sc_txlast = nexttx;
  492 
  493 #if NBPFILTER > 0
  494                 /*
  495                  * Pass the packet to any BPF listeners.
  496                  */
  497                 if (ifp->if_bpf)
  498                         bpf_mtap(ifp->if_bpf, m0);
  499 #endif
  500         }
  501 
  502         if (sc->sc_txpending == EPIC_NTXDESC) {
  503                 /* No more slots left; notify upper layer. */
  504                 ifp->if_flags |= IFF_OACTIVE;
  505         }
  506 
  507         if (sc->sc_txpending != opending) {
  508                 /*
  509                  * We enqueued packets.  If the transmitter was idle,
  510                  * reset the txdirty pointer.
  511                  */
  512                 if (opending == 0)
  513                         sc->sc_txdirty = firsttx;
  514 
  515                 /*
  516                  * Cause a transmit interrupt to happen on the
  517                  * last packet we enqueued.
  518                  */
  519                 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF;
  520                 EPIC_CDTXSYNC(sc, sc->sc_txlast,
  521                     BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  522 
  523                 /*
  524                  * The entire packet chain is set up.  Give the
  525                  * first descriptor to the EPIC now.
  526                  */
  527                 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER;
  528                 EPIC_CDTXSYNC(sc, firsttx,
  529                     BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  530 
  531                 /* Start the transmitter. */
  532                 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND,
  533                     COMMAND_TXQUEUED);
  534 
  535                 /* Set a watchdog timer in case the chip flakes out. */
  536                 ifp->if_timer = 5;
  537         }
  538 }
  539 
  540 /*
  541  * Watchdog timer handler.
  542  * [ifnet interface function]
  543  */
  544 void
  545 epic_watchdog(struct ifnet *ifp)
  546 {
  547         struct epic_softc *sc = ifp->if_softc;
  548 
  549         printf("%s: device timeout\n", device_xname(sc->sc_dev));
  550         ifp->if_oerrors++;
  551 
  552         (void)epic_init(ifp);
  553 }
  554 
  555 /*
  556  * Handle control requests from the operator.
  557  * [ifnet interface function]
  558  */
  559 int
  560 epic_ioctl(struct ifnet *ifp, u_long cmd, void *data)
  561 {
  562         struct epic_softc *sc = ifp->if_softc;
  563         int s, error;
  564 
  565         s = splnet();
  566 
  567         error = ether_ioctl(ifp, cmd, data);
  568         if (error == ENETRESET) {
  569                 /*
  570                  * Multicast list has changed; set the hardware filter
  571                  * accordingly.  Update our idea of the current media;
  572                  * epic_set_mchash() needs to know what it is.
  573                  */
  574                 if (ifp->if_flags & IFF_RUNNING) {
  575                         mii_pollstat(&sc->sc_mii);
  576                         epic_set_mchash(sc);
  577                 }
  578                 error = 0;
  579         }
  580 
  581         splx(s);
  582         return error;
  583 }
  584 
  585 /*
  586  * Interrupt handler.
  587  */
  588 int
  589 epic_intr(void *arg)
  590 {
  591         struct epic_softc *sc = arg;
  592         struct ifnet *ifp = &sc->sc_ethercom.ec_if;
  593         struct epic_rxdesc *rxd;
  594         struct epic_txdesc *txd;
  595         struct epic_descsoft *ds;
  596         struct mbuf *m;
  597         uint32_t intstat, rxstatus, txstatus;
  598         int i, claimed = 0;
  599         u_int len;
  600 
  601  top:
  602         /*
  603          * Get the interrupt status from the EPIC.
  604          */
  605         intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT);
  606         if ((intstat & INTSTAT_INT_ACTV) == 0)
  607                 return claimed;
  608 
  609         claimed = 1;
  610 
  611         /*
  612          * Acknowledge the interrupt.
  613          */
  614         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT,
  615             intstat & INTMASK);
  616 
  617         /*
  618          * Check for receive interrupts.
  619          */
  620         if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) {
  621                 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) {
  622                         rxd = EPIC_CDRX(sc, i);
  623                         ds = EPIC_DSRX(sc, i);
  624 
  625                         EPIC_CDRXSYNC(sc, i,
  626                             BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
  627 
  628                         rxstatus = rxd->er_rxstatus;
  629                         if (rxstatus & ER_RXSTAT_OWNER) {
  630                                 /*
  631                                  * We have processed all of the
  632                                  * receive buffers.
  633                                  */
  634                                 break;
  635                         }
  636 
  637                         /*
  638                          * Make sure the packet arrived intact.  If an error
  639                          * occurred, update stats and reset the descriptor.
  640                          * The buffer will be reused the next time the
  641                          * descriptor comes up in the ring.
  642                          */
  643                         if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) {
  644                                 if (rxstatus & ER_RXSTAT_CRCERROR)
  645                                         printf("%s: CRC error\n",
  646                                             device_xname(sc->sc_dev));
  647                                 if (rxstatus & ER_RXSTAT_ALIGNERROR)
  648                                         printf("%s: alignment error\n",
  649                                             device_xname(sc->sc_dev));
  650                                 ifp->if_ierrors++;
  651                                 EPIC_INIT_RXDESC(sc, i);
  652                                 continue;
  653                         }
  654 
  655                         bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
  656                             ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD);
  657 
  658                         /*
  659                          * The EPIC includes the CRC with every packet;
  660                          * trim it.
  661                          */
  662                         len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN;
  663 
  664                         if (len < sizeof(struct ether_header)) {
  665                                 /*
  666                                  * Runt packet; drop it now.
  667                                  */
  668                                 ifp->if_ierrors++;
  669                                 EPIC_INIT_RXDESC(sc, i);
  670                                 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
  671                                     ds->ds_dmamap->dm_mapsize,
  672                                     BUS_DMASYNC_PREREAD);
  673                                 continue;
  674                         }
  675 
  676                         /*
  677                          * If the packet is small enough to fit in a
  678                          * single header mbuf, allocate one and copy
  679                          * the data into it.  This greatly reduces
  680                          * memory consumption when we receive lots
  681                          * of small packets.
  682                          *
  683                          * Otherwise, we add a new buffer to the receive
  684                          * chain.  If this fails, we drop the packet and
  685                          * recycle the old buffer.
  686                          */
  687                         if (epic_copy_small != 0 && len <= MHLEN) {
  688                                 MGETHDR(m, M_DONTWAIT, MT_DATA);
  689                                 if (m == NULL)
  690                                         goto dropit;
  691                                 memcpy(mtod(m, void *),
  692                                     mtod(ds->ds_mbuf, void *), len);
  693                                 EPIC_INIT_RXDESC(sc, i);
  694                                 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
  695                                     ds->ds_dmamap->dm_mapsize,
  696                                     BUS_DMASYNC_PREREAD);
  697                         } else {
  698                                 m = ds->ds_mbuf;
  699                                 if (epic_add_rxbuf(sc, i) != 0) {
  700  dropit:
  701                                         ifp->if_ierrors++;
  702                                         EPIC_INIT_RXDESC(sc, i);
  703                                         bus_dmamap_sync(sc->sc_dmat,
  704                                             ds->ds_dmamap, 0,
  705                                             ds->ds_dmamap->dm_mapsize,
  706                                             BUS_DMASYNC_PREREAD);
  707                                         continue;
  708                                 }
  709                         }
  710 
  711                         m->m_pkthdr.rcvif = ifp;
  712                         m->m_pkthdr.len = m->m_len = len;
  713 
  714 #if NBPFILTER > 0
  715                         /*
  716                          * Pass this up to any BPF listeners, but only
  717                          * pass it up the stack if it's for us.
  718                          */
  719                         if (ifp->if_bpf)
  720                                 bpf_mtap(ifp->if_bpf, m);
  721 #endif
  722 
  723                         /* Pass it on. */
  724                         (*ifp->if_input)(ifp, m);
  725                         ifp->if_ipackets++;
  726                 }
  727 
  728                 /* Update the receive pointer. */
  729                 sc->sc_rxptr = i;
  730 
  731                 /*
  732                  * Check for receive queue underflow.
  733                  */
  734                 if (intstat & INTSTAT_RQE) {
  735                         printf("%s: receiver queue empty\n",
  736                             device_xname(sc->sc_dev));
  737                         /*
  738                          * Ring is already built; just restart the
  739                          * receiver.
  740                          */
  741                         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR,
  742                             EPIC_CDRXADDR(sc, sc->sc_rxptr));
  743                         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND,
  744                             COMMAND_RXQUEUED | COMMAND_START_RX);
  745                 }
  746         }
  747 
  748         /*
  749          * Check for transmission complete interrupts.
  750          */
  751         if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) {
  752                 ifp->if_flags &= ~IFF_OACTIVE;
  753                 for (i = sc->sc_txdirty; sc->sc_txpending != 0;
  754                      i = EPIC_NEXTTX(i), sc->sc_txpending--) {
  755                         txd = EPIC_CDTX(sc, i);
  756                         ds = EPIC_DSTX(sc, i);
  757 
  758                         EPIC_CDTXSYNC(sc, i,
  759                             BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
  760 
  761                         txstatus = txd->et_txstatus;
  762                         if (txstatus & ET_TXSTAT_OWNER)
  763                                 break;
  764 
  765                         EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE);
  766 
  767                         bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap,
  768                             0, ds->ds_dmamap->dm_mapsize,
  769                             BUS_DMASYNC_POSTWRITE);
  770                         bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
  771                         m_freem(ds->ds_mbuf);
  772                         ds->ds_mbuf = NULL;
  773 
  774                         /*
  775                          * Check for errors and collisions.
  776                          */
  777                         if ((txstatus & ET_TXSTAT_PACKETTX) == 0)
  778                                 ifp->if_oerrors++;
  779                         else
  780                                 ifp->if_opackets++;
  781                         ifp->if_collisions +=
  782                             TXSTAT_COLLISIONS(txstatus);
  783                         if (txstatus & ET_TXSTAT_CARSENSELOST)
  784                                 printf("%s: lost carrier\n",
  785                                     device_xname(sc->sc_dev));
  786                 }
  787 
  788                 /* Update the dirty transmit buffer pointer. */
  789                 sc->sc_txdirty = i;
  790 
  791                 /*
  792                  * Cancel the watchdog timer if there are no pending
  793                  * transmissions.
  794                  */
  795                 if (sc->sc_txpending == 0)
  796                         ifp->if_timer = 0;
  797 
  798                 /*
  799                  * Kick the transmitter after a DMA underrun.
  800                  */
  801                 if (intstat & INTSTAT_TXU) {
  802                         printf("%s: transmit underrun\n",
  803                             device_xname(sc->sc_dev));
  804                         bus_space_write_4(sc->sc_st, sc->sc_sh,
  805                             EPIC_COMMAND, COMMAND_TXUGO);
  806                         if (sc->sc_txpending)
  807                                 bus_space_write_4(sc->sc_st, sc->sc_sh,
  808                                     EPIC_COMMAND, COMMAND_TXQUEUED);
  809                 }
  810 
  811                 /*
  812                  * Try to get more packets going.
  813                  */
  814                 epic_start(ifp);
  815         }
  816 
  817         /*
  818          * Check for fatal interrupts.
  819          */
  820         if (intstat & INTSTAT_FATAL_INT) {
  821                 if (intstat & INTSTAT_PTA)
  822                         printf("%s: PCI target abort error\n",
  823                             device_xname(sc->sc_dev));
  824                 else if (intstat & INTSTAT_PMA)
  825                         printf("%s: PCI master abort error\n",
  826                             device_xname(sc->sc_dev));
  827                 else if (intstat & INTSTAT_APE)
  828                         printf("%s: PCI address parity error\n",
  829                             device_xname(sc->sc_dev));
  830                 else if (intstat & INTSTAT_DPE)
  831                         printf("%s: PCI data parity error\n",
  832                             device_xname(sc->sc_dev));
  833                 else
  834                         printf("%s: unknown fatal error\n",
  835                             device_xname(sc->sc_dev));
  836                 (void)epic_init(ifp);
  837         }
  838 
  839         /*
  840          * Check for more interrupts.
  841          */
  842         goto top;
  843 }
  844 
  845 /*
  846  * One second timer, used to tick the MII.
  847  */
  848 void
  849 epic_tick(void *arg)
  850 {
  851         struct epic_softc *sc = arg;
  852         int s;
  853 
  854         s = splnet();
  855         mii_tick(&sc->sc_mii);
  856         splx(s);
  857 
  858         callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc);
  859 }
  860 
  861 /*
  862  * Fixup the clock source on the EPIC.
  863  */
  864 void
  865 epic_fixup_clock_source(struct epic_softc *sc)
  866 {
  867         int i;
  868 
  869         /*
  870          * According to SMC Application Note 7-15, the EPIC's clock
  871          * source is incorrect following a reset.  This manifests itself
  872          * as failure to recognize when host software has written to
  873          * a register on the EPIC.  The appnote recommends issuing at
  874          * least 16 consecutive writes to the CLOCK TEST bit to correctly
  875          * configure the clock source.
  876          */
  877         for (i = 0; i < 16; i++)
  878                 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST,
  879                     TEST_CLOCKTEST);
  880 }
  881 
  882 /*
  883  * Perform a soft reset on the EPIC.
  884  */
  885 void
  886 epic_reset(struct epic_softc *sc)
  887 {
  888 
  889         epic_fixup_clock_source(sc);
  890 
  891         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0);
  892         delay(100);
  893         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET);
  894         delay(100);
  895 
  896         epic_fixup_clock_source(sc);
  897 }
  898 
  899 /*
  900  * Initialize the interface.  Must be called at splnet().
  901  */
  902 int
  903 epic_init(struct ifnet *ifp)
  904 {
  905         struct epic_softc *sc = ifp->if_softc;
  906         bus_space_tag_t st = sc->sc_st;
  907         bus_space_handle_t sh = sc->sc_sh;
  908         const uint8_t *enaddr = CLLADDR(ifp->if_sadl);
  909         struct epic_txdesc *txd;
  910         struct epic_descsoft *ds;
  911         uint32_t genctl, reg0;
  912         int i, error = 0;
  913 
  914         /*
  915          * Cancel any pending I/O.
  916          */
  917         epic_stop(ifp, 0);
  918 
  919         /*
  920          * Reset the EPIC to a known state.
  921          */
  922         epic_reset(sc);
  923 
  924         /*
  925          * Magical mystery initialization.
  926          */
  927         bus_space_write_4(st, sh, EPIC_TXTEST, 0);
  928 
  929         /*
  930          * Initialize the EPIC genctl register:
  931          *
  932          *      - 64 byte receive FIFO threshold
  933          *      - automatic advance to next receive frame
  934          */
  935         genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY;
  936 #if BYTE_ORDER == BIG_ENDIAN
  937         genctl |= GENCTL_BIG_ENDIAN;
  938 #endif
  939         bus_space_write_4(st, sh, EPIC_GENCTL, genctl);
  940 
  941         /*
  942          * Reset the MII bus and PHY.
  943          */
  944         reg0 = bus_space_read_4(st, sh, EPIC_NVCTL);
  945         bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1);
  946         bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER);
  947         bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY);
  948         delay(100);
  949         bus_space_write_4(st, sh, EPIC_GENCTL, genctl);
  950         delay(1000);
  951         bus_space_write_4(st, sh, EPIC_NVCTL, reg0);
  952 
  953         /*
  954          * Initialize Ethernet address.
  955          */
  956         reg0 = enaddr[1] << 8 | enaddr[0];
  957         bus_space_write_4(st, sh, EPIC_LAN0, reg0);
  958         reg0 = enaddr[3] << 8 | enaddr[2];
  959         bus_space_write_4(st, sh, EPIC_LAN1, reg0);
  960         reg0 = enaddr[5] << 8 | enaddr[4];
  961         bus_space_write_4(st, sh, EPIC_LAN2, reg0);
  962 
  963         /*
  964          * Initialize receive control.  Remember the external buffer
  965          * size setting.
  966          */
  967         reg0 = bus_space_read_4(st, sh, EPIC_RXCON) &
  968             (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0);
  969         reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST);
  970         if (ifp->if_flags & IFF_PROMISC)
  971                 reg0 |= RXCON_PROMISCMODE;
  972         bus_space_write_4(st, sh, EPIC_RXCON, reg0);
  973 
  974         /* Set the current media. */
  975         if ((error = epic_mediachange(ifp)) != 0)
  976                 goto out;
  977 
  978         /* Set up the multicast hash table. */
  979         epic_set_mchash(sc);
  980 
  981         /*
  982          * Initialize the transmit descriptor ring.  txlast is initialized
  983          * to the end of the list so that it will wrap around to the first
  984          * descriptor when the first packet is transmitted.
  985          */
  986         for (i = 0; i < EPIC_NTXDESC; i++) {
  987                 txd = EPIC_CDTX(sc, i);
  988                 memset(txd, 0, sizeof(struct epic_txdesc));
  989                 txd->et_bufaddr = EPIC_CDFLADDR(sc, i);
  990                 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i));
  991                 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
  992         }
  993         sc->sc_txpending = 0;
  994         sc->sc_txdirty = 0;
  995         sc->sc_txlast = EPIC_NTXDESC - 1;
  996 
  997         /*
  998          * Initialize the receive descriptor ring.
  999          */
 1000         for (i = 0; i < EPIC_NRXDESC; i++) {
 1001                 ds = EPIC_DSRX(sc, i);
 1002                 if (ds->ds_mbuf == NULL) {
 1003                         if ((error = epic_add_rxbuf(sc, i)) != 0) {
 1004                                 printf("%s: unable to allocate or map rx "
 1005                                     "buffer %d error = %d\n",
 1006                                     device_xname(sc->sc_dev), i, error);
 1007                                 /*
 1008                                  * XXX Should attempt to run with fewer receive
 1009                                  * XXX buffers instead of just failing.
 1010                                  */
 1011                                 epic_rxdrain(sc);
 1012                                 goto out;
 1013                         }
 1014                 } else
 1015                         EPIC_INIT_RXDESC(sc, i);
 1016         }
 1017         sc->sc_rxptr = 0;
 1018 
 1019         /*
 1020          * Initialize the interrupt mask and enable interrupts.
 1021          */
 1022         bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK);
 1023         bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA);
 1024 
 1025         /*
 1026          * Give the transmit and receive rings to the EPIC.
 1027          */
 1028         bus_space_write_4(st, sh, EPIC_PTCDAR,
 1029             EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast)));
 1030         bus_space_write_4(st, sh, EPIC_PRCDAR,
 1031             EPIC_CDRXADDR(sc, sc->sc_rxptr));
 1032 
 1033         /*
 1034          * Set the EPIC in motion.
 1035          */
 1036         bus_space_write_4(st, sh, EPIC_COMMAND,
 1037             COMMAND_RXQUEUED | COMMAND_START_RX);
 1038 
 1039         /*
 1040          * ...all done!
 1041          */
 1042         ifp->if_flags |= IFF_RUNNING;
 1043         ifp->if_flags &= ~IFF_OACTIVE;
 1044 
 1045         /*
 1046          * Start the one second clock.
 1047          */
 1048         callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc);
 1049 
 1050         /*
 1051          * Attempt to start output on the interface.
 1052          */
 1053         epic_start(ifp);
 1054 
 1055  out:
 1056         if (error)
 1057                 printf("%s: interface not running\n", device_xname(sc->sc_dev));
 1058         return error;
 1059 }
 1060 
 1061 /*
 1062  * Drain the receive queue.
 1063  */
 1064 void
 1065 epic_rxdrain(struct epic_softc *sc)
 1066 {
 1067         struct epic_descsoft *ds;
 1068         int i;
 1069 
 1070         for (i = 0; i < EPIC_NRXDESC; i++) {
 1071                 ds = EPIC_DSRX(sc, i);
 1072                 if (ds->ds_mbuf != NULL) {
 1073                         bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
 1074                         m_freem(ds->ds_mbuf);
 1075                         ds->ds_mbuf = NULL;
 1076                 }
 1077         }
 1078 }
 1079 
 1080 /*
 1081  * Stop transmission on the interface.
 1082  */
 1083 void
 1084 epic_stop(struct ifnet *ifp, int disable)
 1085 {
 1086         struct epic_softc *sc = ifp->if_softc;
 1087         bus_space_tag_t st = sc->sc_st;
 1088         bus_space_handle_t sh = sc->sc_sh;
 1089         struct epic_descsoft *ds;
 1090         uint32_t reg;
 1091         int i;
 1092 
 1093         /*
 1094          * Stop the one second clock.
 1095          */
 1096         callout_stop(&sc->sc_mii_callout);
 1097 
 1098         /* Down the MII. */
 1099         mii_down(&sc->sc_mii);
 1100 
 1101         /* Paranoia... */
 1102         epic_fixup_clock_source(sc);
 1103 
 1104         /*
 1105          * Disable interrupts.
 1106          */
 1107         reg = bus_space_read_4(st, sh, EPIC_GENCTL);
 1108         bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA);
 1109         bus_space_write_4(st, sh, EPIC_INTMASK, 0);
 1110 
 1111         /*
 1112          * Stop the DMA engine and take the receiver off-line.
 1113          */
 1114         bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA |
 1115             COMMAND_STOP_TDMA | COMMAND_STOP_RX);
 1116 
 1117         /*
 1118          * Release any queued transmit buffers.
 1119          */
 1120         for (i = 0; i < EPIC_NTXDESC; i++) {
 1121                 ds = EPIC_DSTX(sc, i);
 1122                 if (ds->ds_mbuf != NULL) {
 1123                         bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
 1124                         m_freem(ds->ds_mbuf);
 1125                         ds->ds_mbuf = NULL;
 1126                 }
 1127         }
 1128 
 1129         /*
 1130          * Mark the interface down and cancel the watchdog timer.
 1131          */
 1132         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 1133         ifp->if_timer = 0;
 1134 
 1135         if (disable)
 1136                 epic_rxdrain(sc);
 1137 }
 1138 
 1139 /*
 1140  * Read the EPIC Serial EEPROM.
 1141  */
 1142 void
 1143 epic_read_eeprom(struct epic_softc *sc, int word, int wordcnt, uint16_t *data)
 1144 {
 1145         bus_space_tag_t st = sc->sc_st;
 1146         bus_space_handle_t sh = sc->sc_sh;
 1147         uint16_t reg;
 1148         int i, x;
 1149 
 1150 #define EEPROM_WAIT_READY(st, sh) \
 1151         while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \
 1152                 /* nothing */
 1153 
 1154         /*
 1155          * Enable the EEPROM.
 1156          */
 1157         bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE);
 1158         EEPROM_WAIT_READY(st, sh);
 1159 
 1160         for (i = 0; i < wordcnt; i++) {
 1161                 /* Send CHIP SELECT for one clock tick. */
 1162                 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS);
 1163                 EEPROM_WAIT_READY(st, sh);
 1164 
 1165                 /* Shift in the READ opcode. */
 1166                 for (x = 3; x > 0; x--) {
 1167                         reg = EECTL_ENABLE|EECTL_EECS;
 1168                         if (EPIC_EEPROM_OPC_READ & (1 << (x - 1)))
 1169                                 reg |= EECTL_EEDI;
 1170                         bus_space_write_4(st, sh, EPIC_EECTL, reg);
 1171                         EEPROM_WAIT_READY(st, sh);
 1172                         bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
 1173                         EEPROM_WAIT_READY(st, sh);
 1174                         bus_space_write_4(st, sh, EPIC_EECTL, reg);
 1175                         EEPROM_WAIT_READY(st, sh);
 1176                 }
 1177 
 1178                 /* Shift in address. */
 1179                 for (x = 6; x > 0; x--) {
 1180                         reg = EECTL_ENABLE|EECTL_EECS;
 1181                         if ((word + i) & (1 << (x - 1)))
 1182                                 reg |= EECTL_EEDI;
 1183                         bus_space_write_4(st, sh, EPIC_EECTL, reg);
 1184                         EEPROM_WAIT_READY(st, sh);
 1185                         bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
 1186                         EEPROM_WAIT_READY(st, sh);
 1187                         bus_space_write_4(st, sh, EPIC_EECTL, reg);
 1188                         EEPROM_WAIT_READY(st, sh);
 1189                 }
 1190 
 1191                 /* Shift out data. */
 1192                 reg = EECTL_ENABLE|EECTL_EECS;
 1193                 data[i] = 0;
 1194                 for (x = 16; x > 0; x--) {
 1195                         bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK);
 1196                         EEPROM_WAIT_READY(st, sh);
 1197                         if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO)
 1198                                 data[i] |= (1 << (x - 1));
 1199                         bus_space_write_4(st, sh, EPIC_EECTL, reg);
 1200                         EEPROM_WAIT_READY(st, sh);
 1201                 }
 1202 
 1203                 /* Clear CHIP SELECT. */
 1204                 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE);
 1205                 EEPROM_WAIT_READY(st, sh);
 1206         }
 1207 
 1208         /*
 1209          * Disable the EEPROM.
 1210          */
 1211         bus_space_write_4(st, sh, EPIC_EECTL, 0);
 1212 
 1213 #undef EEPROM_WAIT_READY
 1214 }
 1215 
 1216 /*
 1217  * Add a receive buffer to the indicated descriptor.
 1218  */
 1219 int
 1220 epic_add_rxbuf(struct epic_softc *sc, int idx)
 1221 {
 1222         struct epic_descsoft *ds = EPIC_DSRX(sc, idx);
 1223         struct mbuf *m;
 1224         int error;
 1225 
 1226         MGETHDR(m, M_DONTWAIT, MT_DATA);
 1227         if (m == NULL)
 1228                 return ENOBUFS;
 1229 
 1230         MCLGET(m, M_DONTWAIT);
 1231         if ((m->m_flags & M_EXT) == 0) {
 1232                 m_freem(m);
 1233                 return ENOBUFS;
 1234         }
 1235 
 1236         if (ds->ds_mbuf != NULL)
 1237                 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap);
 1238 
 1239         ds->ds_mbuf = m;
 1240 
 1241         error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap,
 1242             m->m_ext.ext_buf, m->m_ext.ext_size, NULL,
 1243             BUS_DMA_READ|BUS_DMA_NOWAIT);
 1244         if (error) {
 1245                 printf("%s: can't load rx DMA map %d, error = %d\n",
 1246                     device_xname(sc->sc_dev), idx, error);
 1247                 panic("%s", __func__);  /* XXX */
 1248         }
 1249 
 1250         bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0,
 1251             ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD);
 1252 
 1253         EPIC_INIT_RXDESC(sc, idx);
 1254 
 1255         return 0;
 1256 }
 1257 
 1258 /*
 1259  * Set the EPIC multicast hash table.
 1260  *
 1261  * NOTE: We rely on a recently-updated mii_media_active here!
 1262  */
 1263 void
 1264 epic_set_mchash(struct epic_softc *sc)
 1265 {
 1266         struct ethercom *ec = &sc->sc_ethercom;
 1267         struct ifnet *ifp = &sc->sc_ethercom.ec_if;
 1268         struct ether_multi *enm;
 1269         struct ether_multistep step;
 1270         uint32_t hash, mchash[4];
 1271 
 1272         /*
 1273          * Set up the multicast address filter by passing all multicast
 1274          * addresses through a CRC generator, and then using the low-order
 1275          * 6 bits as an index into the 64 bit multicast hash table (only
 1276          * the lower 16 bits of each 32 bit multicast hash register are
 1277          * valid).  The high order bits select the register, while the
 1278          * rest of the bits select the bit within the register.
 1279          */
 1280 
 1281         if (ifp->if_flags & IFF_PROMISC)
 1282                 goto allmulti;
 1283 
 1284         if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) {
 1285                 /* XXX hardware bug in 10Mbps mode. */
 1286                 goto allmulti;
 1287         }
 1288 
 1289         mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0;
 1290 
 1291         ETHER_FIRST_MULTI(step, ec, enm);
 1292         while (enm != NULL) {
 1293                 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) {
 1294                         /*
 1295                          * We must listen to a range of multicast addresses.
 1296                          * For now, just accept all multicasts, rather than
 1297                          * trying to set only those filter bits needed to match
 1298                          * the range.  (At this time, the only use of address
 1299                          * ranges is for IP multicast routing, for which the
 1300                          * range is big enough to require all bits set.)
 1301                          */
 1302                         goto allmulti;
 1303                 }
 1304 
 1305                 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN);
 1306                 hash >>= 26;
 1307 
 1308                 /* Set the corresponding bit in the hash table. */
 1309                 mchash[hash >> 4] |= 1 << (hash & 0xf);
 1310 
 1311                 ETHER_NEXT_MULTI(step, enm);
 1312         }
 1313 
 1314         ifp->if_flags &= ~IFF_ALLMULTI;
 1315         goto sethash;
 1316 
 1317  allmulti:
 1318         ifp->if_flags |= IFF_ALLMULTI;
 1319         mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff;
 1320 
 1321  sethash:
 1322         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]);
 1323         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]);
 1324         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]);
 1325         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]);
 1326 }
 1327 
 1328 /*
 1329  * Wait for the MII to become ready.
 1330  */
 1331 int
 1332 epic_mii_wait(struct epic_softc *sc, uint32_t rw)
 1333 {
 1334         int i;
 1335 
 1336         for (i = 0; i < 50; i++) {
 1337                 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw)
 1338                     == 0)
 1339                         break;
 1340                 delay(2);
 1341         }
 1342         if (i == 50) {
 1343                 printf("%s: MII timed out\n", device_xname(sc->sc_dev));
 1344                 return 1;
 1345         }
 1346 
 1347         return 0;
 1348 }
 1349 
 1350 /*
 1351  * Read from the MII.
 1352  */
 1353 int
 1354 epic_mii_read(device_t self, int phy, int reg)
 1355 {
 1356         struct epic_softc *sc = device_private(self);
 1357 
 1358         if (epic_mii_wait(sc, MMCTL_WRITE))
 1359                 return 0;
 1360 
 1361         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL,
 1362             MMCTL_ARG(phy, reg, MMCTL_READ));
 1363 
 1364         if (epic_mii_wait(sc, MMCTL_READ))
 1365                 return 0;
 1366 
 1367         return bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) &
 1368             MMDATA_MASK;
 1369 }
 1370 
 1371 /*
 1372  * Write to the MII.
 1373  */
 1374 void
 1375 epic_mii_write(device_t self, int phy, int reg, int val)
 1376 {
 1377         struct epic_softc *sc = device_private(self);
 1378 
 1379         if (epic_mii_wait(sc, MMCTL_WRITE))
 1380                 return;
 1381 
 1382         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val);
 1383         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL,
 1384             MMCTL_ARG(phy, reg, MMCTL_WRITE));
 1385 }
 1386 
 1387 /*
 1388  * Callback from PHY when media changes.
 1389  */
 1390 void
 1391 epic_statchg(device_t self)
 1392 {
 1393         struct epic_softc *sc = device_private(self);
 1394         uint32_t txcon, miicfg;
 1395 
 1396         /*
 1397          * Update loopback bits in TXCON to reflect duplex mode.
 1398          */
 1399         txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON);
 1400         if (sc->sc_mii.mii_media_active & IFM_FDX)
 1401                 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2);
 1402         else
 1403                 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2);
 1404         bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon);
 1405 
 1406         /* On some cards we need manualy set fullduplex led */
 1407         if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) {
 1408                 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG);
 1409                 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX)
 1410                         miicfg |= MIICFG_ENABLE;
 1411                 else
 1412                         miicfg &= ~MIICFG_ENABLE;
 1413                 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg);
 1414         }
 1415 
 1416         /*
 1417          * There is a multicast filter bug in 10Mbps mode.  Kick the
 1418          * multicast filter in case the speed changed.
 1419          */
 1420         epic_set_mchash(sc);
 1421 }
 1422 
 1423 /*
 1424  * Callback from ifmedia to request new media setting.
 1425  *
 1426  * XXX Looks to me like some of this complexity should move into
 1427  * XXX one or two custom PHY drivers. --dyoung
 1428  */
 1429 int
 1430 epic_mediachange(struct ifnet *ifp)
 1431 {
 1432         struct epic_softc *sc = ifp->if_softc;
 1433         struct mii_data *mii = &sc->sc_mii;
 1434         struct ifmedia *ifm = &mii->mii_media;
 1435         int media = ifm->ifm_cur->ifm_media;
 1436         uint32_t miicfg;
 1437         struct mii_softc *miisc;
 1438         int cfg, rc;
 1439 
 1440         if ((ifp->if_flags & IFF_UP) == 0)
 1441                 return 0;
 1442 
 1443         if (IFM_INST(media) != sc->sc_serinst) {
 1444                 /* If we're not selecting serial interface, select MII mode */
 1445 #ifdef EPICMEDIADEBUG
 1446                 printf("%s: parallel mode\n", ifp->if_xname);
 1447 #endif
 1448                 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG);
 1449                 miicfg &= ~MIICFG_SERMODEENA;
 1450                 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg);
 1451         }
 1452 
 1453         if ((rc = mii_mediachg(mii)) == ENXIO)
 1454                 rc = 0;
 1455 
 1456         if (IFM_INST(media) == sc->sc_serinst) {
 1457                 /* select serial interface */
 1458 #ifdef EPICMEDIADEBUG
 1459                 printf("%s: serial mode\n", ifp->if_xname);
 1460 #endif
 1461                 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG);
 1462                 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE);
 1463                 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg);
 1464 
 1465                 /* There is no driver to fill this */
 1466                 mii->mii_media_active = media;
 1467                 mii->mii_media_status = 0;
 1468 
 1469                 epic_statchg(sc->sc_dev);
 1470                 return 0;
 1471         }
 1472 
 1473         /* Lookup selected PHY */
 1474         LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
 1475                 if (IFM_INST(media) == miisc->mii_inst)
 1476                         break;
 1477         }
 1478         if (!miisc) {
 1479                 printf("%s: can't happen\n", __func__); /* ??? panic */
 1480                 return 0;
 1481         }
 1482 #ifdef EPICMEDIADEBUG
 1483         printf("%s: using phy %s\n", ifp->if_xname,
 1484                device_xname(miisc->mii_dev));
 1485 #endif
 1486 
 1487         if (miisc->mii_flags & MIIF_HAVEFIBER) {
 1488                 /* XXX XXX assume it's a Level1 - should check */
 1489 
 1490                 /* We have to powerup fiber transceivers */
 1491                 cfg = PHY_READ(miisc, MII_LXTPHY_CONFIG);
 1492                 if (IFM_SUBTYPE(media) == IFM_100_FX) {
 1493 #ifdef EPICMEDIADEBUG
 1494                         printf("%s: power up fiber\n", ifp->if_xname);
 1495 #endif
 1496                         cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0);
 1497                 } else {
 1498 #ifdef EPICMEDIADEBUG
 1499                         printf("%s: power down fiber\n", ifp->if_xname);
 1500 #endif
 1501                         cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0);
 1502                 }
 1503                 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg);
 1504         }
 1505 
 1506         return rc;
 1507 }

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