Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/smc83c170.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* $NetBSD: smc83c170.c,v 1.96 2022/09/25 18:43:32 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the Standard Microsystems Corp. 83C170 35 * Ethernet PCI Integrated Controller (EPIC/100). 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.96 2022/09/25 18:43:32 thorpej Exp $"); 40 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/kernel.h> 47 #include <sys/socket.h> 48 #include <sys/ioctl.h> 49 #include <sys/errno.h> 50 #include <sys/device.h> 51 52 #include <net/if.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_ether.h> 56 57 #include <net/bpf.h> 58 59 #include <sys/bus.h> 60 #include <sys/intr.h> 61 62 #include <dev/mii/miivar.h> 63 #include <dev/mii/lxtphyreg.h> 64 65 #include <dev/ic/smc83c170reg.h> 66 #include <dev/ic/smc83c170var.h> 67 68 static void epic_start(struct ifnet *); 69 static void epic_watchdog(struct ifnet *); 70 static int epic_ioctl(struct ifnet *, u_long, void *); 71 static int epic_init(struct ifnet *); 72 static void epic_stop(struct ifnet *, int); 73 74 static bool epic_shutdown(device_t, int); 75 76 static void epic_reset(struct epic_softc *); 77 static void epic_rxdrain(struct epic_softc *); 78 static int epic_add_rxbuf(struct epic_softc *, int); 79 static void epic_read_eeprom(struct epic_softc *, int, int, uint16_t *); 80 static void epic_set_mchash(struct epic_softc *); 81 static void epic_fixup_clock_source(struct epic_softc *); 82 static int epic_mii_read(device_t, int, int, uint16_t *); 83 static int epic_mii_write(device_t, int, int, uint16_t); 84 static int epic_mii_wait(struct epic_softc *, uint32_t); 85 static void epic_tick(void *); 86 87 static void epic_statchg(struct ifnet *); 88 static int epic_mediachange(struct ifnet *); 89 90 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 91 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 92 93 int epic_copy_small = 0; 94 95 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 96 97 /* 98 * Attach an EPIC interface to the system. 99 */ 100 void 101 epic_attach(struct epic_softc *sc) 102 { 103 bus_space_tag_t st = sc->sc_st; 104 bus_space_handle_t sh = sc->sc_sh; 105 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 106 struct mii_data * const mii = &sc->sc_mii; 107 int rseg, error, miiflags; 108 u_int i; 109 bus_dma_segment_t seg; 110 uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 111 uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 112 char *nullbuf; 113 114 callout_init(&sc->sc_mii_callout, 0); 115 callout_setfunc(&sc->sc_mii_callout, epic_tick, sc); 116 117 /* 118 * Allocate the control data structures, and create and load the 119 * DMA map for it. 120 */ 121 if ((error = bus_dmamem_alloc(sc->sc_dmat, 122 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 123 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 124 aprint_error_dev(sc->sc_dev, 125 "unable to allocate control data, error = %d\n", error); 126 goto fail_0; 127 } 128 129 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 130 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 131 (void **)&sc->sc_control_data, 132 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 133 aprint_error_dev(sc->sc_dev, 134 "unable to map control data, error = %d\n", error); 135 goto fail_1; 136 } 137 nullbuf = 138 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 139 memset(nullbuf, 0, ETHER_PAD_LEN); 140 141 if ((error = bus_dmamap_create(sc->sc_dmat, 142 sizeof(struct epic_control_data), 1, 143 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 144 &sc->sc_cddmamap)) != 0) { 145 aprint_error_dev(sc->sc_dev, 146 "unable to create control data DMA map, error = %d\n", 147 error); 148 goto fail_2; 149 } 150 151 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 152 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 153 BUS_DMA_NOWAIT)) != 0) { 154 aprint_error_dev(sc->sc_dev, 155 "unable to load control data DMA map, error = %d\n", 156 error); 157 goto fail_3; 158 } 159 160 /* 161 * Create the transmit buffer DMA maps. 162 */ 163 for (i = 0; i < EPIC_NTXDESC; i++) { 164 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 165 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 166 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 167 aprint_error_dev(sc->sc_dev, 168 "unable to create tx DMA map %d, error = %d\n", 169 i, error); 170 goto fail_4; 171 } 172 } 173 174 /* 175 * Create the receive buffer DMA maps. 176 */ 177 for (i = 0; i < EPIC_NRXDESC; i++) { 178 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 179 MCLBYTES, 0, BUS_DMA_NOWAIT, 180 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 181 aprint_error_dev(sc->sc_dev, 182 "unable to create rx DMA map %d, error = %d\n", 183 i, error); 184 goto fail_5; 185 } 186 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 187 } 188 189 /* 190 * create and map the pad buffer 191 */ 192 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 193 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 194 aprint_error_dev(sc->sc_dev, 195 "unable to create pad buffer DMA map, error = %d\n", error); 196 goto fail_5; 197 } 198 199 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 200 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 201 aprint_error_dev(sc->sc_dev, 202 "unable to load pad buffer DMA map, error = %d\n", error); 203 goto fail_6; 204 } 205 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 206 BUS_DMASYNC_PREWRITE); 207 208 /* 209 * Bring the chip out of low-power mode and reset it to a known state. 210 */ 211 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 212 epic_reset(sc); 213 214 /* 215 * Read the Ethernet address from the EEPROM. 216 */ 217 epic_read_eeprom(sc, 0, __arraycount(myea), myea); 218 for (i = 0; i < __arraycount(myea); i++) { 219 enaddr[i * 2] = myea[i] & 0xff; 220 enaddr[i * 2 + 1] = myea[i] >> 8; 221 } 222 223 /* 224 * ...and the device name. 225 */ 226 epic_read_eeprom(sc, 0x2c, __arraycount(mydevname), mydevname); 227 for (i = 0; i < __arraycount(mydevname); i++) { 228 devname[i * 2] = mydevname[i] & 0xff; 229 devname[i * 2 + 1] = mydevname[i] >> 8; 230 } 231 232 devname[sizeof(mydevname)] = '\0'; 233 for (i = sizeof(mydevname) ; i > 0; i--) { 234 if (devname[i - 1] == ' ') 235 devname[i - 1] = '\0'; 236 else 237 break; 238 } 239 240 aprint_normal_dev(sc->sc_dev, "%s, Ethernet address %s\n", 241 devname, ether_sprintf(enaddr)); 242 243 miiflags = 0; 244 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 245 miiflags |= MIIF_HAVEFIBER; 246 247 /* 248 * Initialize our media structures and probe the MII. 249 */ 250 mii->mii_ifp = ifp; 251 mii->mii_readreg = epic_mii_read; 252 mii->mii_writereg = epic_mii_write; 253 mii->mii_statchg = epic_statchg; 254 255 sc->sc_ethercom.ec_mii = mii; 256 ifmedia_init(&mii->mii_media, IFM_IMASK, epic_mediachange, 257 ether_mediastatus); 258 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 259 MII_OFFSET_ANY, miiflags); 260 if (LIST_EMPTY(&mii->mii_phys)) { 261 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_NONE, 0, NULL); 262 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_NONE); 263 } else 264 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 265 266 if (sc->sc_hwflags & EPIC_HAS_BNC) { 267 /* use the next free media instance */ 268 sc->sc_serinst = mii->mii_instance++; 269 ifmedia_add(&mii->mii_media, 270 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->sc_serinst), 271 0, NULL); 272 aprint_normal_dev(sc->sc_dev, "10base2/BNC\n"); 273 } else 274 sc->sc_serinst = -1; 275 276 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 277 ifp->if_softc = sc; 278 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 279 ifp->if_ioctl = epic_ioctl; 280 ifp->if_start = epic_start; 281 ifp->if_watchdog = epic_watchdog; 282 ifp->if_init = epic_init; 283 ifp->if_stop = epic_stop; 284 IFQ_SET_READY(&ifp->if_snd); 285 286 /* 287 * We can support 802.1Q VLAN-sized frames. 288 */ 289 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 290 291 /* 292 * Attach the interface. 293 */ 294 if_attach(ifp); 295 if_deferred_start_init(ifp, NULL); 296 ether_ifattach(ifp, enaddr); 297 298 /* 299 * Make sure the interface is shutdown during reboot. 300 */ 301 if (pmf_device_register1(sc->sc_dev, NULL, NULL, epic_shutdown)) 302 pmf_class_network_register(sc->sc_dev, ifp); 303 else 304 aprint_error_dev(sc->sc_dev, 305 "couldn't establish power handler\n"); 306 307 return; 308 309 /* 310 * Free any resources we've allocated during the failed attach 311 * attempt. Do this in reverse order and fall through. 312 */ 313 fail_6: 314 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 315 fail_5: 316 for (i = 0; i < EPIC_NRXDESC; i++) { 317 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 318 bus_dmamap_destroy(sc->sc_dmat, 319 EPIC_DSRX(sc, i)->ds_dmamap); 320 } 321 fail_4: 322 for (i = 0; i < EPIC_NTXDESC; i++) { 323 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 324 bus_dmamap_destroy(sc->sc_dmat, 325 EPIC_DSTX(sc, i)->ds_dmamap); 326 } 327 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 328 fail_3: 329 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 330 fail_2: 331 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 332 sizeof(struct epic_control_data)); 333 fail_1: 334 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 335 fail_0: 336 return; 337 } 338 339 /* 340 * Shutdown hook. Make sure the interface is stopped at reboot. 341 */ 342 static bool 343 epic_shutdown(device_t self, int howto) 344 { 345 struct epic_softc *sc = device_private(self); 346 347 epic_stop(&sc->sc_ethercom.ec_if, 1); 348 349 return true; 350 } 351 352 /* 353 * Start packet transmission on the interface. 354 * [ifnet interface function] 355 */ 356 static void 357 epic_start(struct ifnet *ifp) 358 { 359 struct epic_softc *sc = ifp->if_softc; 360 struct mbuf *m0, *m; 361 struct epic_txdesc *txd; 362 struct epic_descsoft *ds; 363 struct epic_fraglist *fr; 364 bus_dmamap_t dmamap; 365 int error, firsttx, nexttx, opending, seg; 366 u_int len; 367 368 /* 369 * Remember the previous txpending and the first transmit 370 * descriptor we use. 371 */ 372 opending = sc->sc_txpending; 373 firsttx = EPIC_NEXTTX(sc->sc_txlast); 374 375 /* 376 * Loop through the send queue, setting up transmit descriptors 377 * until we drain the queue, or use up all available transmit 378 * descriptors. 379 */ 380 while (sc->sc_txpending < EPIC_NTXDESC) { 381 /* 382 * Grab a packet off the queue. 383 */ 384 IFQ_POLL(&ifp->if_snd, m0); 385 if (m0 == NULL) 386 break; 387 m = NULL; 388 389 /* 390 * Get the last and next available transmit descriptor. 391 */ 392 nexttx = EPIC_NEXTTX(sc->sc_txlast); 393 txd = EPIC_CDTX(sc, nexttx); 394 fr = EPIC_CDFL(sc, nexttx); 395 ds = EPIC_DSTX(sc, nexttx); 396 dmamap = ds->ds_dmamap; 397 398 /* 399 * Load the DMA map. If this fails, the packet either 400 * didn't fit in the alloted number of frags, or we were 401 * short on resources. In this case, we'll copy and try 402 * again. 403 */ 404 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 405 BUS_DMA_WRITE | BUS_DMA_NOWAIT)) != 0 || 406 (m0->m_pkthdr.len < ETHER_PAD_LEN && 407 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 408 if (error == 0) 409 bus_dmamap_unload(sc->sc_dmat, dmamap); 410 411 MGETHDR(m, M_DONTWAIT, MT_DATA); 412 if (m == NULL) { 413 printf("%s: unable to allocate Tx mbuf\n", 414 device_xname(sc->sc_dev)); 415 break; 416 } 417 MCLAIM(m, &sc->sc_ethercom.ec_tx_mowner); 418 if (m0->m_pkthdr.len > MHLEN) { 419 MCLGET(m, M_DONTWAIT); 420 if ((m->m_flags & M_EXT) == 0) { 421 printf("%s: unable to allocate Tx " 422 "cluster\n", 423 device_xname(sc->sc_dev)); 424 m_freem(m); 425 break; 426 } 427 } 428 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 429 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 430 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 431 m, BUS_DMA_WRITE | BUS_DMA_NOWAIT); 432 if (error) { 433 printf("%s: unable to load Tx buffer, " 434 "error = %d\n", device_xname(sc->sc_dev), 435 error); 436 break; 437 } 438 } 439 IFQ_DEQUEUE(&ifp->if_snd, m0); 440 if (m != NULL) { 441 m_freem(m0); 442 m0 = m; 443 } 444 445 /* Initialize the fraglist. */ 446 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 447 fr->ef_frags[seg].ef_addr = 448 dmamap->dm_segs[seg].ds_addr; 449 fr->ef_frags[seg].ef_length = 450 dmamap->dm_segs[seg].ds_len; 451 } 452 len = m0->m_pkthdr.len; 453 if (len < ETHER_PAD_LEN) { 454 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 455 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 456 len = ETHER_PAD_LEN; 457 seg++; 458 } 459 fr->ef_nfrags = seg; 460 461 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 462 463 /* Sync the DMA map. */ 464 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 465 BUS_DMASYNC_PREWRITE); 466 467 /* 468 * Store a pointer to the packet so we can free it later. 469 */ 470 ds->ds_mbuf = m0; 471 472 /* 473 * Fill in the transmit descriptor. 474 */ 475 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 476 477 /* 478 * If this is the first descriptor we're enqueueing, 479 * don't give it to the EPIC yet. That could cause 480 * a race condition. We'll do it below. 481 */ 482 if (nexttx == firsttx) 483 txd->et_txstatus = TXSTAT_TXLENGTH(len); 484 else 485 txd->et_txstatus = 486 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 487 488 EPIC_CDTXSYNC(sc, nexttx, 489 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 490 491 /* Advance the tx pointer. */ 492 sc->sc_txpending++; 493 sc->sc_txlast = nexttx; 494 495 /* 496 * Pass the packet to any BPF listeners. 497 */ 498 bpf_mtap(ifp, m0, BPF_D_OUT); 499 } 500 501 if (sc->sc_txpending != opending) { 502 /* 503 * We enqueued packets. If the transmitter was idle, 504 * reset the txdirty pointer. 505 */ 506 if (opending == 0) 507 sc->sc_txdirty = firsttx; 508 509 /* 510 * Cause a transmit interrupt to happen on the 511 * last packet we enqueued. 512 */ 513 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 514 EPIC_CDTXSYNC(sc, sc->sc_txlast, 515 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 516 517 /* 518 * The entire packet chain is set up. Give the 519 * first descriptor to the EPIC now. 520 */ 521 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 522 EPIC_CDTXSYNC(sc, firsttx, 523 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 524 525 /* Start the transmitter. */ 526 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 527 COMMAND_TXQUEUED); 528 529 /* Set a watchdog timer in case the chip flakes out. */ 530 ifp->if_timer = 5; 531 } 532 } 533 534 /* 535 * Watchdog timer handler. 536 * [ifnet interface function] 537 */ 538 static void 539 epic_watchdog(struct ifnet *ifp) 540 { 541 struct epic_softc *sc = ifp->if_softc; 542 543 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 544 if_statinc(ifp, if_oerrors); 545 546 (void)epic_init(ifp); 547 } 548 549 /* 550 * Handle control requests from the operator. 551 * [ifnet interface function] 552 */ 553 static int 554 epic_ioctl(struct ifnet *ifp, u_long cmd, void *data) 555 { 556 struct epic_softc *sc = ifp->if_softc; 557 int s, error; 558 559 s = splnet(); 560 561 error = ether_ioctl(ifp, cmd, data); 562 if (error == ENETRESET) { 563 /* 564 * Multicast list has changed; set the hardware filter 565 * accordingly. Update our idea of the current media; 566 * epic_set_mchash() needs to know what it is. 567 */ 568 if (ifp->if_flags & IFF_RUNNING) { 569 mii_pollstat(&sc->sc_mii); 570 epic_set_mchash(sc); 571 } 572 error = 0; 573 } 574 575 splx(s); 576 return error; 577 } 578 579 /* 580 * Interrupt handler. 581 */ 582 int 583 epic_intr(void *arg) 584 { 585 struct epic_softc *sc = arg; 586 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 587 struct epic_rxdesc *rxd; 588 struct epic_txdesc *txd; 589 struct epic_descsoft *ds; 590 struct mbuf *m; 591 uint32_t intstat, rxstatus, txstatus; 592 int i, claimed = 0; 593 u_int len; 594 595 top: 596 /* 597 * Get the interrupt status from the EPIC. 598 */ 599 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 600 if ((intstat & INTSTAT_INT_ACTV) == 0) 601 return claimed; 602 603 claimed = 1; 604 605 /* 606 * Acknowledge the interrupt. 607 */ 608 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 609 intstat & INTMASK); 610 611 /* 612 * Check for receive interrupts. 613 */ 614 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 615 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 616 rxd = EPIC_CDRX(sc, i); 617 ds = EPIC_DSRX(sc, i); 618 619 EPIC_CDRXSYNC(sc, i, 620 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 621 622 rxstatus = rxd->er_rxstatus; 623 if (rxstatus & ER_RXSTAT_OWNER) { 624 /* 625 * We have processed all of the 626 * receive buffers. 627 */ 628 break; 629 } 630 631 /* 632 * Make sure the packet arrived intact. If an error 633 * occurred, update stats and reset the descriptor. 634 * The buffer will be reused the next time the 635 * descriptor comes up in the ring. 636 */ 637 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 638 if (rxstatus & ER_RXSTAT_CRCERROR) 639 printf("%s: CRC error\n", 640 device_xname(sc->sc_dev)); 641 if (rxstatus & ER_RXSTAT_ALIGNERROR) 642 printf("%s: alignment error\n", 643 device_xname(sc->sc_dev)); 644 if_statinc(ifp, if_ierrors); 645 EPIC_INIT_RXDESC(sc, i); 646 continue; 647 } 648 649 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 650 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 651 652 /* 653 * The EPIC includes the CRC with every packet; 654 * trim it. 655 */ 656 len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN; 657 658 if (len < sizeof(struct ether_header)) { 659 /* 660 * Runt packet; drop it now. 661 */ 662 if_statinc(ifp, if_ierrors); 663 EPIC_INIT_RXDESC(sc, i); 664 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 665 ds->ds_dmamap->dm_mapsize, 666 BUS_DMASYNC_PREREAD); 667 continue; 668 } 669 670 /* 671 * If the packet is small enough to fit in a 672 * single header mbuf, allocate one and copy 673 * the data into it. This greatly reduces 674 * memory consumption when we receive lots 675 * of small packets. 676 * 677 * Otherwise, we add a new buffer to the receive 678 * chain. If this fails, we drop the packet and 679 * recycle the old buffer. 680 */ 681 if (epic_copy_small != 0 && len <= MHLEN) { 682 MGETHDR(m, M_DONTWAIT, MT_DATA); 683 if (m == NULL) 684 goto dropit; 685 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 686 memcpy(mtod(m, void *), 687 mtod(ds->ds_mbuf, void *), len); 688 EPIC_INIT_RXDESC(sc, i); 689 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 690 ds->ds_dmamap->dm_mapsize, 691 BUS_DMASYNC_PREREAD); 692 } else { 693 m = ds->ds_mbuf; 694 if (epic_add_rxbuf(sc, i) != 0) { 695 dropit: 696 if_statinc(ifp, if_ierrors); 697 EPIC_INIT_RXDESC(sc, i); 698 bus_dmamap_sync(sc->sc_dmat, 699 ds->ds_dmamap, 0, 700 ds->ds_dmamap->dm_mapsize, 701 BUS_DMASYNC_PREREAD); 702 continue; 703 } 704 } 705 706 m_set_rcvif(m, ifp); 707 m->m_pkthdr.len = m->m_len = len; 708 709 /* Pass it on. */ 710 if_percpuq_enqueue(ifp->if_percpuq, m); 711 } 712 713 /* Update the receive pointer. */ 714 sc->sc_rxptr = i; 715 716 /* 717 * Check for receive queue underflow. 718 */ 719 if (intstat & INTSTAT_RQE) { 720 printf("%s: receiver queue empty\n", 721 device_xname(sc->sc_dev)); 722 /* 723 * Ring is already built; just restart the 724 * receiver. 725 */ 726 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 727 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 728 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 729 COMMAND_RXQUEUED | COMMAND_START_RX); 730 } 731 } 732 733 /* 734 * Check for transmission complete interrupts. 735 */ 736 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 737 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 738 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 739 txd = EPIC_CDTX(sc, i); 740 ds = EPIC_DSTX(sc, i); 741 742 EPIC_CDTXSYNC(sc, i, 743 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 744 745 txstatus = txd->et_txstatus; 746 if (txstatus & ET_TXSTAT_OWNER) 747 break; 748 749 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 750 751 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 752 0, ds->ds_dmamap->dm_mapsize, 753 BUS_DMASYNC_POSTWRITE); 754 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 755 m_freem(ds->ds_mbuf); 756 ds->ds_mbuf = NULL; 757 758 /* 759 * Check for errors and collisions. 760 */ 761 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 762 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 763 if_statinc_ref(nsr, if_oerrors); 764 else 765 if_statinc_ref(nsr, if_opackets); 766 if (TXSTAT_COLLISIONS(txstatus)) 767 if_statadd_ref(nsr, if_collisions, 768 TXSTAT_COLLISIONS(txstatus)); 769 if (txstatus & ET_TXSTAT_CARSENSELOST) 770 printf("%s: lost carrier\n", 771 device_xname(sc->sc_dev)); 772 IF_STAT_PUTREF(ifp); 773 } 774 775 /* Update the dirty transmit buffer pointer. */ 776 sc->sc_txdirty = i; 777 778 /* 779 * Cancel the watchdog timer if there are no pending 780 * transmissions. 781 */ 782 if (sc->sc_txpending == 0) 783 ifp->if_timer = 0; 784 785 /* 786 * Kick the transmitter after a DMA underrun. 787 */ 788 if (intstat & INTSTAT_TXU) { 789 printf("%s: transmit underrun\n", 790 device_xname(sc->sc_dev)); 791 bus_space_write_4(sc->sc_st, sc->sc_sh, 792 EPIC_COMMAND, COMMAND_TXUGO); 793 if (sc->sc_txpending) 794 bus_space_write_4(sc->sc_st, sc->sc_sh, 795 EPIC_COMMAND, COMMAND_TXQUEUED); 796 } 797 798 /* 799 * Try to get more packets going. 800 */ 801 if_schedule_deferred_start(ifp); 802 } 803 804 /* 805 * Check for fatal interrupts. 806 */ 807 if (intstat & INTSTAT_FATAL_INT) { 808 if (intstat & INTSTAT_PTA) 809 printf("%s: PCI target abort error\n", 810 device_xname(sc->sc_dev)); 811 else if (intstat & INTSTAT_PMA) 812 printf("%s: PCI master abort error\n", 813 device_xname(sc->sc_dev)); 814 else if (intstat & INTSTAT_APE) 815 printf("%s: PCI address parity error\n", 816 device_xname(sc->sc_dev)); 817 else if (intstat & INTSTAT_DPE) 818 printf("%s: PCI data parity error\n", 819 device_xname(sc->sc_dev)); 820 else 821 printf("%s: unknown fatal error\n", 822 device_xname(sc->sc_dev)); 823 (void)epic_init(ifp); 824 } 825 826 /* 827 * Check for more interrupts. 828 */ 829 goto top; 830 } 831 832 /* 833 * One second timer, used to tick the MII. 834 */ 835 static void 836 epic_tick(void *arg) 837 { 838 struct epic_softc *sc = arg; 839 int s; 840 841 s = splnet(); 842 mii_tick(&sc->sc_mii); 843 splx(s); 844 845 callout_schedule(&sc->sc_mii_callout, hz); 846 } 847 848 /* 849 * Fixup the clock source on the EPIC. 850 */ 851 static void 852 epic_fixup_clock_source(struct epic_softc *sc) 853 { 854 int i; 855 856 /* 857 * According to SMC Application Note 7-15, the EPIC's clock 858 * source is incorrect following a reset. This manifests itself 859 * as failure to recognize when host software has written to 860 * a register on the EPIC. The appnote recommends issuing at 861 * least 16 consecutive writes to the CLOCK TEST bit to correctly 862 * configure the clock source. 863 */ 864 for (i = 0; i < 16; i++) 865 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 866 TEST_CLOCKTEST); 867 } 868 869 /* 870 * Perform a soft reset on the EPIC. 871 */ 872 static void 873 epic_reset(struct epic_softc *sc) 874 { 875 876 epic_fixup_clock_source(sc); 877 878 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 879 delay(100); 880 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 881 delay(100); 882 883 epic_fixup_clock_source(sc); 884 } 885 886 /* 887 * Initialize the interface. Must be called at splnet(). 888 */ 889 static int 890 epic_init(struct ifnet *ifp) 891 { 892 struct epic_softc *sc = ifp->if_softc; 893 bus_space_tag_t st = sc->sc_st; 894 bus_space_handle_t sh = sc->sc_sh; 895 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 896 struct epic_txdesc *txd; 897 struct epic_descsoft *ds; 898 uint32_t genctl, reg0; 899 int i, error = 0; 900 901 /* 902 * Cancel any pending I/O. 903 */ 904 epic_stop(ifp, 0); 905 906 /* 907 * Reset the EPIC to a known state. 908 */ 909 epic_reset(sc); 910 911 /* 912 * Magical mystery initialization. 913 */ 914 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 915 916 /* 917 * Initialize the EPIC genctl register: 918 * 919 * - 64 byte receive FIFO threshold 920 * - automatic advance to next receive frame 921 */ 922 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 923 #if BYTE_ORDER == BIG_ENDIAN 924 genctl |= GENCTL_BIG_ENDIAN; 925 #endif 926 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 927 928 /* 929 * Reset the MII bus and PHY. 930 */ 931 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 932 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 933 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 934 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 935 delay(100); 936 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 937 delay(1000); 938 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 939 940 /* 941 * Initialize Ethernet address. 942 */ 943 reg0 = enaddr[1] << 8 | enaddr[0]; 944 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 945 reg0 = enaddr[3] << 8 | enaddr[2]; 946 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 947 reg0 = enaddr[5] << 8 | enaddr[4]; 948 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 949 950 /* 951 * Initialize receive control. Remember the external buffer 952 * size setting. 953 */ 954 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 955 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 956 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 957 if (ifp->if_flags & IFF_PROMISC) 958 reg0 |= RXCON_PROMISCMODE; 959 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 960 961 /* Set the current media. */ 962 if ((error = epic_mediachange(ifp)) != 0) 963 goto out; 964 965 /* Set up the multicast hash table. */ 966 epic_set_mchash(sc); 967 968 /* 969 * Initialize the transmit descriptor ring. txlast is initialized 970 * to the end of the list so that it will wrap around to the first 971 * descriptor when the first packet is transmitted. 972 */ 973 for (i = 0; i < EPIC_NTXDESC; i++) { 974 txd = EPIC_CDTX(sc, i); 975 memset(txd, 0, sizeof(struct epic_txdesc)); 976 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 977 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 978 EPIC_CDTXSYNC(sc, i, 979 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 980 } 981 sc->sc_txpending = 0; 982 sc->sc_txdirty = 0; 983 sc->sc_txlast = EPIC_NTXDESC - 1; 984 985 /* 986 * Initialize the receive descriptor ring. 987 */ 988 for (i = 0; i < EPIC_NRXDESC; i++) { 989 ds = EPIC_DSRX(sc, i); 990 if (ds->ds_mbuf == NULL) { 991 if ((error = epic_add_rxbuf(sc, i)) != 0) { 992 printf("%s: unable to allocate or map rx " 993 "buffer %d error = %d\n", 994 device_xname(sc->sc_dev), i, error); 995 /* 996 * XXX Should attempt to run with fewer receive 997 * XXX buffers instead of just failing. 998 */ 999 epic_rxdrain(sc); 1000 goto out; 1001 } 1002 } else 1003 EPIC_INIT_RXDESC(sc, i); 1004 } 1005 sc->sc_rxptr = 0; 1006 1007 /* 1008 * Initialize the interrupt mask and enable interrupts. 1009 */ 1010 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1011 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1012 1013 /* 1014 * Give the transmit and receive rings to the EPIC. 1015 */ 1016 bus_space_write_4(st, sh, EPIC_PTCDAR, 1017 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1018 bus_space_write_4(st, sh, EPIC_PRCDAR, 1019 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1020 1021 /* 1022 * Set the EPIC in motion. 1023 */ 1024 bus_space_write_4(st, sh, EPIC_COMMAND, 1025 COMMAND_RXQUEUED | COMMAND_START_RX); 1026 1027 /* 1028 * ...all done! 1029 */ 1030 ifp->if_flags |= IFF_RUNNING; 1031 1032 /* 1033 * Start the one second clock. 1034 */ 1035 callout_schedule(&sc->sc_mii_callout, hz); 1036 1037 /* 1038 * Attempt to start output on the interface. 1039 */ 1040 epic_start(ifp); 1041 1042 out: 1043 if (error) 1044 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1045 return error; 1046 } 1047 1048 /* 1049 * Drain the receive queue. 1050 */ 1051 static void 1052 epic_rxdrain(struct epic_softc *sc) 1053 { 1054 struct epic_descsoft *ds; 1055 int i; 1056 1057 for (i = 0; i < EPIC_NRXDESC; i++) { 1058 ds = EPIC_DSRX(sc, i); 1059 if (ds->ds_mbuf != NULL) { 1060 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1061 m_freem(ds->ds_mbuf); 1062 ds->ds_mbuf = NULL; 1063 } 1064 } 1065 } 1066 1067 /* 1068 * Stop transmission on the interface. 1069 */ 1070 static void 1071 epic_stop(struct ifnet *ifp, int disable) 1072 { 1073 struct epic_softc *sc = ifp->if_softc; 1074 bus_space_tag_t st = sc->sc_st; 1075 bus_space_handle_t sh = sc->sc_sh; 1076 struct epic_descsoft *ds; 1077 uint32_t reg; 1078 int i; 1079 1080 /* 1081 * Stop the one second clock. 1082 */ 1083 callout_stop(&sc->sc_mii_callout); 1084 1085 /* Down the MII. */ 1086 mii_down(&sc->sc_mii); 1087 1088 /* Paranoia... */ 1089 epic_fixup_clock_source(sc); 1090 1091 /* 1092 * Disable interrupts. 1093 */ 1094 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1095 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1096 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1097 1098 /* 1099 * Stop the DMA engine and take the receiver off-line. 1100 */ 1101 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1102 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1103 1104 /* 1105 * Release any queued transmit buffers. 1106 */ 1107 for (i = 0; i < EPIC_NTXDESC; i++) { 1108 ds = EPIC_DSTX(sc, i); 1109 if (ds->ds_mbuf != NULL) { 1110 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1111 m_freem(ds->ds_mbuf); 1112 ds->ds_mbuf = NULL; 1113 } 1114 } 1115 1116 /* 1117 * Mark the interface down and cancel the watchdog timer. 1118 */ 1119 ifp->if_flags &= ~IFF_RUNNING; 1120 ifp->if_timer = 0; 1121 1122 if (disable) 1123 epic_rxdrain(sc); 1124 } 1125 1126 /* 1127 * Read the EPIC Serial EEPROM. 1128 */ 1129 static void 1130 epic_read_eeprom(struct epic_softc *sc, int word, int wordcnt, uint16_t *data) 1131 { 1132 bus_space_tag_t st = sc->sc_st; 1133 bus_space_handle_t sh = sc->sc_sh; 1134 uint16_t reg; 1135 int i, x; 1136 1137 #define EEPROM_WAIT_READY(st, sh) \ 1138 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1139 /* nothing */ 1140 1141 /* 1142 * Enable the EEPROM. 1143 */ 1144 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1145 EEPROM_WAIT_READY(st, sh); 1146 1147 for (i = 0; i < wordcnt; i++) { 1148 /* Send CHIP SELECT for one clock tick. */ 1149 bus_space_write_4(st, sh, EPIC_EECTL, 1150 EECTL_ENABLE | EECTL_EECS); 1151 EEPROM_WAIT_READY(st, sh); 1152 1153 /* Shift in the READ opcode. */ 1154 for (x = 3; x > 0; x--) { 1155 reg = EECTL_ENABLE | EECTL_EECS; 1156 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1157 reg |= EECTL_EEDI; 1158 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1159 EEPROM_WAIT_READY(st, sh); 1160 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1161 EEPROM_WAIT_READY(st, sh); 1162 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1163 EEPROM_WAIT_READY(st, sh); 1164 } 1165 1166 /* Shift in address. */ 1167 for (x = 6; x > 0; x--) { 1168 reg = EECTL_ENABLE | EECTL_EECS; 1169 if ((word + i) & (1 << (x - 1))) 1170 reg |= EECTL_EEDI; 1171 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1172 EEPROM_WAIT_READY(st, sh); 1173 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1174 EEPROM_WAIT_READY(st, sh); 1175 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1176 EEPROM_WAIT_READY(st, sh); 1177 } 1178 1179 /* Shift out data. */ 1180 reg = EECTL_ENABLE | EECTL_EECS; 1181 data[i] = 0; 1182 for (x = 16; x > 0; x--) { 1183 bus_space_write_4(st, sh, EPIC_EECTL, reg |EECTL_EESK); 1184 EEPROM_WAIT_READY(st, sh); 1185 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1186 data[i] |= (1 << (x - 1)); 1187 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1188 EEPROM_WAIT_READY(st, sh); 1189 } 1190 1191 /* Clear CHIP SELECT. */ 1192 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1193 EEPROM_WAIT_READY(st, sh); 1194 } 1195 1196 /* 1197 * Disable the EEPROM. 1198 */ 1199 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1200 1201 #undef EEPROM_WAIT_READY 1202 } 1203 1204 /* 1205 * Add a receive buffer to the indicated descriptor. 1206 */ 1207 static int 1208 epic_add_rxbuf(struct epic_softc *sc, int idx) 1209 { 1210 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1211 struct mbuf *m; 1212 int error; 1213 1214 MGETHDR(m, M_DONTWAIT, MT_DATA); 1215 if (m == NULL) 1216 return ENOBUFS; 1217 MCLAIM(m, &sc->sc_ethercom.ec_rx_mowner); 1218 1219 MCLGET(m, M_DONTWAIT); 1220 if ((m->m_flags & M_EXT) == 0) { 1221 m_freem(m); 1222 return ENOBUFS; 1223 } 1224 1225 if (ds->ds_mbuf != NULL) 1226 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1227 1228 ds->ds_mbuf = m; 1229 1230 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1231 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1232 BUS_DMA_READ | BUS_DMA_NOWAIT); 1233 if (error) { 1234 printf("%s: can't load rx DMA map %d, error = %d\n", 1235 device_xname(sc->sc_dev), idx, error); 1236 panic("%s", __func__); /* XXX */ 1237 } 1238 1239 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1240 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1241 1242 EPIC_INIT_RXDESC(sc, idx); 1243 1244 return 0; 1245 } 1246 1247 /* 1248 * Set the EPIC multicast hash table. 1249 * 1250 * NOTE: We rely on a recently-updated mii_media_active here! 1251 */ 1252 static void 1253 epic_set_mchash(struct epic_softc *sc) 1254 { 1255 struct ethercom *ec = &sc->sc_ethercom; 1256 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1257 struct ether_multi *enm; 1258 struct ether_multistep step; 1259 uint32_t hash, mchash[4]; 1260 1261 /* 1262 * Set up the multicast address filter by passing all multicast 1263 * addresses through a CRC generator, and then using the low-order 1264 * 6 bits as an index into the 64 bit multicast hash table (only 1265 * the lower 16 bits of each 32 bit multicast hash register are 1266 * valid). The high order bits select the register, while the 1267 * rest of the bits select the bit within the register. 1268 */ 1269 1270 if (ifp->if_flags & IFF_PROMISC) 1271 goto allmulti; 1272 1273 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1274 /* XXX hardware bug in 10Mbps mode. */ 1275 goto allmulti; 1276 } 1277 1278 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1279 1280 ETHER_LOCK(ec); 1281 ETHER_FIRST_MULTI(step, ec, enm); 1282 while (enm != NULL) { 1283 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1284 /* 1285 * We must listen to a range of multicast addresses. 1286 * For now, just accept all multicasts, rather than 1287 * trying to set only those filter bits needed to match 1288 * the range. (At this time, the only use of address 1289 * ranges is for IP multicast routing, for which the 1290 * range is big enough to require all bits set.) 1291 */ 1292 ETHER_UNLOCK(ec); 1293 goto allmulti; 1294 } 1295 1296 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1297 hash >>= 26; 1298 1299 /* Set the corresponding bit in the hash table. */ 1300 mchash[hash >> 4] |= 1 << (hash & 0xf); 1301 1302 ETHER_NEXT_MULTI(step, enm); 1303 } 1304 ETHER_UNLOCK(ec); 1305 1306 ifp->if_flags &= ~IFF_ALLMULTI; 1307 goto sethash; 1308 1309 allmulti: 1310 ifp->if_flags |= IFF_ALLMULTI; 1311 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1312 1313 sethash: 1314 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1315 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1316 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1317 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1318 } 1319 1320 /* 1321 * Wait for the MII to become ready. 1322 */ 1323 static int 1324 epic_mii_wait(struct epic_softc *sc, uint32_t rw) 1325 { 1326 int i; 1327 1328 for (i = 0; i < 50; i++) { 1329 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1330 == 0) 1331 break; 1332 delay(2); 1333 } 1334 if (i == 50) { 1335 printf("%s: MII timed out\n", device_xname(sc->sc_dev)); 1336 return ETIMEDOUT; 1337 } 1338 1339 return 0; 1340 } 1341 1342 /* 1343 * Read from the MII. 1344 */ 1345 static int 1346 epic_mii_read(device_t self, int phy, int reg, uint16_t *val) 1347 { 1348 struct epic_softc *sc = device_private(self); 1349 int rv; 1350 1351 if ((rv = epic_mii_wait(sc, MMCTL_WRITE)) != 0) 1352 return rv; 1353 1354 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1355 MMCTL_ARG(phy, reg, MMCTL_READ)); 1356 1357 if ((rv = epic_mii_wait(sc, MMCTL_READ)) != 0) 1358 return rv; 1359 1360 *val = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) 1361 & MMDATA_MASK; 1362 return 0; 1363 } 1364 1365 /* 1366 * Write to the MII. 1367 */ 1368 static int 1369 epic_mii_write(device_t self, int phy, int reg, uint16_t val) 1370 { 1371 struct epic_softc *sc = device_private(self); 1372 int rv; 1373 1374 if ((rv = epic_mii_wait(sc, MMCTL_WRITE)) != 0) 1375 return rv; 1376 1377 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1378 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1379 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1380 1381 return 0; 1382 } 1383 1384 /* 1385 * Callback from PHY when media changes. 1386 */ 1387 static void 1388 epic_statchg(struct ifnet *ifp) 1389 { 1390 struct epic_softc *sc = ifp->if_softc; 1391 uint32_t txcon, miicfg; 1392 1393 /* 1394 * Update loopback bits in TXCON to reflect duplex mode. 1395 */ 1396 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1397 if (sc->sc_mii.mii_media_active & IFM_FDX) 1398 txcon |= (TXCON_LOOPBACK_D1 | TXCON_LOOPBACK_D2); 1399 else 1400 txcon &= ~(TXCON_LOOPBACK_D1 | TXCON_LOOPBACK_D2); 1401 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1402 1403 /* On some cards we need manualy set fullduplex led */ 1404 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1405 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1406 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1407 miicfg |= MIICFG_ENABLE; 1408 else 1409 miicfg &= ~MIICFG_ENABLE; 1410 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1411 } 1412 1413 /* 1414 * There is a multicast filter bug in 10Mbps mode. Kick the 1415 * multicast filter in case the speed changed. 1416 */ 1417 epic_set_mchash(sc); 1418 } 1419 1420 /* 1421 * Callback from ifmedia to request new media setting. 1422 * 1423 * XXX Looks to me like some of this complexity should move into 1424 * XXX one or two custom PHY drivers. --dyoung 1425 */ 1426 static int 1427 epic_mediachange(struct ifnet *ifp) 1428 { 1429 struct epic_softc *sc = ifp->if_softc; 1430 struct mii_data *mii = &sc->sc_mii; 1431 struct ifmedia *ifm = &mii->mii_media; 1432 int media = ifm->ifm_cur->ifm_media; 1433 uint32_t miicfg; 1434 struct mii_softc *miisc; 1435 int rc; 1436 uint16_t cfg; 1437 1438 if ((ifp->if_flags & IFF_UP) == 0) 1439 return 0; 1440 1441 if (IFM_INST(media) != sc->sc_serinst) { 1442 /* If we're not selecting serial interface, select MII mode */ 1443 #ifdef EPICMEDIADEBUG 1444 printf("%s: parallel mode\n", ifp->if_xname); 1445 #endif 1446 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1447 miicfg &= ~MIICFG_SERMODEENA; 1448 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1449 } 1450 1451 if ((rc = mii_mediachg(mii)) == ENXIO) 1452 rc = 0; 1453 1454 if (IFM_INST(media) == sc->sc_serinst) { 1455 /* select serial interface */ 1456 #ifdef EPICMEDIADEBUG 1457 printf("%s: serial mode\n", ifp->if_xname); 1458 #endif 1459 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1460 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1461 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1462 1463 /* There is no driver to fill this */ 1464 mii->mii_media_active = media; 1465 mii->mii_media_status = 0; 1466 1467 epic_statchg(mii->mii_ifp); 1468 return 0; 1469 } 1470 1471 /* Lookup selected PHY */ 1472 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1473 if (IFM_INST(media) == miisc->mii_inst) 1474 break; 1475 } 1476 if (!miisc) { 1477 printf("%s: can't happen\n", __func__); /* ??? panic */ 1478 return 0; 1479 } 1480 #ifdef EPICMEDIADEBUG 1481 printf("%s: using phy %s\n", ifp->if_xname, 1482 device_xname(miisc->mii_dev)); 1483 #endif 1484 1485 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1486 /* XXX XXX assume it's a Level1 - should check */ 1487 1488 /* We have to powerup fiber transceivers */ 1489 PHY_READ(miisc, MII_LXTPHY_CONFIG, &cfg); 1490 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1491 #ifdef EPICMEDIADEBUG 1492 printf("%s: power up fiber\n", ifp->if_xname); 1493 #endif 1494 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1495 } else { 1496 #ifdef EPICMEDIADEBUG 1497 printf("%s: power down fiber\n", ifp->if_xname); 1498 #endif 1499 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1500 } 1501 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1502 } 1503 1504 return rc; 1505 }
Cache object: bd761f71d9ce50c1f6c698627438dac4
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]