1 /* $NetBSD: smc83c170reg.h,v 1.11.12.1 2007/02/24 13:30:41 bouyer Exp $ */
2
3 /*-
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 #ifndef _DEV_IC_SMC83C170REG_H_
41 #define _DEV_IC_SMC83C170REG_H_
42
43 /*
44 * Register description for the Standard Microsystems Corp. 83C170
45 * Ethernet PCI Integrated Controller (EPIC/100).
46 */
47
48 /*
49 * EPIC transmit descriptor. Must be 4-byte aligned.
50 */
51 struct epic_txdesc {
52 volatile uint32_t et_txstatus; /* transmit status; see below */
53 volatile uint32_t et_bufaddr; /* buffer address */
54 volatile uint32_t et_control; /* control word; see below */
55 volatile uint32_t et_nextdesc; /* next descriptor pointer */
56 };
57
58 /* et_txstatus */
59 #define TXSTAT_TXLENGTH_SHIFT 16 /* TX length in higher 16bits */
60 #define TXSTAT_TXLENGTH(x) ((x) << TXSTAT_TXLENGTH_SHIFT)
61
62 #define ET_TXSTAT_OWNER 0x8000 /* NIC owns descriptor */
63 #define ET_TXSTAT_COLLMASK 0x1f00 /* collisions */
64 #define ET_TXSTAT_DEFERRING 0x0080 /* deferring due to jabber */
65 #define ET_TXSTAT_OOWCOLL 0x0040 /* out of window collision */
66 #define ET_TXSTAT_CDHB 0x0020 /* collision detect heartbeat */
67 #define ET_TXSTAT_UNDERRUN 0x0010 /* DMA underrun */
68 #define ET_TXSTAT_CARSENSELOST 0x0008 /* carrier lost */
69 #define ET_TXSTAT_TXWITHCOLL 0x0004 /* encountered collisions during tx */
70 #define ET_TXSTAT_NONDEFERRED 0x0002 /* transmitted without deferring */
71 #define ET_TXSTAT_PACKETTX 0x0001 /* packet transmitted successfully */
72
73 #define TXSTAT_COLLISIONS(x) (((x) & ET_TXSTAT_COLLMASK) >> 8)
74
75 /* et_control */
76 #define TXCTL_BUFLENGTH_MASK 0x0000ffff /* buf length in lower 16bits */
77 #define TXCTL_BUFLENGTH(x) ((x) & TXCTL_BUFLENGTH_MASK)
78
79 #define ET_TXCTL_LASTDESC 0x00100000 /* last descriptor in frame */
80 #define ET_TXCTL_NOCRC 0x00080000 /* disable CRC generation */
81 #define ET_TXCTL_IAF 0x00040000 /* interrupt after frame */
82 #define ET_TXCTL_LFFORM 0x00020000 /* alternate fraglist format */
83 #define ET_TXCTL_FRAGLIST 0x00010000 /* descriptor points to fraglist */
84
85 /*
86 * EPIC receive descriptor. Must be 4-byte aligned.
87 */
88 struct epic_rxdesc {
89 volatile uint32_t er_rxstatus; /* receive status; see below */
90 volatile uint32_t er_bufaddr; /* buffer address */
91 volatile uint32_t er_control; /* control word; see below */
92 volatile uint32_t er_nextdesc; /* next descriptor pointer */
93 };
94
95 /* er_rxstatus */
96 #define RXSTAT_RXLENGTH_SHIFT 16 /* TX length in higher 16bits */
97 #define RXSTAT_RXLENGTH(x) ((x) >> RXSTAT_RXLENGTH_SHIFT)
98
99 #define ER_RXSTAT_OWNER 0x8000 /* NIC owns descriptor */
100 #define ER_RXSTAT_HDRCOPIED 0x4000 /* rx status posted after hdr copy */
101 #define ER_RXSTAT_FRAGLISTERR 0x2000 /* ran out of frags to copy frame */
102 #define ER_RXSTAT_NETSTATVALID 0x1000 /* length and status are valid */
103 #define ER_RXSTAT_RCVRDIS 0x0040 /* receiver disabled */
104 #define ER_RXSTAT_BCAST 0x0020 /* broadcast address recognized */
105 #define ER_RXSTAT_MCAST 0x0010 /* multicast address recognized */
106 #define ER_RXSTAT_MISSEDPKT 0x0008 /* missed packet */
107 #define ER_RXSTAT_CRCERROR 0x0004 /* EPIC or MII asserted CRC error */
108 #define ER_RXSTAT_ALIGNERROR 0x0002 /* frame not byte-aligned */
109 #define ER_RXSTAT_PKTINTACT 0x0001 /* packet received without error */
110
111 /* er_control */
112 #define RXCTL_BUFLENGTH_MASK 0x0000ffff /* buf length in lower 16bits */
113 #define RXCTL_BUFLENGTH(x) ((x) & RXCTL_BUFLENGTH_MASK)
114
115 #define ER_RXCTL_HEADER 0x00040000 /* descriptor is for hdr copy */
116 #define ER_RXCTL_LFFORM 0x00020000 /* alternate fraglist format */
117 #define ER_RXCTL_FRAGLIST 0x00010000 /* descriptor points to fraglist */
118
119 /*
120 * This is not really part of the register description, but we need
121 * to define the number of transmit fragments *somewhere*.
122 */
123 #define EPIC_NFRAGS 16 /* maximum number of frags in list */
124
125 /*
126 * EPIC fraglist descriptor.
127 */
128 struct epic_fraglist {
129 volatile uint32_t ef_nfrags; /* number of frags in list */
130 struct {
131 volatile uint32_t ef_addr; /* address of frag */
132 volatile uint32_t ef_length; /* length of frag */
133 } ef_frags[EPIC_NFRAGS];
134 };
135
136 /*
137 * EPIC control registers.
138 */
139
140 #define EPIC_COMMAND 0x00 /* COMMAND */
141 #define COMMAND_TXUGO 0x00000080 /* start tx after underrun */
142 #define COMMAND_STOP_RDMA 0x00000040 /* stop rx dma */
143 #define COMMAND_STOP_TDMA 0x00000020 /* stop tx dma */
144 #define COMMAND_NEXTFRAME 0x00000010 /* move onto next rx frame */
145 #define COMMAND_RXQUEUED 0x00000008 /* queue a rx descriptor */
146 #define COMMAND_TXQUEUED 0x00000004 /* queue a tx descriptor */
147 #define COMMAND_START_RX 0x00000002 /* start receiver */
148 #define COMMAND_STOP_RX 0x00000001 /* stop receiver */
149
150 #define EPIC_INTSTAT 0x04 /* INTERRUPT STATUS */
151 #define INTSTAT_PTA 0x08000000 /* PCI target abort */
152 #define INTSTAT_PMA 0x04000000 /* PCI master abort */
153 #define INTSTAT_APE 0x02000000 /* PCI address parity error */
154 #define INTSTAT_DPE 0x01000000 /* PCI data parity error */
155 #define INTSTAT_RSV 0x00800000 /* rx status valid */
156 #define INTSTAT_RCTS 0x00400000 /* rx copy threshold status */
157 #define INTSTAT_RBE 0x00200000 /* rx buffers empty */
158 #define INTSTAT_TCIP 0x00100000 /* tx copy in progress */
159 #define INTSTAT_RCIP 0x00080000 /* rx copy in progress */
160 #define INTSTAT_TXIDLE 0x00040000 /* transmit idle */
161 #define INTSTAT_RXIDLE 0x00020000 /* receive idle */
162 #define INTSTAT_INT_ACTV 0x00010000 /* interrupt active */
163 #define INTSTAT_GP2_INT 0x00008000 /* gpio2 low (PHY event) */
164 #define INTSTAT_FATAL_INT 0x00001000 /* fatal error occurred */
165 #define INTSTAT_RCT 0x00000800 /* rx copy threshold crossed */
166 #define INTSTAT_PREI 0x00000400 /* preemptive interrupt */
167 #define INTSTAT_CNT 0x00000200 /* counter overflow */
168 #define INTSTAT_TXU 0x00000100 /* transmit underrun */
169 #define INTSTAT_TQE 0x00000080 /* transmit queue empty */
170 #define INTSTAT_TCC 0x00000040 /* transmit chain complete */
171 #define INTSTAT_TXC 0x00000020 /* transmit complete */
172 #define INTSTAT_RXE 0x00000010 /* receive error */
173 #define INTSTAT_OVW 0x00000008 /* rx buffer overflow */
174 #define INTSTAT_RQE 0x00000004 /* receive queue empty */
175 #define INTSTAT_HCC 0x00000002 /* header copy complete */
176 #define INTSTAT_RCC 0x00000001 /* receive copy complete */
177
178 #define EPIC_INTMASK 0x08 /* INTERRUPT MASK */
179 /* Bits 0-15 enable the corresponding interrupt in INTSTAT. */
180
181 #define EPIC_GENCTL 0x0c /* GENERAL CONTROL */
182 #define GENCTL_RESET_PHY 0x00004000 /* reset PHY */
183 #define GENCTL_SOFT1 0x00002000 /* software use */
184 #define GENCTL_SOFT0 0x00001000 /* software use */
185 #define GENCTL_MEM_READ_CTL1 0x00000800 /* PCI memory control */
186 #define GENCTL_MEM_READ_CTL0 0x00000400 /* (see below) */
187 #define GENCTL_RX_FIFO_THRESH1 0x00000200 /* rx fifo thresh */
188 #define GENCTL_RX_FIFO_THRESH0 0x00000100 /* (see below) */
189 #define GENCTL_BIG_ENDIAN 0x00000020 /* big endian mode */
190 #define GENCTL_ONECOPY 0x00000010 /* auto-NEXTFRAME */
191 #define GENCTL_POWERDOWN 0x00000008 /* powersave sleep mode */
192 #define GENCTL_SOFTINT 0x00000004 /* software-generated intr */
193 #define GENCTL_INTENA 0x00000002 /* interrupt enable */
194 #define GENCTL_SOFTRESET 0x00000001 /* initialize EPIC */
195
196 /*
197 * Explanation of MEMORY READ CONTROL:
198 *
199 * These bits control which PCI command the transmit DMA will use when
200 * bursting data over the PCI bus. When CTL1 is set, the transmit DMA
201 * will use the PCI "memory read line" command. When CTL0 is set, the
202 * transmit DMA will use the PCI "memory read multiple" command. When
203 * neither bit is set, the transmit DMA will use the "memory read" command.
204 * Use of "memory read line" or "memory read multiple" may enhance
205 * performance on some systems.
206 */
207
208 /*
209 * Explanation of RECEIVE FIFO THRESHOLD:
210 *
211 * Controls the level at which the PCI burst state machine begins to
212 * empty the receive FIFO. Default is "1/2 full" (0,1).
213 *
214 * 0,0 1/4 full 32 bytes
215 * 0,1 1/2 full 64 bytes
216 * 1,0 3/4 full 96 bytes
217 * 1,1 full 128 bytes
218 */
219
220 #define EPIC_NVCTL 0x10 /* NON-VOLATILE CONTROL */
221 #define NVCTL_IPG_DLY_MASK 0x00000780 /* interpacket delay gap */
222 #define NVCTL_CB_MODE 0x00000040 /* CardBus mode */
223 #define NVCTL_GPIO2 0x00000020 /* general purpose i/o */
224 #define NVCTL_GPIO1 0x00000010 /* ... */
225 #define NVCTL_GPOE2 0x00000008 /* general purpose output ena */
226 #define NVCTL_GPOE1 0x00000004 /* ... */
227 #define NVCTL_CLKRUNSUPP 0x00000002 /* clock run supported */
228 #define NVCTL_ENAMEMMAP 0x00000001 /* enable memory map */
229
230 #define NVCTL_IPG_DLY(x) (((x) & NVCTL_IPG_DLY_MASK) >> 7)
231
232 #define EPIC_EECTL 0x14 /* EEPROM CONTROL */
233 #define EECTL_EEPROMSIZE 0x00000040 /* eeprom size; see below */
234 #define EECTL_EERDY 0x00000020 /* eeprom ready */
235 #define EECTL_EEDO 0x00000010 /* eeprom data out (from) */
236 #define EECTL_EEDI 0x00000008 /* eeprom data in (to) */
237 #define EECTL_EESK 0x00000004 /* eeprom clock */
238 #define EECTL_EECS 0x00000002 /* eeprom chip select */
239 #define EECTL_ENABLE 0x00000001 /* eeprom enable */
240
241 /*
242 * Explanation of EEPROM SIZE:
243 *
244 * Indicates the size of the serial EEPROM:
245 *
246 * 1 16x16 or 64x16
247 * 0 128x16 or 256x16
248 */
249
250 /*
251 * Serial EEPROM opcodes, including start bit:
252 */
253 #define EPIC_EEPROM_OPC_WRITE 0x05
254 #define EPIC_EEPROM_OPC_READ 0x06
255
256 #define EPIC_PBLCNT 0x18 /* PBLCNT */
257 #define PBLCNT_MASK 0x0000003f /* programmable burst length */
258
259 #define EPIC_TEST 0x1c /* TEST */
260 #define TEST_CLOCKTEST 0x00000008
261
262 #define EPIC_CRCCNT 0x20 /* CRC ERROR COUNTER */
263 #define CRCCNT_MASK 0x0000000f /* crc errs since last read */
264
265 #define EPIC_ALICNT 0x24 /* FRAME ALIGNMENT ERROR COUNTER */
266 #define ALICNT_MASK 0x0000000f /* align errs since last read */
267
268 #define EPIC_MPCNT 0x28 /* MISSED PACKET COUNTER */
269 #define MPCNT_MASK 0x0000000f /* miss. pkts since last read */
270
271 #define EPIC_RXFIFO 0x2c
272
273 #define EPIC_MMCTL 0x30 /* MII MANAGEMENT INTERFACE CONTROL */
274 #define MMCTL_PHY_ADDR_MASK 0x00003e00 /* phy address field */
275 #define MMCTL_PHY_REG_ADDR_MASK 0x000001f0 /* phy register address field */
276 #define MMCTL_RESPONDER 0x00000008 /* phy responder */
277 #define MMCTL_WRITE 0x00000002 /* write to phy */
278 #define MMCTL_READ 0x00000001 /* read from phy */
279
280 #define MMCTL_ARG(phy, reg, cmd) (((phy) << 9) | ((reg) << 4) | (cmd))
281
282 #define EPIC_MMDATA 0x34 /* MII MANAGEMENT INTERFACE DATA */
283 #define MMDATA_MASK 0x0000ffff /* MII frame data */
284
285 #define EPIC_MIICFG 0x38 /* MII CONFIGURATION */
286 #define MIICFG_ALTDIR 0x00000080 /* alternate direction */
287 #define MIICFG_ALTDATA 0x00000040 /* alternate data */
288 #define MIICFG_ALTCLOCK 0x00000020 /* alternate clock source */
289 #define MIICFG_ENASER 0x00000010 /* enable serial manag intf */
290 #define MIICFG_PHYPRESENT 0x00000008 /* phy present on MII */
291 #define MIICFG_LINKSTATUS 0x00000004 /* 694 link status */
292 #define MIICFG_ENABLE 0x00000002 /* enable 694 */
293 #define MIICFG_SERMODEENA 0x00000001 /* serial mode enable */
294
295 #define EPIC_IPG 0x3c /* INTERPACKET GAP */
296 #define IPG_INTERFRAME_MASK 0x00007f00 /* interframe gap time */
297 #define IPG_INTERPKT_MASK 0x000000ff /* interpacket gap time */
298
299 #define EPIC_LAN0 0x40 /* LAN ADDRESS */
300
301 #define EPIC_LAN1 0x44
302
303 #define EPIC_LAN2 0x48
304
305 #define LANn_MASK 0x0000ffff
306
307 /*
308 * Explanation of LAN ADDRESS registers:
309 *
310 * LAN address is described as:
311 *
312 * 0000 [n1][n0][n3][n2] | 0000 [n5][n4][n7][n6] | 0000 [n9][n8][n11][n10]
313 *
314 * n == one nibble, mapped as follows:
315 *
316 * LAN0 [15-12] n3
317 * LAN0 [11-8] n2
318 * LAN0 [7-4] n1
319 * LAN0 [3-0] n0
320 * LAN1 [15-12] n7
321 * LAN1 [11-8] n6
322 * LAN1 [7-4] n5
323 * LAN1 [3-0] n4
324 * LAN2 [15-12] n11
325 * LAN2 [11-8] n10
326 * LAN2 [7-4] n9
327 * LAN2 [3-0] n8
328 *
329 * The LAN address is automatically recalled from the EEPROM after a
330 * hard reseet.
331 */
332
333 #define EPIC_IDCHK 0x4c /* BOARD ID/CHECKSUM */
334 #define IDCHK_ID_MASK 0x0000ff00 /* board ID */
335 #define IDCHK_CKSUM_MASK 0x000000ff /* checksum (should be 0xff) */
336
337 #define EPIC_MC0 0x50 /* MULTICAST ADDRESS HASH TABLE */
338
339 #define EPIC_MC1 0x54
340
341 #define EPIC_MC2 0x58
342
343 #define EPIC_MC3 0x5c
344
345 /*
346 * Explanation of MULTICAST ADDRESS HASH TABLE registers:
347 *
348 * Bits in the hash table are encoded as follows:
349 *
350 * MC0 [15-0]
351 * MC1 [31-16]
352 * MC2 [47-32]
353 * MC3 [53-48]
354 */
355
356 #define EPIC_RXCON 0x60 /* RECEIVE CONTROL */
357 #define RXCON_EXTBUFSIZESEL1 0x00000200 /* ext buf size; see below */
358 #define RXCON_EXTBUFSIZESEL0 0x00000100 /* ... */
359 #define RXCON_EARLYRXENABLE 0x00000080 /* early receive enable */
360 #define RXCON_MONITORMODE 0x00000040 /* monitor mode */
361 #define RXCON_PROMISCMODE 0x00000020 /* promiscuous mode */
362 #define RXCON_RXINVADDR 0x00000010 /* rx inv individual addr */
363 #define RXCON_RXMULTICAST 0x00000008 /* receive multicast */
364 #define RXCON_RXBROADCAST 0x00000004 /* receive broadcast */
365 #define RXCON_RXRUNT 0x00000002 /* receive runt frames */
366 #define RXCON_SAVEERRPKTS 0x00000001 /* save errored packets */
367
368 /*
369 * Explanation of EXTERNAL BUFFER SIZE SELECT:
370 *
371 * 0,0 external buffer access is disabled
372 * 0,1 16k
373 * 1,0 32k
374 * 1,1 128k
375 */
376
377 #define EPIC_RXSTAT 0x64 /* RECEIVE STATUS */
378
379 #define EPIC_RXCNT 0x68
380
381 #define EPIC_RXTEST 0x6c
382
383 #define EPIC_TXCON 0x70 /* TRANSMIT CONTROL */
384 #define TXCON_SLOTTIME_MASK 0x000000f8 /* slot time */
385 #define TXCON_LOOPBACK_D2 0x00000004 /* loopback mode bit 2 */
386 #define TXCON_LOOPBACK_D1 0x00000002 /* loopback mode bit 1 */
387 #define TXCON_EARLYTX_ENABLE 0x00000001 /* early transmit enable */
388
389 /*
390 * Explanation of LOOPBACK MODE BIT:
391 *
392 * 0,0 normal operation
393 * 0,1 internal loopback (before PHY)
394 * 1,0 external loopback (after PHY)
395 * 1,1 full duplex - decouples transmit and receive blocks
396 */
397
398 #define EPIC_TXSTAT 0x74 /* TRANSMIT STATUS */
399
400 #define EPIC_TDPAR 0x78
401
402 #define EPIC_TXTEST 0x7c
403
404 #define EPIC_PRFDAR 0x80
405
406 #define EPIC_PRCDAR 0x84 /* PCI RECEIVE CURRENT DESCRIPTOR ADDR */
407
408 #define EPIC_PRHDAR 0x88
409
410 #define EPIC_PRFLAR 0x8c
411
412 #define EPIC_PRDLGTH 0x90
413
414 #define EPIC_PRFCNT 0x94
415
416 #define EPIC_PRLCAR 0x98
417
418 #define EPIC_PRLPAR 0x9c
419
420 #define EPIC_PREFAR 0xa0
421
422 #define EPIC_PRSTAT 0xa4 /* PCI RECEIVE DMA STATUS */
423
424 #define EPIC_PRBUF 0xa8
425
426 #define EPIC_RDNCAR 0xac
427
428 #define EPIC_PRCPTHR 0xb0 /* PCI RECEIVE COPY THRESHOLD */
429
430 #define EPIC_ROMDATA 0xb4
431
432 #define EPIC_PREEMPR 0xbc
433
434 #define EPIC_PTFDAR 0xc0
435
436 #define EPIC_PTCDAR 0xc4 /* PCI TRANSMIT CURRENT DESCRIPTOR ADDR */
437
438 #define EPIC_PTHDAR 0xc8
439
440 #define EPIC_PTFLAR 0xcc
441
442 #define EPIC_PTDLGTH 0xd0
443
444 #define EPIC_PTFCNT 0xd4
445
446 #define EPIC_PTLCAR 0xd8
447
448 #define EPIC_ETXTHR 0xdc /* EARLY TRANSMIT THRESHOLD */
449
450 #define EPIC_PTETXC 0xe0
451
452 #define EPIC_PTSTAT 0xe4
453
454 #define EPIC_PTBUF 0xe8
455
456 #define EPIC_PTFDAR2 0xec
457
458 #define EPIC_FEVTR 0xf0 /* FEVTR (CardBus) */
459
460 #define EPIC_FEVTRMSKR 0xf4 /* FEVTRMSKR (CardBus) */
461
462 #define EPIC_FPRSTSTR 0xf8 /* FPRSTR (CardBus) */
463
464 #define EPIC_FFRCEVTR 0xfc /* PPRCEVTR (CardBus) */
465
466 /*
467 * EEPROM format:
468 *
469 * Word Bits Description
470 * ---- ---- -----------
471 * 0 7-0 LAN Address Byte 0
472 * 0 15-8 LAN Address Byte 1
473 * 1 7-0 LAN Address Byte 2
474 * 1 15-8 LAN Address Byte 3
475 * 2 7-0 LAN Address Byte 4
476 * 2 15-8 LAN Address Byte 5
477 * 3 7-0 Board ID
478 * 3 15-8 Checksum
479 * 4 5-0 Non-Volatile Control Register Contents
480 * 5 7-0 PCI Minimum Grant Desired Setting
481 * 5 15-8 PCI Maximum Latency Desired Setting
482 * 6 15-0 Subsystem Vendor ID
483 * 7 14-0 Subsystem ID
484 */
485
486 #endif /* _DEV_IC_SMC83C170REG_H_ */
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