1 /* $OpenBSD: smc83c170reg.h,v 1.3 2022/01/09 05:42:42 jsg Exp $ */
2 /* $NetBSD: smc83c170reg.h,v 1.9 2003/11/08 16:08:13 tsutsui Exp $ */
3
4 /*-
5 * Copyright (c) 1998 The NetBSD Foundation, Inc.
6 * All rights reserved.
7 *
8 * This code is derived from software contributed to The NetBSD Foundation
9 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
10 * NASA Ames Research Center.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef _DEV_IC_SMC83C170REG_H_
35 #define _DEV_IC_SMC83C170REG_H_
36
37 /*
38 * Register description for the Standard Microsystems Corp. 83C170
39 * Ethernet PCI Integrated Controller (EPIC/100).
40 */
41
42 /*
43 * EPIC transmit descriptor. Must be 4-byte aligned.
44 */
45 struct epic_txdesc {
46 u_int32_t et_txstatus; /* transmit status; see below */
47 u_int32_t et_bufaddr; /* buffer address */
48 u_int32_t et_control; /* control word; see below */
49 u_int32_t et_nextdesc; /* next descriptor pointer */
50 };
51
52 /* et_txstatus */
53 #define TXSTAT_TXLENGTH_SHIFT 16 /* TX length in higher 16bits */
54 #define TXSTAT_TXLENGTH(x) ((x) << TXSTAT_TXLENGTH_SHIFT)
55
56 #define ET_TXSTAT_OWNER 0x8000 /* NIC owns descriptor */
57 #define ET_TXSTAT_COLLMASK 0x1f00 /* collisions */
58 #define ET_TXSTAT_DEFERRING 0x0080 /* deferring due to jabber */
59 #define ET_TXSTAT_OOWCOLL 0x0040 /* out of window collision */
60 #define ET_TXSTAT_CDHB 0x0020 /* collision detect heartbeat */
61 #define ET_TXSTAT_UNDERRUN 0x0010 /* DMA underrun */
62 #define ET_TXSTAT_CARSENSELOST 0x0008 /* carrier lost */
63 #define ET_TXSTAT_TXWITHCOLL 0x0004 /* encountered collisions during tx */
64 #define ET_TXSTAT_NONDEFERRED 0x0002 /* transmitted without deferring */
65 #define ET_TXSTAT_PACKETTX 0x0001 /* packet transmitted successfully */
66
67 #define TXSTAT_COLLISIONS(x) (((x) & ET_TXSTAT_COLLMASK) >> 8)
68
69 /* et_control */
70 #define TXCTL_BUFLENGTH_MASK 0x0000ffff /* buf length in lower 16bits */
71 #define TXCTL_BUFLENGTH(x) ((x) & TXCTL_BUFLENGTH_MASK)
72
73 #define ET_TXCTL_LASTDESC 0x00100000 /* last descriptor in frame */
74 #define ET_TXCTL_NOCRC 0x00080000 /* disable CRC generation */
75 #define ET_TXCTL_IAF 0x00040000 /* interrupt after frame */
76 #define ET_TXCTL_LFFORM 0x00020000 /* alternate fraglist format */
77 #define ET_TXCTL_FRAGLIST 0x00010000 /* descriptor points to fraglist */
78
79 /*
80 * EPIC receive descriptor. Must be 4-byte aligned.
81 */
82 struct epic_rxdesc {
83 u_int32_t er_rxstatus; /* receive status; see below */
84 u_int32_t er_bufaddr; /* buffer address */
85 u_int32_t er_control; /* control word; see below */
86 u_int32_t er_nextdesc; /* next descriptor pointer */
87 };
88
89 /* er_rxstatus */
90 #define RXSTAT_RXLENGTH_SHIFT 16 /* TX length in higher 16bits */
91 #define RXSTAT_RXLENGTH(x) ((x) >> RXSTAT_RXLENGTH_SHIFT)
92
93 #define ER_RXSTAT_OWNER 0x8000 /* NIC owns descriptor */
94 #define ER_RXSTAT_HDRCOPIED 0x4000 /* rx status posted after hdr copy */
95 #define ER_RXSTAT_FRAGLISTERR 0x2000 /* ran out of frags to copy frame */
96 #define ER_RXSTAT_NETSTATVALID 0x1000 /* length and status are valid */
97 #define ER_RXSTAT_RCVRDIS 0x0040 /* receiver disabled */
98 #define ER_RXSTAT_BCAST 0x0020 /* broadcast address recognized */
99 #define ER_RXSTAT_MCAST 0x0010 /* multicast address recognized */
100 #define ER_RXSTAT_MISSEDPKT 0x0008 /* missed packet */
101 #define ER_RXSTAT_CRCERROR 0x0004 /* EPIC or MII asserted CRC error */
102 #define ER_RXSTAT_ALIGNERROR 0x0002 /* frame not byte-aligned */
103 #define ER_RXSTAT_PKTINTACT 0x0001 /* packet received without error */
104
105 /* er_control */
106 #define RXCTL_BUFLENGTH_MASK 0x0000ffff /* buf length in lower 16bits */
107 #define RXCTL_BUFLENGTH(x) ((x) & RXCTL_BUFLENGTH_MASK)
108
109 #define ER_RXCTL_HEADER 0x00040000 /* descriptor is for hdr copy */
110 #define ER_RXCTL_LFFORM 0x00020000 /* alternate fraglist format */
111 #define ER_RXCTL_FRAGLIST 0x00010000 /* descriptor points to fraglist */
112
113 /*
114 * This is not really part of the register description, but we need
115 * to define the number of transmit fragments *somewhere*.
116 */
117 #define EPIC_NFRAGS 16 /* maximum number of frags in list */
118
119 /*
120 * EPIC fraglist descriptor.
121 */
122 struct epic_fraglist {
123 u_int32_t ef_nfrags; /* number of frags in list */
124 struct {
125 u_int32_t ef_addr; /* address of frag */
126 u_int32_t ef_length; /* length of frag */
127 } ef_frags[EPIC_NFRAGS];
128 };
129
130 /*
131 * EPIC control registers.
132 */
133
134 #define EPIC_COMMAND 0x00 /* COMMAND */
135 #define COMMAND_TXUGO 0x00000080 /* start tx after underrun */
136 #define COMMAND_STOP_RDMA 0x00000040 /* stop rx dma */
137 #define COMMAND_STOP_TDMA 0x00000020 /* stop tx dma */
138 #define COMMAND_NEXTFRAME 0x00000010 /* move onto next rx frame */
139 #define COMMAND_RXQUEUED 0x00000008 /* queue a rx descriptor */
140 #define COMMAND_TXQUEUED 0x00000004 /* queue a tx descriptor */
141 #define COMMAND_START_RX 0x00000002 /* start receiver */
142 #define COMMAND_STOP_RX 0x00000001 /* stop receiver */
143
144 #define EPIC_INTSTAT 0x04 /* INTERRUPT STATUS */
145 #define INTSTAT_PTA 0x08000000 /* PCI target abort */
146 #define INTSTAT_PMA 0x04000000 /* PCI master abort */
147 #define INTSTAT_APE 0x02000000 /* PCI address parity error */
148 #define INTSTAT_DPE 0x01000000 /* PCI data parity error */
149 #define INTSTAT_RSV 0x00800000 /* rx status valid */
150 #define INTSTAT_RCTS 0x00400000 /* rx copy threshold status */
151 #define INTSTAT_RBE 0x00200000 /* rx buffers empty */
152 #define INTSTAT_TCIP 0x00100000 /* tx copy in progress */
153 #define INTSTAT_RCIP 0x00080000 /* rx copy in progress */
154 #define INTSTAT_TXIDLE 0x00040000 /* transmit idle */
155 #define INTSTAT_RXIDLE 0x00020000 /* receive idle */
156 #define INTSTAT_INT_ACTV 0x00010000 /* interrupt active */
157 #define INTSTAT_GP2_INT 0x00008000 /* gpio2 low (PHY event) */
158 #define INTSTAT_FATAL_INT 0x00001000 /* fatal error occurred */
159 #define INTSTAT_RCT 0x00000800 /* rx copy threshold crossed */
160 #define INTSTAT_PREI 0x00000400 /* preemptive interrupt */
161 #define INTSTAT_CNT 0x00000200 /* counter overflow */
162 #define INTSTAT_TXU 0x00000100 /* transmit underrun */
163 #define INTSTAT_TQE 0x00000080 /* transmit queue empty */
164 #define INTSTAT_TCC 0x00000040 /* transmit chain complete */
165 #define INTSTAT_TXC 0x00000020 /* transmit complete */
166 #define INTSTAT_RXE 0x00000010 /* receive error */
167 #define INTSTAT_OVW 0x00000008 /* rx buffer overflow */
168 #define INTSTAT_RQE 0x00000004 /* receive queue empty */
169 #define INTSTAT_HCC 0x00000002 /* header copy complete */
170 #define INTSTAT_RCC 0x00000001 /* receive copy complete */
171
172 #define EPIC_INTMASK 0x08 /* INTERRUPT MASK */
173 /* Bits 0-15 enable the corresponding interrupt in INTSTAT. */
174
175 #define EPIC_GENCTL 0x0c /* GENERAL CONTROL */
176 #define GENCTL_RESET_PHY 0x00004000 /* reset PHY */
177 #define GENCTL_SOFT1 0x00002000 /* software use */
178 #define GENCTL_SOFT0 0x00001000 /* software use */
179 #define GENCTL_MEM_READ_CTL1 0x00000800 /* PCI memory control */
180 #define GENCTL_MEM_READ_CTL0 0x00000400 /* (see below) */
181 #define GENCTL_RX_FIFO_THRESH1 0x00000200 /* rx fifo thresh */
182 #define GENCTL_RX_FIFO_THRESH0 0x00000100 /* (see below) */
183 #define GENCTL_BIG_ENDIAN 0x00000020 /* big endian mode */
184 #define GENCTL_ONECOPY 0x00000010 /* auto-NEXTFRAME */
185 #define GENCTL_POWERDOWN 0x00000008 /* powersave sleep mode */
186 #define GENCTL_SOFTINT 0x00000004 /* software-generated intr */
187 #define GENCTL_INTENA 0x00000002 /* interrupt enable */
188 #define GENCTL_SOFTRESET 0x00000001 /* initialize EPIC */
189
190 /*
191 * Explanation of MEMORY READ CONTROL:
192 *
193 * These bits control which PCI command the transmit DMA will use when
194 * bursting data over the PCI bus. When CTL1 is set, the transmit DMA
195 * will use the PCI "memory read line" command. When CTL0 is set, the
196 * transmit DMA will use the PCI "memory read multiple" command. When
197 * neither bit is set, the transmit DMA will use the "memory read" command.
198 * Use of "memory read line" or "memory read multiple" may enhance
199 * performance on some systems.
200 */
201
202 /*
203 * Explanation of RECEIVE FIFO THRESHOLD:
204 *
205 * Controls the level at which the PCI burst state machine begins to
206 * empty the receive FIFO. Default is "1/2 full" (0,1).
207 *
208 * 0,0 1/4 full 32 bytes
209 * 0,1 1/2 full 64 bytes
210 * 1,0 3/4 full 96 bytes
211 * 1,1 full 128 bytes
212 */
213
214 #define EPIC_NVCTL 0x10 /* NON-VOLATILE CONTROL */
215 #define NVCTL_IPG_DLY_MASK 0x00000780 /* interpacket delay gap */
216 #define NVCTL_CB_MODE 0x00000040 /* CardBus mode */
217 #define NVCTL_GPIO2 0x00000020 /* general purpose i/o */
218 #define NVCTL_GPIO1 0x00000010 /* ... */
219 #define NVCTL_GPOE2 0x00000008 /* general purpose output ena */
220 #define NVCTL_GPOE1 0x00000004 /* ... */
221 #define NVCTL_CLKRUNSUPP 0x00000002 /* clock run supported */
222 #define NVCTL_ENAMEMMAP 0x00000001 /* enable memory map */
223
224 #define NVCTL_IPG_DLY(x) (((x) & NVCTL_IPG_DLY_MASK) >> 7)
225
226 #define EPIC_EECTL 0x14 /* EEPROM CONTROL */
227 #define EECTL_EEPROMSIZE 0x00000040 /* eeprom size; see below */
228 #define EECTL_EERDY 0x00000020 /* eeprom ready */
229 #define EECTL_EEDO 0x00000010 /* eeprom data out (from) */
230 #define EECTL_EEDI 0x00000008 /* eeprom data in (to) */
231 #define EECTL_EESK 0x00000004 /* eeprom clock */
232 #define EECTL_EECS 0x00000002 /* eeprom chip select */
233 #define EECTL_ENABLE 0x00000001 /* eeprom enable */
234
235 /*
236 * Explanation of EEPROM SIZE:
237 *
238 * Indicates the size of the serial EEPROM:
239 *
240 * 1 16x16 or 64x16
241 * 0 128x16 or 256x16
242 */
243
244 /*
245 * Serial EEPROM opcodes, including start bit:
246 */
247 #define EPIC_EEPROM_OPC_WRITE 0x05
248 #define EPIC_EEPROM_OPC_READ 0x06
249
250 #define EPIC_PBLCNT 0x18 /* PBLCNT */
251 #define PBLCNT_MASK 0x0000003f /* programmable burst length */
252
253 #define EPIC_TEST 0x1c /* TEST */
254 #define TEST_CLOCKTEST 0x00000008
255
256 #define EPIC_CRCCNT 0x20 /* CRC ERROR COUNTER */
257 #define CRCCNT_MASK 0x0000000f /* crc errs since last read */
258
259 #define EPIC_ALICNT 0x24 /* FRAME ALIGNMENT ERROR COUNTER */
260 #define ALICNT_MASK 0x0000000f /* align errs since last read */
261
262 #define EPIC_MPCNT 0x28 /* MISSED PACKET COUNTER */
263 #define MPCNT_MASK 0x0000000f /* miss. pkts since last read */
264
265 #define EPIC_RXFIFO 0x2c
266
267 #define EPIC_MMCTL 0x30 /* MII MANAGEMENT INTERFACE CONTROL */
268 #define MMCTL_PHY_ADDR_MASK 0x00003e00 /* phy address field */
269 #define MMCTL_PHY_REG_ADDR_MASK 0x000001f0 /* phy register address field */
270 #define MMCTL_RESPONDER 0x00000008 /* phy responder */
271 #define MMCTL_WRITE 0x00000002 /* write to phy */
272 #define MMCTL_READ 0x00000001 /* read from phy */
273
274 #define MMCTL_ARG(phy, reg, cmd) (((phy) << 9) | ((reg) << 4) | (cmd))
275
276 #define EPIC_MMDATA 0x34 /* MII MANAGEMENT INTERFACE DATA */
277 #define MMDATA_MASK 0x0000ffff /* MII frame data */
278
279 #define EPIC_MIICFG 0x38 /* MII CONFIGURATION */
280 #define MIICFG_ALTDIR 0x00000080 /* alternate direction */
281 #define MIICFG_ALTDATA 0x00000040 /* alternate data */
282 #define MIICFG_ALTCLOCK 0x00000020 /* alternate clock source */
283 #define MIICFG_ENASER 0x00000010 /* enable serial manag intf */
284 #define MIICFG_PHYPRESENT 0x00000008 /* phy present on MII */
285 #define MIICFG_LINKSTATUS 0x00000004 /* 694 link status */
286 #define MIICFG_ENABLE 0x00000002 /* enable 694 */
287 #define MIICFG_SERMODEENA 0x00000001 /* serial mode enable */
288
289 #define EPIC_IPG 0x3c /* INTERPACKET GAP */
290 #define IPG_INTERFRAME_MASK 0x00007f00 /* interframe gap time */
291 #define IPG_INTERPKT_MASK 0x000000ff /* interpacket gap time */
292
293 #define EPIC_LAN0 0x40 /* LAN ADDRESS */
294
295 #define EPIC_LAN1 0x44
296
297 #define EPIC_LAN2 0x48
298
299 #define LANn_MASK 0x0000ffff
300
301 /*
302 * Explanation of LAN ADDRESS registers:
303 *
304 * LAN address is described as:
305 *
306 * 0000 [n1][n0][n3][n2] | 0000 [n5][n4][n7][n6] | 0000 [n9][n8][n11][n10]
307 *
308 * n == one nibble, mapped as follows:
309 *
310 * LAN0 [15-12] n3
311 * LAN0 [11-8] n2
312 * LAN0 [7-4] n1
313 * LAN0 [3-0] n0
314 * LAN1 [15-12] n7
315 * LAN1 [11-8] n6
316 * LAN1 [7-4] n5
317 * LAN1 [3-0] n4
318 * LAN2 [15-12] n11
319 * LAN2 [11-8] n10
320 * LAN2 [7-4] n9
321 * LAN2 [3-0] n8
322 *
323 * The LAN address is automatically recalled from the EEPROM after a
324 * hard reset.
325 */
326
327 #define EPIC_IDCHK 0x4c /* BOARD ID/CHECKSUM */
328 #define IDCHK_ID_MASK 0x0000ff00 /* board ID */
329 #define IDCHK_CKSUM_MASK 0x000000ff /* checksum (should be 0xff) */
330
331 #define EPIC_MC0 0x50 /* MULTICAST ADDRESS HASH TABLE */
332
333 #define EPIC_MC1 0x54
334
335 #define EPIC_MC2 0x58
336
337 #define EPIC_MC3 0x5c
338
339 /*
340 * Explanation of MULTICAST ADDRESS HASH TABLE registers:
341 *
342 * Bits in the hash table are encoded as follows:
343 *
344 * MC0 [15-0]
345 * MC1 [31-16]
346 * MC2 [47-32]
347 * MC3 [53-48]
348 */
349
350 #define EPIC_RXCON 0x60 /* RECEIVE CONTROL */
351 #define RXCON_EXTBUFSIZESEL1 0x00000200 /* ext buf size; see below */
352 #define RXCON_EXTBUFSIZESEL0 0x00000100 /* ... */
353 #define RXCON_EARLYRXENABLE 0x00000080 /* early receive enable */
354 #define RXCON_MONITORMODE 0x00000040 /* monitor mode */
355 #define RXCON_PROMISCMODE 0x00000020 /* promiscuous mode */
356 #define RXCON_RXINVADDR 0x00000010 /* rx inv individual addr */
357 #define RXCON_RXMULTICAST 0x00000008 /* receive multicast */
358 #define RXCON_RXBROADCAST 0x00000004 /* receive broadcast */
359 #define RXCON_RXRUNT 0x00000002 /* receive runt frames */
360 #define RXCON_SAVEERRPKTS 0x00000001 /* save errored packets */
361
362 /*
363 * Explanation of EXTERNAL BUFFER SIZE SELECT:
364 *
365 * 0,0 external buffer access is disabled
366 * 0,1 16k
367 * 1,0 32k
368 * 1,1 128k
369 */
370
371 #define EPIC_RXSTAT 0x64 /* RECEIVE STATUS */
372
373 #define EPIC_RXCNT 0x68
374
375 #define EPIC_RXTEST 0x6c
376
377 #define EPIC_TXCON 0x70 /* TRANSMIT CONTROL */
378 #define TXCON_SLOTTIME_MASK 0x000000f8 /* slot time */
379 #define TXCON_LOOPBACK_D2 0x00000004 /* loopback mode bit 2 */
380 #define TXCON_LOOPBACK_D1 0x00000002 /* loopback mode bit 1 */
381 #define TXCON_EARLYTX_ENABLE 0x00000001 /* early transmit enable */
382
383 /*
384 * Explanation of LOOPBACK MODE BIT:
385 *
386 * 0,0 normal operation
387 * 0,1 internal loopback (before PHY)
388 * 1,0 external loopback (after PHY)
389 * 1,1 full duplex - decouples transmit and receive blocks
390 */
391
392 #define EPIC_TXSTAT 0x74 /* TRANSMIT STATUS */
393
394 #define EPIC_TDPAR 0x78
395
396 #define EPIC_TXTEST 0x7c
397
398 #define EPIC_PRFDAR 0x80
399
400 #define EPIC_PRCDAR 0x84 /* PCI RECEIVE CURRENT DESCRIPTOR ADDR */
401
402 #define EPIC_PRHDAR 0x88
403
404 #define EPIC_PRFLAR 0x8c
405
406 #define EPIC_PRDLGTH 0x90
407
408 #define EPIC_PRFCNT 0x94
409
410 #define EPIC_PRLCAR 0x98
411
412 #define EPIC_PRLPAR 0x9c
413
414 #define EPIC_PREFAR 0xa0
415
416 #define EPIC_PRSTAT 0xa4 /* PCI RECEIVE DMA STATUS */
417
418 #define EPIC_PRBUF 0xa8
419
420 #define EPIC_RDNCAR 0xac
421
422 #define EPIC_PRCPTHR 0xb0 /* PCI RECEIVE COPY THRESHOLD */
423
424 #define EPIC_ROMDATA 0xb4
425
426 #define EPIC_PREEMPR 0xbc
427
428 #define EPIC_PTFDAR 0xc0
429
430 #define EPIC_PTCDAR 0xc4 /* PCI TRANSMIT CURRENT DESCRIPTOR ADDR */
431
432 #define EPIC_PTHDAR 0xc8
433
434 #define EPIC_PTFLAR 0xcc
435
436 #define EPIC_PTDLGTH 0xd0
437
438 #define EPIC_PTFCNT 0xd4
439
440 #define EPIC_PTLCAR 0xd8
441
442 #define EPIC_ETXTHR 0xdc /* EARLY TRANSMIT THRESHOLD */
443
444 #define EPIC_PTETXC 0xe0
445
446 #define EPIC_PTSTAT 0xe4
447
448 #define EPIC_PTBUF 0xe8
449
450 #define EPIC_PTFDAR2 0xec
451
452 #define EPIC_FEVTR 0xf0 /* FEVTR (CardBus) */
453
454 #define EPIC_FEVTRMSKR 0xf4 /* FEVTRMSKR (CardBus) */
455
456 #define EPIC_FPRSTSTR 0xf8 /* FPRSTR (CardBus) */
457
458 #define EPIC_FFRCEVTR 0xfc /* PPRCEVTR (CardBus) */
459
460 /*
461 * EEPROM format:
462 *
463 * Word Bits Description
464 * ---- ---- -----------
465 * 0 7-0 LAN Address Byte 0
466 * 0 15-8 LAN Address Byte 1
467 * 1 7-0 LAN Address Byte 2
468 * 1 15-8 LAN Address Byte 3
469 * 2 7-0 LAN Address Byte 4
470 * 2 15-8 LAN Address Byte 5
471 * 3 7-0 Board ID
472 * 3 15-8 Checksum
473 * 4 5-0 Non-Volatile Control Register Contents
474 * 5 7-0 PCI Minimum Grant Desired Setting
475 * 5 15-8 PCI Maximum Latency Desired Setting
476 * 6 15-0 Subsystem Vendor ID
477 * 7 14-0 Subsystem ID
478 */
479
480 #endif /* _DEV_IC_SMC83C170REG_H_ */
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