smc83c170var.h

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    1 /*      $OpenBSD: smc83c170var.h,v 1.5 2022/01/09 05:42:42 jsg Exp $    */
    2 /*      $NetBSD: smc83c170var.h,v 1.9 2005/02/04 02:10:37 perry Exp $   */
    3 
    4 /*-
    5  * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
    6  * All rights reserved.
    7  *
    8  * This code is derived from software contributed to The NetBSD Foundation
    9  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   10  * NASA Ames Research Center.
   11  *
   12  * Redistribution and use in source and binary forms, with or without
   13  * modification, are permitted provided that the following conditions
   14  * are met:
   15  * 1. Redistributions of source code must retain the above copyright
   16  *    notice, this list of conditions and the following disclaimer.
   17  * 2. Redistributions in binary form must reproduce the above copyright
   18  *    notice, this list of conditions and the following disclaimer in the
   19  *    documentation and/or other materials provided with the distribution.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   23  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   24  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   31  * POSSIBILITY OF SUCH DAMAGE.
   32  */
   33 
   34 #ifndef _DEV_IC_SMC83C170VAR_H_
   35 #define _DEV_IC_SMC83C170VAR_H_
   36 
   37 #include <sys/timeout.h>
   38 
   39 /*
   40  * Misc. definitions for the Standard Microsystems Corp. 83C170
   41  * Ethernet PCI Integrated Controller (EPIC/100) driver.
   42  */
   43 
   44 /*
   45  * Transmit descriptor list size.
   46  */
   47 #define EPIC_NTXDESC            128
   48 #define EPIC_NTXDESC_MASK       (EPIC_NTXDESC - 1)
   49 #define EPIC_NEXTTX(x)          ((x + 1) & EPIC_NTXDESC_MASK)
   50 
   51 /*
   52  * Receive descriptor list size.
   53  */
   54 #define EPIC_NRXDESC            64
   55 #define EPIC_NRXDESC_MASK       (EPIC_NRXDESC - 1)
   56 #define EPIC_NEXTRX(x)          ((x + 1) & EPIC_NRXDESC_MASK)
   57 
   58 /*
   59  * Control structures are DMA'd to the EPIC chip.  We allocate them in
   60  * a single clump that maps to a single DMA segment to make several things
   61  * easier.
   62  */
   63 struct epic_control_data {
   64         /*
   65          * The transmit descriptors.
   66          */
   67         struct epic_txdesc ecd_txdescs[EPIC_NTXDESC];
   68 
   69         /*
   70          * The receive descriptors.
   71          */
   72         struct epic_rxdesc ecd_rxdescs[EPIC_NRXDESC];
   73 
   74         /*
   75          * The transmit fraglists.
   76          */
   77         struct epic_fraglist ecd_txfrags[EPIC_NTXDESC];
   78 };
   79 
   80 #define EPIC_CDOFF(x)   offsetof(struct epic_control_data, x)
   81 #define EPIC_CDTXOFF(x) EPIC_CDOFF(ecd_txdescs[(x)])
   82 #define EPIC_CDRXOFF(x) EPIC_CDOFF(ecd_rxdescs[(x)])
   83 #define EPIC_CDFLOFF(x) EPIC_CDOFF(ecd_txfrags[(x)])
   84 
   85 /*
   86  * Software state for transmit and receive descriptors.
   87  */
   88 struct epic_descsoft {
   89         struct mbuf *ds_mbuf;           /* head of mbuf chain */
   90         bus_dmamap_t ds_dmamap;         /* our DMA map */
   91 };
   92 
   93 /*
   94  * Software state per device.
   95  */
   96 struct epic_softc {
   97         struct device sc_dev;           /* generic device information */
   98         bus_space_tag_t sc_st;          /* bus space tag */
   99         bus_space_handle_t sc_sh;       /* bus space handle */
  100         bus_dma_tag_t sc_dmat;          /* bus DMA tag */
  101         struct arpcom sc_arpcom;        /* ethernet common data */
  102 
  103         int sc_hwflags;                 /* info about board */
  104 #define EPIC_HAS_BNC            0x01    /* BNC on serial interface */
  105 #define EPIC_HAS_MII_FIBER      0x02    /* fiber on MII lxtphy */
  106 #define EPIC_DUPLEXLED_ON_694   0x04    /* duplex LED by software */
  107 
  108         struct mii_data sc_mii;         /* MII/media information */
  109         struct timeout sc_mii_timeout;  /* MII timeout */
  110 
  111         bus_dmamap_t sc_cddmamap;       /* control data DMA map */
  112 #define sc_cddma        sc_cddmamap->dm_segs[0].ds_addr
  113         bus_dmamap_t sc_nulldmamap;     /* DMA map for the pad buffer */
  114 #define sc_nulldma      sc_nulldmamap->dm_segs[0].ds_addr
  115 
  116         /*
  117          * Software state for transmit and receive descriptors.
  118          */
  119         struct epic_descsoft sc_txsoft[EPIC_NTXDESC];
  120         struct epic_descsoft sc_rxsoft[EPIC_NRXDESC];
  121 
  122         /*
  123          * Control data structures.
  124          */
  125         struct epic_control_data *sc_control_data;
  126 
  127         int     sc_txpending;           /* number of TX requests pending */
  128         int     sc_txdirty;             /* first dirty TX descriptor */
  129         int     sc_txlast;              /* last used TX descriptor */
  130 
  131         int     sc_rxptr;               /* next ready RX descriptor */
  132 
  133         uint64_t        sc_serinst;     /* ifmedia instance for serial mode */
  134 };
  135 
  136 #define EPIC_CDTXADDR(sc, x)    ((sc)->sc_cddma + EPIC_CDTXOFF((x)))
  137 #define EPIC_CDRXADDR(sc, x)    ((sc)->sc_cddma + EPIC_CDRXOFF((x)))
  138 #define EPIC_CDFLADDR(sc, x)    ((sc)->sc_cddma + EPIC_CDFLOFF((x)))
  139 
  140 #define EPIC_CDTX(sc, x)        (&(sc)->sc_control_data->ecd_txdescs[(x)])
  141 #define EPIC_CDRX(sc, x)        (&(sc)->sc_control_data->ecd_rxdescs[(x)])
  142 #define EPIC_CDFL(sc, x)        (&(sc)->sc_control_data->ecd_txfrags[(x)])
  143 
  144 #define EPIC_DSTX(sc, x)        (&(sc)->sc_txsoft[(x)])
  145 #define EPIC_DSRX(sc, x)        (&(sc)->sc_rxsoft[(x)])
  146 
  147 #define EPIC_CDTXSYNC(sc, x, ops)                                       \
  148         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
  149             EPIC_CDTXOFF((x)), sizeof(struct epic_txdesc), (ops))
  150 
  151 #define EPIC_CDRXSYNC(sc, x, ops)                                       \
  152         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
  153             EPIC_CDRXOFF((x)), sizeof(struct epic_rxdesc), (ops))
  154 
  155 #define EPIC_CDFLSYNC(sc, x, ops)                                       \
  156         bus_dmamap_sync((sc)->sc_dmat, (sc)->sc_cddmamap,               \
  157             EPIC_CDFLOFF((x)), sizeof(struct epic_fraglist), (ops))
  158 
  159 #define EPIC_INIT_RXDESC(sc, x)                                         \
  160 do {                                                                    \
  161         struct epic_descsoft *__ds = EPIC_DSRX((sc), (x));              \
  162         struct epic_rxdesc *__rxd = EPIC_CDRX((sc), (x));               \
  163         struct mbuf *__m = __ds->ds_mbuf;                               \
  164                                                                         \
  165         /*                                                              \
  166          * Note we scoot the packet forward 2 bytes in the buffer       \
  167          * so that the payload after the Ethernet header is aligned     \
  168          * to a 4 byte boundary.                                        \
  169          */                                                             \
  170         __m->m_data = __m->m_ext.ext_buf + 2;                           \
  171         __rxd->er_bufaddr = __ds->ds_dmamap->dm_segs[0].ds_addr + 2;    \
  172         __rxd->er_control = RXCTL_BUFLENGTH(__m->m_ext.ext_size - 2);   \
  173         __rxd->er_rxstatus = ER_RXSTAT_OWNER;                           \
  174         __rxd->er_nextdesc = EPIC_CDRXADDR((sc), EPIC_NEXTRX((x)));     \
  175         EPIC_CDRXSYNC((sc), (x), BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); \
  176 } while (/* CONSTCOND */ 0)
  177 
  178 #ifdef _KERNEL
  179 void    epic_attach(struct epic_softc *, const char *);
  180 int     epic_intr(void *);
  181 #endif /* _KERNEL */
  182 
  183 #endif /* _DEV_IC_SMC83C170VAR_H_ */

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sys/dev/ic/smc83c170var.h