1 /* $OpenBSD: smc91cxxreg.h,v 1.4 2022/01/09 05:42:42 jsg Exp $ */
2 /* $NetBSD: smc91cxxreg.h,v 1.2 1997/09/02 00:10:58 thorpej Exp $ */
3
4 /*
5 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Gardner Buchanan.
19 * 4. The name of Gardner Buchanan may not be used to endorse or promote
20 * products derived from this software without specific prior written
21 * permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 * from FreeBSD Id: if_snreg.h,v 1.4 1996/03/18 15:47:30 gardner Exp
35 */
36
37 /*
38 * This file contains register information and access macros for
39 * the SMC91xxx chipset.
40 *
41 * Information contained in this file was obtained from the SMC91C92
42 * and SMC91C94 manuals from SMC. You will need one of these in order
43 * to make any meaningful changes to this driver. Information about
44 * obtaining one can be found at http://www.smc.com in the components
45 * division.
46 *
47 * This FreeBSD driver is derived in part from the smc9194 Linux driver
48 * by Erik Stahlman.
49 */
50
51
52 /*
53 * Wait time for memory to be free. This probably shouldn't be
54 * tuned that much, as waiting for this means nothing else happens
55 * in the system
56 */
57 #define MEMORY_WAIT_TIME 1000
58
59
60 /* The SMC91xxx uses 16 I/O ports */
61 #define SMC_IOSIZE 16
62
63
64 /*
65 * A description of the SMC registers is probably in order here,
66 * although for details, the SMC datasheet is invaluable.
67 * The data sheet I (GB) am using is "SMC91C92 Single Chip Ethernet
68 * Controller With RAM", Rev. 12/0/94. Constant definitions I give
69 * here are loosely based on the mnemonic names given to them in the
70 * data sheet, but there are many exceptions.
71 *
72 * Basically, the chip has 4 banks of registers (0 to 3), which
73 * are accessed by writing a number into the BANK_SELECT register
74 * (I also use a SMC_SELECT_BANK macro for this). Registers are
75 * either Byte or Word sized. My constant definitions end in _B
76 * or _W as appropriate.
77 *
78 * The banks are arranged so that for most purposes, bank 2 is all
79 * that is needed for normal run time tasks.
80 */
81
82
83 /*
84 * Bank Select Register. This also doubles as
85 * a chip identification register. This register
86 * is mapped at the same position in all banks.
87 */
88 #define BANK_SELECT_REG_W 0x0e
89 #define BSR_DETECT_MASK 0xff00
90 #define BSR_DETECT_VALUE 0x3300
91
92
93 /*
94 * BANK 0
95 */
96
97 /*
98 * Transmit Control Register controls some aspects of the transmit
99 * behavior of the Ethernet Protocol Handler.
100 */
101 #define TXMIT_CONTROL_REG_W 0x00
102
103 #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */
104 #define TCR_LOOP 0x0002 /* Enable internal analogue loopback */
105 #define TCR_FORCOL 0x0004 /* Force Collision on next TX */
106 #define TCR_PAD_ENABLE 0x0080 /* Pad short packets to 64 bytes */
107 #define TCR_NOCRC 0x0100 /* Do not append CRC */
108 #define TCR_MON_CSN 0x0400 /* monitors the carrier status */
109 #define TCR_FDUPLX 0x0800 /* receive packets sent out */
110 #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */
111 #define TCR_EPH_LOOP 0x2000 /* Enable internal digital loopback */
112 #define TCR_SWFDUP 0x8000 /* FEAST: Switched full-duplex (only w/ MII) */
113
114
115 /*
116 * Status of the last transmitted frame and instantaneous status of
117 * the Ethernet Protocol Handler jumbled together. In auto-release
118 * mode this information is simply discarded after each TX. This info
119 * is copied to the status word of in-memory packets after transmit
120 * where relevant statuses can be checked.
121 */
122 #define EPH_STATUS_REG_W 0x02
123
124 #define EPHSR_TX_SUC 0x0001 /* Transmit was successful */
125 #define EPHSR_SNGLCOL 0x0002 /* Single collision occurred */
126 #define EPHSR_MULCOL 0x0004 /* Multiple Collisions occurred */
127 #define EPHSR_LTX_MULT 0x0008 /* Transmit was a multicast */
128 #define EPHSR_16COL 0x0010 /* 16 Collisions occurred, TX disabled */
129 #define EPHSR_SQET 0x0020 /* SQE Test failed, TX disabled */
130 #define EPHSR_LTX_BRD 0x0040 /* Transmit was a broadcast */
131 #define EPHSR_DEFR 0x0080 /* TX deferred due to carrier det. */
132 #define EPHSR_LATCOL 0x0200 /* Late collision detected, TX disabled */
133 #define EPHSR_LOST_CAR 0x0400 /* Lost carrier sense, TX disabled */
134 #define EPHSR_EXC_DEF 0x0800 /* Excessive deferrals in TX >2 MAXETHER
135 * times */
136 #define EPHSR_CTR_ROL 0x1000 /* Some ECR Counter(s) rolled over */
137 #define EPHSR_RX_OVRN 0x2000 /* Receiver overrun, packets dropped */
138 #define EPHSR_LINK_OK 0x4000 /* Link integrity is OK */
139 #define EPHSR_TXUNRN 0x8000 /* Transmit underrun */
140
141
142 /*
143 * Receiver Control Register controls some aspects of the receive
144 * behavior of the Ethernet Protocol Handler.
145 */
146 #define RECV_CONTROL_REG_W 0x04
147
148 #define RCR_RX_ABORT 0x0001 /* Received huge packet */
149 #define RCR_PROMISC 0x0002 /* enable promiscuous mode */
150 #define RCR_ALMUL 0x0004 /* receive all multicast packets */
151 #define RCR_ENABLE 0x0100 /* IFF this is set, we can receive packets */
152 #define RCR_STRIP_CRC 0x0200 /* strips CRC */
153 #define RCR_GAIN_BITS 0x0c00 /* PLL Gain control (for testing) */
154 #define RCR_FILT_CAR 0x4000 /* Enable 12 bit carrier filter */
155 #define RCR_SOFTRESET 0x8000 /* Resets the EPH logic */
156
157
158 /*
159 * TX Statistics counters
160 */
161 #define COUNTER_REG_W 0x06
162
163 #define ECR_COLN_MASK 0x000f /* Vanilla collisions */
164 #define ECR_MCOLN_MASK 0x00f0 /* Multiple collisions */
165 #define ECR_DTX_MASK 0x0f00 /* Deferred transmits */
166 #define ECR_EXDTX_MASK 0xf000 /* Excessively deferred transmits */
167
168
169 /*
170 * Memory Information
171 */
172 #define MEM_INFO_REG_W 0x08
173
174 #define MIR_FREE_MASK 0xff00 /* Free memory pages available */
175 #define MIR_TOTAL_MASK 0x00ff /* Total memory pages available */
176
177
178 /*
179 * Memory Configuration
180 */
181 #define MEM_CFG_REG_W 0x0a
182
183 #define MCR_MEM_MULT(x) (((x)>>9)&7) /* Memory size multiplier */
184 #define MCR_TXRSV_MASK 0x001f /* Count of pages reserved for transmit */
185
186
187 /*
188 * Bank 0, Register 0x0c is unused in the SMC91C92
189 */
190
191
192 /*
193 * BANK 1
194 */
195
196 /*
197 * Adapter configuration
198 */
199 #define CONFIG_REG_W 0x00
200
201 #define CR_INT_SEL0 0x0002 /* Interrupt selector */
202 #define CR_INT_SEL1 0x0004 /* Interrupt selector */
203 #define CR_DIS_LINK 0x0040 /* Disable 10BaseT Link Test */
204 #define CR_16BIT 0x0080 /* Bus width */
205 #define CR_AUI_SELECT 0x0100 /* Use external (AUI) Transceiver */
206 #define CR_SET_SQLCH 0x0200 /* Squelch level */
207 #define CR_FULL_STEP 0x0400 /* AUI signalling mode */
208 #define CR_NOW_WAIT_ST 0x1000 /* Disable bus wait states */
209 #define CR_MII_SELECT 0x8000 /* FEAST: MII port selected */
210
211
212 /*
213 * The contents of this port are used by the adapter
214 * to decode its I/O address. We use it as a verification
215 * that the adapter is detected properly when probing.
216 */
217 #define BASE_ADDR_REG_W 0x02 /* The selected I/O Base addr. */
218
219
220 /*
221 * These registers hold the Ethernet MAC address.
222 */
223 #define IAR_ADDR0_REG_W 0x04 /* My Ethernet address */
224 #define IAR_ADDR1_REG_W 0x06 /* My Ethernet address */
225 #define IAR_ADDR2_REG_W 0x08 /* My Ethernet address */
226
227
228 /*
229 * General purpose register used for talking to the EEPROM.
230 */
231 #define GENERAL_REG_W 0x0a
232
233
234 /*
235 * Control register used for talking to the EEPROM and
236 * setting some EPH functions.
237 */
238 #define CONTROL_REG_W 0x0c
239
240 #define CTR_STORE 0x0001 /* Store something to EEPROM */
241 #define CTR_RELOAD 0x0002 /* Read EEPROM into registers */
242 #define CTR_EEPROM_SEL 0x0004 /* Select registers for Reload/Store */
243 #define CTR_TE_ENABLE 0x0020 /* Enable TX Error detection via EPH_INT */
244 #define CTR_CR_ENABLE 0x0040 /* Enable Counter Rollover via EPH_INT */
245 #define CTR_LE_ENABLE 0x0080 /* Enable Link Error detection via EPH_INT */
246 #define CTR_AUTO_RELEASE 0x0800 /* Enable auto release mode for TX */
247 #define CTR_POWERDOWN 0x2000 /* Enter powerdown mode */
248 #define CTR_RCV_BAD 0x4000 /* Enable receipt of frames with bad CRC */
249
250
251 /*
252 * BANK 2
253 */
254
255
256 /*
257 * Memory Management Unit Control Register
258 * Controls allocation of memory to receive and
259 * transmit functions.
260 */
261 #define MMU_CMD_REG_W 0x00
262
263 #define MMUCR_BUSY 0x0001 /* MMU busy performing a release */
264
265 /*
266 * MMU Commands:
267 */
268 #define MMUCR_NOP 0x0000 /* Do nothing */
269 #define MMUCR_ALLOC 0x0020 /* Or with number of 256 byte packets - 1 */
270 #define MMUCR_RESET 0x0040 /* Reset MMU State */
271 #define MMUCR_REMOVE 0x0060 /* Dequeue (but not free) current RX packet */
272 #define MMUCR_RELEASE 0x0080 /* Dequeue and free the current RX packet */
273 #define MMUCR_FREEPKT 0x00a0 /* Release packet in PNR register */
274 #define MMUCR_ENQUEUE 0x00c0 /* Enqueue the packet for transmit */
275 #define MMUCR_RESETTX 0x00e0 /* Reset transmit queues */
276
277 /*
278 * Packet Number at TX Area
279 */
280 #define PACKET_NUM_REG_B 0x02
281
282 /*
283 * Packet number resulting from MMUCR_ALLOC
284 */
285 #define ALLOC_RESULT_REG_B 0x03
286 #define ARR_FAILED 0x80
287
288 /*
289 * Transmit and receive queue heads
290 */
291 #define FIFO_PORTS_REG_W 0x04
292 #define FIFO_REMPTY 0x8000
293 #define FIFO_TEMPTY 0x0080
294 #define FIFO_RX_MASK 0x7f00
295 #define FIFO_TX_MASK 0x007f
296
297
298 /*
299 * The address within the packet for reading/writing. The
300 * PTR_RCV bit is tricky. When PTR_RCV==1, the packet number
301 * to be read is found in the FIFO_PORTS_REG_W, FIFO_RX_MASK.
302 * When PTR_RCV==0, the packet number to be written is found
303 * in the PACKET_NUM_REG_B.
304 */
305 #define POINTER_REG_W 0x06
306
307 #define PTR_READ 0x2000 /* Intended access mode */
308 #define PTR_AUTOINC 0x4000 /* Do auto inc after read/write */
309 #define PTR_RCV 0x8000 /* FIFO_RX is packet, otherwise PNR is packet */
310
311 /*
312 * Data I/O register to be used in conjunction with
313 * The pointer register to read and write data from the
314 * card. The same register can be used for byte and word
315 * ops.
316 */
317 #define DATA_REG_W 0x08
318 #define DATA_REG_B 0x08
319 #define DATA_1_REG_B 0x08
320 #define DATA_2_REG_B 0x0a
321
322
323 /*
324 * Sense interrupt status (READ)
325 */
326 #define INTR_STAT_REG_B 0x0c
327
328
329 /*
330 * Acknowledge interrupt sources (WRITE)
331 */
332 #define INTR_ACK_REG_B 0x0c
333
334
335 /*
336 * Interrupt mask. Bit set indicates interrupt allowed.
337 */
338 #define INTR_MASK_REG_B 0x0d
339
340 /*
341 * Interrupts
342 */
343 #define IM_RCV_INT 0x01 /* A packet has been received */
344 #define IM_TX_INT 0x02 /* Packet TX complete */
345 #define IM_TX_EMPTY_INT 0x04 /* No packets left to TX */
346 #define IM_ALLOC_INT 0x08 /* Memory allocation completed */
347 #define IM_RX_OVRN_INT 0x10 /* Receiver was overrun */
348 #define IM_EPH_INT 0x20 /* Misc. EPH conditions (see CONTROL_REG_W) */
349 #define IM_ERCV_INT 0x40 /* not on SMC9192 */
350
351
352 /*
353 * BANK 3
354 */
355
356
357 /*
358 * Multicast subscriptions.
359 * The multicast handling in the SMC90Cxx is quite complicated. A table
360 * of multicast address subscriptions is provided and a clever way of
361 * speeding the search of that table by hashing is implemented in the
362 * hardware. I have ignored this and simply subscribed to all multicasts
363 * and let the kernel deal with the results.
364 */
365 #define MULTICAST1_REG_W 0x00
366 #define MULTICAST2_REG_W 0x02
367 #define MULTICAST3_REG_W 0x04
368 #define MULTICAST4_REG_W 0x06
369
370 /*
371 * These registers do not exist on SMC9192, or at least
372 * are not documented in the SMC91C92 data sheet.
373 *
374 * The REVISION_REG_W register does however seem to work.
375 *
376 * On the FEAST, the low nibble controls the MII interface.
377 */
378 #define MGMT_REG_W 0x08
379
380 #define MR_MDOE 0x08
381 #define MR_MCLK 0x04
382 #define MR_MDI 0x02
383 #define MR_MDO 0x01
384
385 #define REVISION_REG_W 0x0a /* (hi: chip id low: rev #) */
386 #define RR_REV(x) ((x) & 0x0f)
387 #define RR_ID(x) (((x) >> 4) & 0x0f)
388
389 #define ERCV_REG_W 0x0c
390
391 /*
392 * These are constants expected to be found in the
393 * chip id register.
394 */
395 #define CHIP_9190 3
396 #define CHIP_9194 4
397 #define CHIP_9195 5
398 #define CHIP_91100 7
399 #define CHIP_91100FD 8
400
401
402 /*
403 * When packets are stuffed into the card or sucked out of the card
404 * they are set up more or less as follows:
405 *
406 * Addr msbyte lsbyte
407 * 00 SSSSSSSS SSSSSSSS - STATUS-WORD 16 bit TX or RX status
408 * 02 RRRRR - RESERVED (unused)
409 * 02 CCC CCCCCCCC - BYTE COUNT (RX: always even, TX: bit 0 ignored)
410 * 04 DDDDDDDD DDDDDDDD - DESTINATION ADDRESS
411 * 06 DDDDDDDD DDDDDDDD (48 bit Ethernet MAC Address)
412 * 08 DDDDDDDD DDDDDDDD
413 * 0A SSSSSSSS SSSSSSSS - SOURCE ADDRESS
414 * 0C SSSSSSSS SSSSSSSS (48 bit Ethernet MAC Address)
415 * 0E SSSSSSSS SSSSSSSS
416 * 10 PPPPPPPP PPPPPPPP
417 * .. PPPPPPPP PPPPPPPP
418 * C-2 CCCCCCCC - CONTROL BYTE
419 * C-2 PPPPPPPP - Last data byte (If odd length)
420 *
421 * The STATUS_WORD is derived from the EPH_STATUS_REG_W register
422 * during transmit and is composed of another set of bits described
423 * below during receive.
424 */
425
426
427 /*
428 * Receive status bits. These values are found in the status word
429 * field of a received packet. For receive packets I use the RS_ODDFRAME
430 * to detect whether a frame has an extra byte on it. The CTLB_ODD
431 * bit of the control byte tells the same thing.
432 */
433 #define RS_MULTICAST 0x0001 /* Packet is multicast */
434 #define RS_HASH_MASK 0x007e /* Mask of multicast hash value */
435 #define RS_TOOSHORT 0x0400 /* Frame was a runt, <64 bytes */
436 #define RS_TOOLONG 0x0800 /* Frame was giant, >1518 */
437 #define RS_ODDFRAME 0x1000 /* Frame is odd lengthed */
438 #define RS_BADCRC 0x2000 /* Frame had CRC error */
439 #define RS_ALGNERR 0x8000 /* Frame had alignment error */
440 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
441
442 #define RLEN_MASK 0x07ff /* Significant length bits in RX length */
443
444 /*
445 * The control byte has the following significant bits.
446 * For transmit, the CTLB_ODD bit specifies whether an extra byte
447 * is present in the frame. Bit 0 of the byte count field is
448 * ignored. I just pad every frame to even length and forget about
449 * it.
450 */
451 #define CTLB_CRC 0x10 /* Add CRC for this packet (TX only) */
452 #define CTLB_ODD 0x20 /* The packet length is ODD */
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