Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/tcic2.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* $NetBSD: tcic2.c,v 1.30.14.1 2009/07/26 18:33:35 snj Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 Christoph Badura. All rights reserved. 5 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Marc Horowitz. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: tcic2.c,v 1.30.14.1 2009/07/26 18:33:35 snj Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/extent.h> 40 #include <sys/malloc.h> 41 #include <sys/kthread.h> 42 43 #include <sys/bus.h> 44 #include <sys/intr.h> 45 46 #include <dev/pcmcia/pcmciareg.h> 47 #include <dev/pcmcia/pcmciavar.h> 48 49 #include <dev/ic/tcic2reg.h> 50 #include <dev/ic/tcic2var.h> 51 52 #include "locators.h" 53 54 #ifdef TCICDEBUG 55 int tcic_debug = 1; 56 #define DPRINTF(arg) if (tcic_debug) printf arg; 57 #else 58 #define DPRINTF(arg) 59 #endif 60 61 /* 62 * Individual drivers will allocate their own memory and io regions. Memory 63 * regions must be a multiple of 4k, aligned on a 4k boundary. 64 */ 65 66 #define TCIC_MEM_ALIGN TCIC_MEM_PAGESIZE 67 68 void tcic_attach_socket(struct tcic_handle *); 69 void tcic_init_socket(struct tcic_handle *); 70 71 int tcic_print(void *arg, const char *pnp); 72 int tcic_intr_socket(struct tcic_handle *); 73 74 void tcic_attach_card(struct tcic_handle *); 75 void tcic_detach_card(struct tcic_handle *, int); 76 void tcic_deactivate_card(struct tcic_handle *); 77 78 void tcic_chip_do_mem_map(struct tcic_handle *, int); 79 void tcic_chip_do_io_map(struct tcic_handle *, int); 80 81 void tcic_create_event_thread(void *); 82 void tcic_event_thread(void *); 83 84 void tcic_queue_event(struct tcic_handle *, int); 85 86 /* Map between irq numbers and internal representation */ 87 #if 1 88 int tcic_irqmap[] = 89 { 0, 0, 0, 3, 4, 5, 6, 7, 0, 0, 10, 1, 0, 0, 14, 0 }; 90 int tcic_valid_irqs = 0x4cf8; 91 #else 92 int tcic_irqmap[] = /* irqs 9 and 6 switched, some ISA cards */ 93 { 0, 0, 0, 3, 4, 5, 0, 7, 0, 6, 10, 1, 0, 0, 14, 0 }; 94 int tcic_valid_irqs = 0x4eb8; 95 #endif 96 97 int tcic_mem_speed = 250; /* memory access time in nanoseconds */ 98 int tcic_io_speed = 165; /* io access time in nanoseconds */ 99 100 /* 101 * Check various reserved and otherwise in their value restricted bits. 102 */ 103 int 104 tcic_check_reserved_bits(iot, ioh) 105 bus_space_tag_t iot; 106 bus_space_handle_t ioh; 107 { 108 int val, auxreg; 109 110 DPRINTF(("tcic: chkrsvd 1\n")); 111 /* R_ADDR bit 30:28 have a restricted range. */ 112 val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK) 113 >> TCIC_SS_SHIFT; 114 if (val > 1) 115 return 0; 116 117 DPRINTF(("tcic: chkrsvd 2\n")); 118 /* R_SCTRL bits 6,2,1 are reserved. */ 119 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 120 if (val & TCIC_SCTRL_RSVD) 121 return 0; 122 123 DPRINTF(("tcic: chkrsvd 3\n")); 124 /* R_ICSR bit 2 must be same as bit 3. */ 125 val = bus_space_read_1(iot, ioh, TCIC_R_ICSR); 126 if (((val >> 1) & 1) != ((val >> 2) & 1)) 127 return 0; 128 129 DPRINTF(("tcic: chkrsvd 4\n")); 130 /* R_IENA bits 7,2 are reserverd. */ 131 val = bus_space_read_1(iot, ioh, TCIC_R_IENA); 132 if (val & TCIC_IENA_RSVD) 133 return 0; 134 135 DPRINTF(("tcic: chkrsvd 5\n")); 136 /* Some aux registers have reserved bits. */ 137 /* Which are we looking at? */ 138 auxreg = bus_space_read_1(iot, ioh, TCIC_R_MODE) 139 & TCIC_AR_MASK; 140 val = bus_space_read_2(iot, ioh, TCIC_R_AUX); 141 DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val)); 142 switch (auxreg) { 143 case TCIC_AR_SYSCFG: 144 if (INVALID_AR_SYSCFG(val)) 145 return 0; 146 break; 147 case TCIC_AR_ILOCK: 148 if (INVALID_AR_ILOCK(val)) 149 return 0; 150 break; 151 case TCIC_AR_TEST: 152 if (INVALID_AR_TEST(val)) 153 return 0; 154 break; 155 } 156 157 DPRINTF(("tcic: chkrsvd 6\n")); 158 /* XXX fails if pcmcia bios is enabled. */ 159 /* Various bits set or not depending if in RESET mode. */ 160 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 161 if (val & TCIC_SCTRL_RESET) { 162 DPRINTF(("tcic: chkrsvd 7\n")); 163 /* Address bits must be 0 */ 164 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR); 165 if (val != 0) 166 return 0; 167 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2); 168 if (val != 0) 169 return 0; 170 DPRINTF(("tcic: chkrsvd 8\n")); 171 /* EDC bits must be 0 */ 172 val = bus_space_read_2(iot, ioh, TCIC_R_EDC); 173 if (val != 0) 174 return 0; 175 /* We're OK, so take it out of reset. XXX -chb */ 176 bus_space_write_1(iot, ioh, TCIC_R_SCTRL, 0); 177 } 178 else { /* not in RESET mode */ 179 int omode; 180 int val1, val2; 181 DPRINTF(("tcic: chkrsvd 9\n")); 182 /* Programming timers must have expired. */ 183 val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT); 184 if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 185 != (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 186 return 0; 187 DPRINTF(("tcic: chkrsvd 10\n")); 188 /* 189 * EDC bits should change on read from data space 190 * as long as either EDC or the data are nonzero. 191 */ 192 if ((bus_space_read_2(iot, ioh, TCIC_R_ADDR2) 193 & TCIC_ADDR2_INDREG) != 0) { 194 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 195 val2 = bus_space_read_2(iot, ioh, TCIC_R_DATA); 196 if (val1 | val2) { 197 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 198 if (val1 == val2) 199 return 0; 200 } 201 } 202 DPRINTF(("tcic: chkrsvd 11\n")); 203 /* XXX what does this check? -chb */ 204 omode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 205 val1 = omode ^ TCIC_AR_MASK; 206 bus_space_write_1(iot, ioh, TCIC_R_MODE, val1); 207 val2 = bus_space_read_1(iot, ioh, TCIC_R_MODE); 208 bus_space_write_1(iot, ioh, TCIC_R_MODE, omode); 209 if ( val1 != val2) 210 return 0; 211 } 212 /* All tests passed */ 213 return 1; 214 } 215 216 /* 217 * Read chip ID from AR_ILOCK in test mode. 218 */ 219 int 220 tcic_chipid(iot, ioh) 221 bus_space_tag_t iot; 222 bus_space_handle_t ioh; 223 { 224 unsigned id, otest; 225 226 otest = tcic_read_aux_2(iot, ioh, TCIC_AR_TEST); 227 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, TCIC_TEST_DIAG); 228 id = tcic_read_aux_2(iot, ioh, TCIC_AR_ILOCK); 229 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, otest); 230 id &= TCIC_ILOCKTEST_ID_MASK; 231 id >>= TCIC_ILOCKTEST_ID_SHFT; 232 233 /* clear up IRQs inside tcic. XXX -chb */ 234 while (bus_space_read_1(iot, ioh, TCIC_R_ICSR)) 235 bus_space_write_1(iot, ioh, TCIC_R_ICSR, TCIC_ICSR_JAM); 236 237 return id; 238 } 239 /* 240 * Indicate whether the driver can handle the chip. 241 */ 242 int 243 tcic_chipid_known(id) 244 int id; 245 { 246 /* XXX only know how to handle DB86082 -chb */ 247 switch (id) { 248 case TCIC_CHIPID_DB86082_1: 249 case TCIC_CHIPID_DB86082A: 250 case TCIC_CHIPID_DB86082B_ES: 251 case TCIC_CHIPID_DB86082B: 252 case TCIC_CHIPID_DB86084_1: 253 case TCIC_CHIPID_DB86084A: 254 case TCIC_CHIPID_DB86184_1: 255 case TCIC_CHIPID_DB86072_1_ES: 256 case TCIC_CHIPID_DB86072_1: 257 return 1; 258 } 259 260 return 0; 261 } 262 263 const char * 264 tcic_chipid_to_string(id) 265 int id; 266 { 267 switch (id) { 268 case TCIC_CHIPID_DB86082_1: 269 return ("Databook DB86082"); 270 case TCIC_CHIPID_DB86082A: 271 return ("Databook DB86082A"); 272 case TCIC_CHIPID_DB86082B_ES: 273 return ("Databook DB86082B-es"); 274 case TCIC_CHIPID_DB86082B: 275 return ("Databook DB86082B"); 276 case TCIC_CHIPID_DB86084_1: 277 return ("Databook DB86084"); 278 case TCIC_CHIPID_DB86084A: 279 return ("Databook DB86084A"); 280 case TCIC_CHIPID_DB86184_1: 281 return ("Databook DB86184"); 282 case TCIC_CHIPID_DB86072_1_ES: 283 return ("Databook DB86072-es"); 284 case TCIC_CHIPID_DB86072_1: 285 return ("Databook DB86072"); 286 } 287 288 return ("Unknown controller"); 289 } 290 /* 291 * Return bitmask of IRQs that the chip can handle. 292 * XXX should be table driven. 293 */ 294 int 295 tcic_validirqs(chipid) 296 int chipid; 297 { 298 switch (chipid) { 299 case TCIC_CHIPID_DB86082_1: 300 case TCIC_CHIPID_DB86082A: 301 case TCIC_CHIPID_DB86082B_ES: 302 case TCIC_CHIPID_DB86082B: 303 case TCIC_CHIPID_DB86084_1: 304 case TCIC_CHIPID_DB86084A: 305 case TCIC_CHIPID_DB86184_1: 306 case TCIC_CHIPID_DB86072_1_ES: 307 case TCIC_CHIPID_DB86072_1: 308 return tcic_valid_irqs; 309 } 310 return 0; 311 } 312 313 void 314 tcic_attach(sc) 315 struct tcic_softc *sc; 316 { 317 int i, reg; 318 319 /* set more chipset dependent parameters in the softc. */ 320 switch (sc->chipid) { 321 case TCIC_CHIPID_DB86084_1: 322 case TCIC_CHIPID_DB86084A: 323 case TCIC_CHIPID_DB86184_1: 324 sc->pwrena = TCIC_PWR_ENA; 325 break; 326 default: 327 sc->pwrena = 0; 328 break; 329 } 330 331 /* set up global config registers */ 332 reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING; 333 reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK); 334 tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg); 335 reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL; 336 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 337 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK); 338 reg |= TCIC_ILOCK_HOLD_CCLK; 339 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg); 340 341 /* the TCIC has two sockets */ 342 /* XXX should i check for actual presence of sockets? -chb */ 343 for (i = 0; i < TCIC_NSLOTS; i++) { 344 sc->handle[i].sc = sc; 345 sc->handle[i].sock = i; 346 sc->handle[i].flags = TCIC_FLAG_SOCKETP; 347 sc->handle[i].memwins 348 = sc->chipid == TCIC_CHIPID_DB86082_1 ? 4 : 5; 349 } 350 351 /* establish the interrupt */ 352 reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA); 353 tcic_write_1(&sc->handle[0], TCIC_R_IENA, 354 (reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH); 355 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 356 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, 357 (reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]); 358 359 /* XXX block interrupts? */ 360 361 for (i = 0; i < TCIC_NSLOTS; i++) { 362 /* XXX make more clear what happens here -chb */ 363 tcic_sel_sock(&sc->handle[i]); 364 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF1_N(i), 0); 365 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF2_N(i), 366 (TCIC_SCF2_MCD|TCIC_SCF2_MWP|TCIC_SCF2_MRDY 367 #if 1 /* XXX explain byte routing issue */ 368 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1|TCIC_SCF2_IDBR)); 369 #else 370 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1)); 371 #endif 372 tcic_write_1(&sc->handle[i], TCIC_R_MODE, 0); 373 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 374 reg &= ~TCIC_SYSCFG_AUTOBUSY; 375 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 376 SIMPLEQ_INIT(&sc->handle[i].events); 377 } 378 379 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) || 380 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) { 381 printf("%s: %s has ", device_xname(&sc->dev), 382 tcic_chipid_to_string(sc->chipid)); 383 384 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) && 385 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) 386 printf("sockets A and B\n"); 387 else if (sc->handle[0].flags & TCIC_FLAG_SOCKETP) 388 printf("socket A only\n"); 389 else 390 printf("socket B only\n"); 391 392 } 393 } 394 395 void 396 tcic_attach_sockets(sc) 397 struct tcic_softc *sc; 398 { 399 int i; 400 401 for (i = 0; i < TCIC_NSLOTS; i++) 402 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 403 tcic_attach_socket(&sc->handle[i]); 404 } 405 406 void 407 tcic_attach_socket(h) 408 struct tcic_handle *h; 409 { 410 struct pcmciabus_attach_args paa; 411 int locs[PCMCIABUSCF_NLOCS]; 412 413 /* initialize the rest of the handle */ 414 415 h->shutdown = 0; 416 h->memalloc = 0; 417 h->ioalloc = 0; 418 h->ih_irq = 0; 419 420 /* now, config one pcmcia device per socket */ 421 422 paa.paa_busname = "pcmcia"; 423 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 424 paa.pch = (pcmcia_chipset_handle_t) h; 425 paa.iobase = h->sc->iobase; 426 paa.iosize = h->sc->iosize; 427 428 locs[PCMCIABUSCF_CONTROLLER] = 0; 429 locs[PCMCIABUSCF_SOCKET] = h->sock; 430 431 h->pcmcia = config_found_sm_loc(&h->sc->dev, "pcmciabus", locs, &paa, 432 tcic_print, config_stdsubmatch); 433 434 /* if there's actually a pcmcia device attached, initialize the slot */ 435 436 if (h->pcmcia) 437 tcic_init_socket(h); 438 } 439 440 void 441 tcic_create_event_thread(arg) 442 void *arg; 443 { 444 struct tcic_handle *h = arg; 445 const char *cs; 446 447 switch (h->sock) { 448 case 0: 449 cs = ""; 450 break; 451 case 1: 452 cs = "1"; 453 break; 454 default: 455 panic("tcic_create_event_thread: unknown tcic socket"); 456 } 457 458 if (kthread_create(PRI_NONE, 0, NULL, tcic_event_thread, h, 459 &h->event_thread, "%s,%s", device_xname(&h->sc->dev), cs)) { 460 aprint_error_dev(&h->sc->dev, "unable to create event thread for sock 0x%02x\n", h->sock); 461 panic("tcic_create_event_thread"); 462 } 463 } 464 465 void 466 tcic_event_thread(arg) 467 void *arg; 468 { 469 struct tcic_handle *h = arg; 470 struct tcic_event *pe; 471 int s; 472 473 while (h->shutdown == 0) { 474 s = splhigh(); 475 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 476 splx(s); 477 (void) tsleep(&h->events, PWAIT, "tcicev", 0); 478 continue; 479 } 480 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 481 splx(s); 482 483 switch (pe->pe_type) { 484 case TCIC_EVENT_INSERTION: 485 DPRINTF(("%s: insertion event\n", device_xname(&h->sc->dev))); 486 tcic_attach_card(h); 487 break; 488 489 case TCIC_EVENT_REMOVAL: 490 DPRINTF(("%s: removal event\n", device_xname(&h->sc->dev))); 491 tcic_detach_card(h, DETACH_FORCE); 492 break; 493 494 default: 495 panic("tcic_event_thread: unknown event %d", 496 pe->pe_type); 497 } 498 free(pe, M_TEMP); 499 } 500 501 h->event_thread = NULL; 502 503 /* In case parent is waiting for us to exit. */ 504 wakeup(h->sc); 505 506 kthread_exit(0); 507 } 508 509 510 void 511 tcic_init_socket(h) 512 struct tcic_handle *h; 513 { 514 int reg; 515 516 /* select this socket's config registers */ 517 tcic_sel_sock(h); 518 519 /* set up the socket to interrupt on card detect */ 520 reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock)); 521 tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD); 522 523 /* enable CD irq in R_IENA */ 524 reg = tcic_read_2(h, TCIC_R_IENA); 525 tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG); 526 527 /* if there's a card there, then attach it. also save sstat */ 528 h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK; 529 if (reg & TCIC_SSTAT_CD) 530 tcic_attach_card(h); 531 } 532 533 int 534 tcic_print(arg, pnp) 535 void *arg; 536 const char *pnp; 537 { 538 struct pcmciabus_attach_args *paa = arg; 539 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 540 541 /* Only "pcmcia"s can attach to "tcic"s... easy. */ 542 if (pnp) 543 aprint_normal("pcmcia at %s", pnp); 544 545 aprint_normal(" socket %d", h->sock); 546 547 return (UNCONF); 548 } 549 550 int 551 tcic_intr(arg) 552 void *arg; 553 { 554 struct tcic_softc *sc = arg; 555 int i, ret = 0; 556 557 DPRINTF(("%s: intr\n", device_xname(&sc->dev))); 558 559 for (i = 0; i < TCIC_NSLOTS; i++) 560 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 561 ret += tcic_intr_socket(&sc->handle[i]); 562 563 return (ret ? 1 : 0); 564 } 565 566 int 567 tcic_intr_socket(h) 568 struct tcic_handle *h; 569 { 570 int icsr, rv; 571 572 rv = 0; 573 tcic_sel_sock(h); 574 icsr = tcic_read_1(h, TCIC_R_ICSR); 575 576 DPRINTF(("%s: %d icsr: 0x%02x \n", device_xname(&h->sc->dev), h->sock, icsr)); 577 578 /* XXX or should the next three be handled in tcic_intr? -chb */ 579 if (icsr & TCIC_ICSR_PROGTIME) { 580 DPRINTF(("%s: %02x PROGTIME\n", device_xname(&h->sc->dev), h->sock)); 581 rv = 1; 582 } 583 if (icsr & TCIC_ICSR_ILOCK) { 584 DPRINTF(("%s: %02x ILOCK\n", device_xname(&h->sc->dev), h->sock)); 585 rv = 1; 586 } 587 if (icsr & TCIC_ICSR_ERR) { 588 DPRINTF(("%s: %02x ERR\n", device_xname(&h->sc->dev), h->sock)); 589 rv = 1; 590 } 591 if (icsr & TCIC_ICSR_CDCHG) { 592 int sstat, delta; 593 594 /* compute what changed since last interrupt */ 595 sstat = tcic_read_aux_1(h->sc->iot, h->sc->ioh, 596 TCIC_AR_WCTL, TCIC_R_WCTL_XCSR) & TCIC_XCSR_STAT_MASK; 597 delta = h->sstat ^ sstat; 598 h->sstat = sstat; 599 600 if (delta) 601 rv = 1; 602 603 DPRINTF(("%s: %02x CDCHG %x\n", device_xname(&h->sc->dev), h->sock, 604 delta)); 605 606 /* 607 * XXX This should probably schedule something to happen 608 * after the interrupt handler completes 609 */ 610 611 if (delta & TCIC_SSTAT_CD) { 612 if (sstat & TCIC_SSTAT_CD) { 613 if (!(h->flags & TCIC_FLAG_CARDP)) { 614 DPRINTF(("%s: enqueing INSERTION event\n", 615 device_xname(&h->sc->dev))); 616 tcic_queue_event(h, TCIC_EVENT_INSERTION); 617 } 618 } else { 619 if (h->flags & TCIC_FLAG_CARDP) { 620 /* Deactivate the card now. */ 621 DPRINTF(("%s: deactivating card\n", 622 device_xname(&h->sc->dev))); 623 tcic_deactivate_card(h); 624 625 DPRINTF(("%s: enqueing REMOVAL event\n", 626 device_xname(&h->sc->dev))); 627 tcic_queue_event(h, TCIC_EVENT_REMOVAL); 628 } 629 } 630 } 631 if (delta & TCIC_SSTAT_RDY) { 632 DPRINTF(("%s: %02x READY\n", device_xname(&h->sc->dev), h->sock)); 633 /* shouldn't happen */ 634 } 635 if (delta & TCIC_SSTAT_LBAT1) { 636 DPRINTF(("%s: %02x LBAT1\n", device_xname(&h->sc->dev), h->sock)); 637 } 638 if (delta & TCIC_SSTAT_LBAT2) { 639 DPRINTF(("%s: %02x LBAT2\n", device_xname(&h->sc->dev), h->sock)); 640 } 641 if (delta & TCIC_SSTAT_WP) { 642 DPRINTF(("%s: %02x WP\n", device_xname(&h->sc->dev), h->sock)); 643 } 644 } 645 return rv; 646 } 647 648 void 649 tcic_queue_event(h, event) 650 struct tcic_handle *h; 651 int event; 652 { 653 struct tcic_event *pe; 654 int s; 655 656 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 657 if (pe == NULL) 658 panic("tcic_queue_event: can't allocate event"); 659 660 pe->pe_type = event; 661 s = splhigh(); 662 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 663 splx(s); 664 wakeup(&h->events); 665 } 666 void 667 tcic_attach_card(h) 668 struct tcic_handle *h; 669 { 670 DPRINTF(("tcic_attach_card\n")); 671 672 if (h->flags & TCIC_FLAG_CARDP) 673 panic("tcic_attach_card: already attached"); 674 675 /* call the MI attach function */ 676 677 pcmcia_card_attach(h->pcmcia); 678 679 h->flags |= TCIC_FLAG_CARDP; 680 } 681 682 void 683 tcic_detach_card(h, flags) 684 struct tcic_handle *h; 685 int flags; /* DETACH_* */ 686 { 687 DPRINTF(("tcic_detach_card\n")); 688 689 if (!(h->flags & TCIC_FLAG_CARDP)) 690 panic("tcic_detach_card: already detached"); 691 692 h->flags &= ~TCIC_FLAG_CARDP; 693 694 /* call the MI detach function */ 695 696 pcmcia_card_detach(h->pcmcia, flags); 697 698 } 699 700 void 701 tcic_deactivate_card(h) 702 struct tcic_handle *h; 703 { 704 int val, reg; 705 706 if (!(h->flags & TCIC_FLAG_CARDP)) 707 panic("tcic_deactivate_card: already detached"); 708 709 /* call the MI deactivate function */ 710 pcmcia_card_deactivate(h->pcmcia); 711 712 tcic_sel_sock(h); 713 714 /* XXX disable card detect resume and configuration reset??? */ 715 716 /* power down the socket */ 717 tcic_write_1(h, TCIC_R_PWR, 0); 718 719 /* reset the card XXX ? -chb */ 720 721 /* turn off irq's for this socket */ 722 reg = TCIC_IR_SCF1_N(h->sock); 723 val = tcic_read_ind_2(h, reg); 724 tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF); 725 reg = TCIC_IR_SCF2_N(h->sock); 726 val = tcic_read_ind_2(h, reg); 727 tcic_write_ind_2(h, reg, 728 (val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY 729 |TCIC_SCF2_MWP|TCIC_SCF2_MCD))); 730 } 731 732 /* XXX the following routine may need to be rewritten. -chb */ 733 int 734 tcic_chip_mem_alloc(pch, size, pcmhp) 735 pcmcia_chipset_handle_t pch; 736 bus_size_t size; 737 struct pcmcia_mem_handle *pcmhp; 738 { 739 struct tcic_handle *h = (struct tcic_handle *) pch; 740 bus_space_handle_t memh; 741 bus_addr_t addr; 742 bus_size_t sizepg; 743 int i, mask, mhandle, got = 0; 744 745 /* out of sc->memh, allocate as many pages as necessary */ 746 747 /* 748 * The TCIC can map memory only in sizes that are 749 * powers of two, aligned at the natural boundary for the size. 750 */ 751 i = tcic_log2((u_int)size); 752 if ((1<<i) < size) 753 i++; 754 sizepg = max(i, TCIC_MEM_SHIFT) - (TCIC_MEM_SHIFT-1); 755 756 DPRINTF(("tcic_chip_mem_alloc: size %ld sizepg %ld\n", (u_long)size, 757 (u_long)sizepg)); 758 759 /* can't allocate that much anyway */ 760 if (sizepg > TCIC_MEM_PAGES) /* XXX -chb */ 761 return 1; 762 763 mask = (1 << sizepg) - 1; 764 765 addr = 0; /* XXX gcc -Wuninitialized */ 766 mhandle = 0; /* XXX gcc -Wuninitialized */ 767 768 /* XXX i should be initialised to always lay on boundary. -chb */ 769 for (i = 0; i < (TCIC_MEM_PAGES + 1 - sizepg); i += sizepg) { 770 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 771 if (bus_space_subregion(h->sc->memt, h->sc->memh, 772 i * TCIC_MEM_PAGESIZE, 773 sizepg * TCIC_MEM_PAGESIZE, &memh)) 774 return (1); 775 mhandle = mask << i; 776 addr = h->sc->membase + (i * TCIC_MEM_PAGESIZE); 777 h->sc->subregionmask &= ~(mhandle); 778 got = 1; 779 break; 780 } 781 } 782 783 if (got == 0) 784 return (1); 785 786 DPRINTF(("tcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 787 (u_long) size)); 788 789 pcmhp->memt = h->sc->memt; 790 pcmhp->memh = memh; 791 pcmhp->addr = addr; 792 pcmhp->size = size; 793 pcmhp->mhandle = mhandle; 794 pcmhp->realsize = sizepg * TCIC_MEM_PAGESIZE; 795 796 return (0); 797 } 798 799 /* XXX the following routine may need to be rewritten. -chb */ 800 void 801 tcic_chip_mem_free(pch, pcmhp) 802 pcmcia_chipset_handle_t pch; 803 struct pcmcia_mem_handle *pcmhp; 804 { 805 struct tcic_handle *h = (struct tcic_handle *) pch; 806 807 h->sc->subregionmask |= pcmhp->mhandle; 808 } 809 810 void 811 tcic_chip_do_mem_map(h, win) 812 struct tcic_handle *h; 813 int win; 814 { 815 int reg, hwwin, wscnt; 816 817 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 818 int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 819 DPRINTF(("tcic_chip_do_mem_map window %d: 0x%lx+0x%lx 0x%lx\n", 820 win, (u_long)h->mem[win].addr, (u_long)h->mem[win].size, 821 (u_long)h->mem[win].offset)); 822 /* 823 * the even windows are used for socket 0, 824 * the odd ones for socket 1. 825 */ 826 hwwin = (win << 1) + h->sock; 827 828 /* the WR_MEXT register is MBZ */ 829 tcic_write_ind_2(h, TCIC_WR_MEXT_N(hwwin), 0); 830 831 /* set the host base address and window size */ 832 if (h->mem[win].size2 <= 1) { 833 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 834 TCIC_MBASE_ADDR_MASK) | TCIC_MBASE_4K; 835 } else { 836 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 837 TCIC_MBASE_ADDR_MASK) | (h->mem[win].size2 >> 1); 838 } 839 tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg); 840 841 /* set the card address and address space */ 842 reg = 0; 843 reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK); 844 reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0; 845 DPRINTF(("tcic_chip_do_map_mem window %d(%d) mmap 0x%04x\n", 846 win, hwwin, reg)); 847 tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg); 848 849 /* set the MCTL register */ 850 /* must save WSCNT field in case this is a DB86082 rev 0 */ 851 /* XXX why can't I do the following two in one statement? */ 852 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK; 853 reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET; 854 reg |= mem8 ? TCIC_MCTL_B8 : 0; 855 reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK; 856 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 857 wscnt = tcic_ns2wscnt(h->mem[win].speed); 858 #else 859 wscnt = tcic_ns2wscnt(tcic_mem_speed); /* 300 is "save" default for CIS memory */ 860 #endif 861 if (h->sc->chipid == TCIC_CHIPID_DB86082_1) { 862 /* 863 * this chip has the wait state count in window 864 * register 7 - hwwin. 865 */ 866 int reg2; 867 reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin)); 868 reg2 &= ~TCIC_MCTL_WSCNT_MASK; 869 reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK; 870 tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2); 871 } else { 872 reg |= wscnt & TCIC_MCTL_WSCNT_MASK; 873 } 874 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 875 876 #ifdef TCICDEBUG 877 { 878 int r1, r2, r3; 879 880 r1 = tcic_read_ind_2(h, TCIC_WR_MBASE_N(hwwin)); 881 r2 = tcic_read_ind_2(h, TCIC_WR_MMAP_N(hwwin)); 882 r3 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 883 884 DPRINTF(("tcic_chip_do_mem_map window %d(%d): %04x %04x %04x\n", 885 win, hwwin, r1, r2, r3)); 886 } 887 #endif 888 } 889 890 /* XXX needs work */ 891 int 892 tcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 893 pcmcia_chipset_handle_t pch; 894 int kind; 895 bus_addr_t card_addr; 896 bus_size_t size; 897 struct pcmcia_mem_handle *pcmhp; 898 bus_size_t *offsetp; 899 int *windowp; 900 { 901 struct tcic_handle *h = (struct tcic_handle *) pch; 902 bus_addr_t busaddr; 903 long card_offset; 904 int i, win; 905 906 win = -1; 907 for (i = 0; i < h->memwins; i++) { 908 if ((h->memalloc & (1 << i)) == 0) { 909 win = i; 910 h->memalloc |= (1 << i); 911 break; 912 } 913 } 914 915 if (win == -1) 916 return (1); 917 918 *windowp = win; 919 920 /* XXX this is pretty gross */ 921 922 if (h->sc->memt != pcmhp->memt) 923 panic("tcic_chip_mem_map memt is bogus"); 924 925 busaddr = pcmhp->addr; 926 927 /* 928 * compute the address offset to the pcmcia address space for the 929 * tcic. this is intentionally signed. The masks and shifts below 930 * will cause TRT to happen in the tcic registers. Deal with making 931 * sure the address is aligned, and return the alignment offset. 932 */ 933 934 *offsetp = card_addr % TCIC_MEM_ALIGN; 935 card_addr -= *offsetp; 936 937 DPRINTF(("tcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 938 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 939 (u_long) card_addr)); 940 941 /* XXX we can't use size. -chb */ 942 /* 943 * include the offset in the size, and decrement size by one, since 944 * the hw wants start/stop 945 */ 946 size += *offsetp - 1; 947 948 card_offset = (((long) card_addr) - ((long) busaddr)); 949 950 DPRINTF(("tcic_chip_mem_map window %d card_offset 0x%lx\n", 951 win, (u_long)card_offset)); 952 953 h->mem[win].addr = busaddr; 954 h->mem[win].size = size; 955 h->mem[win].size2 = tcic_log2((u_int)pcmhp->realsize) - TCIC_MEM_SHIFT; 956 h->mem[win].offset = card_offset; 957 h->mem[win].kind = kind; 958 959 tcic_chip_do_mem_map(h, win); 960 961 return (0); 962 } 963 964 void 965 tcic_chip_mem_unmap(pch, window) 966 pcmcia_chipset_handle_t pch; 967 int window; 968 { 969 struct tcic_handle *h = (struct tcic_handle *) pch; 970 int hwwin; 971 972 if (window >= h->memwins) 973 panic("tcic_chip_mem_unmap: window out of range"); 974 975 hwwin = (window << 1) + h->sock; 976 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), 0); 977 978 h->memalloc &= ~(1 << window); 979 } 980 981 int 982 tcic_chip_io_alloc(pch, start, size, align, pcihp) 983 pcmcia_chipset_handle_t pch; 984 bus_addr_t start; 985 bus_size_t size; 986 bus_size_t align; 987 struct pcmcia_io_handle *pcihp; 988 { 989 struct tcic_handle *h = (struct tcic_handle *) pch; 990 bus_space_tag_t iot; 991 bus_space_handle_t ioh; 992 bus_addr_t ioaddr; 993 int size2, flags = 0; 994 995 /* 996 * Allocate some arbitrary I/O space. 997 */ 998 999 DPRINTF(("tcic_chip_io_alloc req 0x%lx %ld %ld\n", 1000 (u_long) start, (u_long) size, (u_long) align)); 1001 /* 1002 * The TCIC can map I/O space only in sizes that are 1003 * powers of two, aligned at the natural boundary for the size. 1004 */ 1005 size2 = tcic_log2((u_int)size); 1006 if ((1 << size2) < size) 1007 size2++; 1008 /* can't allocate that much anyway */ 1009 if (size2 > 16) /* XXX 64K -chb */ 1010 return 1; 1011 if (align) { 1012 if ((1 << size2) != align) 1013 return 1; /* not suitably aligned */ 1014 } else { 1015 align = 1 << size2; /* no alignment given, make it natural */ 1016 } 1017 if (start & (align - 1)) 1018 return 1; /* not suitably aligned */ 1019 1020 iot = h->sc->iot; 1021 1022 if (start) { 1023 ioaddr = start; 1024 if (bus_space_map(iot, start, size, 0, &ioh)) 1025 return (1); 1026 DPRINTF(("tcic_chip_io_alloc map port %lx+%lx\n", 1027 (u_long) ioaddr, (u_long) size)); 1028 } else { 1029 flags |= PCMCIA_IO_ALLOCATED; 1030 if (bus_space_alloc(iot, h->sc->iobase, 1031 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 1032 &ioaddr, &ioh)) 1033 return (1); 1034 DPRINTF(("tcic_chip_io_alloc alloc port %lx+%lx\n", 1035 (u_long) ioaddr, (u_long) size)); 1036 } 1037 1038 pcihp->iot = iot; 1039 pcihp->ioh = ioh; 1040 pcihp->addr = ioaddr; 1041 pcihp->size = size; 1042 pcihp->flags = flags; 1043 1044 return (0); 1045 } 1046 1047 void 1048 tcic_chip_io_free(pcmcia_chipset_handle_t pch, 1049 struct pcmcia_io_handle *pcihp) 1050 { 1051 bus_space_tag_t iot = pcihp->iot; 1052 bus_space_handle_t ioh = pcihp->ioh; 1053 bus_size_t size = pcihp->size; 1054 1055 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1056 bus_space_free(iot, ioh, size); 1057 else 1058 bus_space_unmap(iot, ioh, size); 1059 } 1060 1061 static int tcic_iowidth_map[] = 1062 { TCIC_ICTL_AUTOSZ, TCIC_ICTL_B8, TCIC_ICTL_B16 }; 1063 1064 void 1065 tcic_chip_do_io_map(h, win) 1066 struct tcic_handle *h; 1067 int win; 1068 { 1069 int reg, size2, iotiny, wbase, hwwin, wscnt; 1070 1071 DPRINTF(("tcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1072 win, (long) h->io[win].addr, (long) h->io[win].size, 1073 h->io[win].width * 8)); 1074 1075 /* 1076 * the even windows are used for socket 0, 1077 * the odd ones for socket 1. 1078 */ 1079 hwwin = (win << 1) + h->sock; 1080 1081 /* set the WR_BASE register */ 1082 /* XXX what if size isn't power of 2? -chb */ 1083 size2 = tcic_log2((u_int)h->io[win].size); 1084 DPRINTF(("tcic_chip_do_io_map win %d size2 %d\n", win, size2)); 1085 if (size2 < 1) { 1086 iotiny = TCIC_ICTL_TINY; 1087 wbase = h->io[win].addr; 1088 } else { 1089 iotiny = 0; 1090 /* XXX we should do better -chb */ 1091 wbase = h->io[win].addr | (1 << (size2 - 1)); 1092 } 1093 tcic_write_ind_2(h, TCIC_WR_IBASE_N(hwwin), wbase); 1094 1095 /* set the WR_ICTL register */ 1096 reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET; 1097 reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK; 1098 reg |= iotiny | tcic_iowidth_map[h->io[win].width]; 1099 if (h->sc->chipid != TCIC_CHIPID_DB86082_1) 1100 reg |= TCIC_ICTL_PASS16; 1101 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 1102 wscnt = tcic_ns2wscnt(h->io[win].speed); 1103 #else 1104 wscnt = tcic_ns2wscnt(tcic_io_speed); /* linux uses 0 as default */ 1105 #endif 1106 reg |= wscnt & TCIC_ICTL_WSCNT_MASK; 1107 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1108 1109 #ifdef TCICDEBUG 1110 { 1111 int r1, r2; 1112 1113 r1 = tcic_read_ind_2(h, TCIC_WR_IBASE_N(hwwin)); 1114 r2 = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1115 1116 DPRINTF(("tcic_chip_do_io_map window %d(%d): %04x %04x\n", 1117 win, hwwin, r1, r2)); 1118 } 1119 #endif 1120 } 1121 1122 int 1123 tcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1124 pcmcia_chipset_handle_t pch; 1125 int width; 1126 bus_addr_t offset; 1127 bus_size_t size; 1128 struct pcmcia_io_handle *pcihp; 1129 int *windowp; 1130 { 1131 struct tcic_handle *h = (struct tcic_handle *) pch; 1132 bus_addr_t ioaddr = pcihp->addr + offset; 1133 int i, win; 1134 #ifdef TCICDEBUG 1135 static const char *width_names[] = { "auto", "io8", "io16" }; 1136 #endif 1137 1138 /* XXX Sanity check offset/size. */ 1139 1140 win = -1; 1141 for (i = 0; i < TCIC_IO_WINS; i++) { 1142 if ((h->ioalloc & (1 << i)) == 0) { 1143 win = i; 1144 h->ioalloc |= (1 << i); 1145 break; 1146 } 1147 } 1148 1149 if (win == -1) 1150 return (1); 1151 1152 *windowp = win; 1153 1154 /* XXX this is pretty gross */ 1155 1156 if (h->sc->iot != pcihp->iot) 1157 panic("tcic_chip_io_map iot is bogus"); 1158 1159 DPRINTF(("tcic_chip_io_map window %d %s port %lx+%lx\n", 1160 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1161 1162 /* XXX wtf is this doing here? */ 1163 1164 printf("%s: port 0x%lx", device_xname(&h->sc->dev), (u_long) ioaddr); 1165 if (size > 1) 1166 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1167 printf("\n"); 1168 1169 h->io[win].addr = ioaddr; 1170 h->io[win].size = size; 1171 h->io[win].width = width; 1172 1173 tcic_chip_do_io_map(h, win); 1174 1175 return (0); 1176 } 1177 1178 void 1179 tcic_chip_io_unmap(pch, window) 1180 pcmcia_chipset_handle_t pch; 1181 int window; 1182 { 1183 struct tcic_handle *h = (struct tcic_handle *) pch; 1184 int hwwin; 1185 1186 if (window >= TCIC_IO_WINS) 1187 panic("tcic_chip_io_unmap: window out of range"); 1188 1189 hwwin = (window << 1) + h->sock; 1190 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), 0); 1191 1192 h->ioalloc &= ~(1 << window); 1193 } 1194 1195 void 1196 tcic_chip_socket_enable(pch) 1197 pcmcia_chipset_handle_t pch; 1198 { 1199 struct tcic_handle *h = (struct tcic_handle *) pch; 1200 int reg, win; 1201 1202 tcic_sel_sock(h); 1203 1204 /* 1205 * power down the socket to reset it. 1206 * put card reset into high-z, put chip outputs to card into high-z 1207 */ 1208 1209 tcic_write_1(h, TCIC_R_PWR, 0); 1210 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1211 reg |= TCIC_ILOCK_CWAIT; 1212 reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA); 1213 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1214 tcic_write_1(h, TCIC_R_SCTRL, 0); /* clear TCIC_SCTRL_ENA */ 1215 1216 /* zero out the address windows */ 1217 1218 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), 0); 1219 /* writing to WR_MBASE_N disables the window */ 1220 for (win = 0; win < h->memwins; win++) { 1221 tcic_write_ind_2(h, TCIC_WR_MBASE_N((win << 1) + h->sock), 0); 1222 } 1223 /* writing to WR_IBASE_N disables the window */ 1224 for (win = 0; win < TCIC_IO_WINS; win++) { 1225 tcic_write_ind_2(h, TCIC_WR_IBASE_N((win << 1) + h->sock), 0); 1226 } 1227 1228 /* power up the socket */ 1229 1230 /* turn on VCC, turn of VPP */ 1231 reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena; 1232 if (h->sc->pwrena) /* this is a '84 type chip */ 1233 reg |= TCIC_PWR_VCC5V; 1234 tcic_write_1(h, TCIC_R_PWR, reg); 1235 delay(10000); 1236 1237 /* enable reset and wiggle it to reset the card */ 1238 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1239 reg |= TCIC_ILOCK_CRESENA; 1240 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1241 /* XXX need bus_space_barrier here */ 1242 reg |= TCIC_ILOCK_CRESET; 1243 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1244 /* enable card signals */ 1245 tcic_write_1(h, TCIC_R_SCTRL, TCIC_SCTRL_ENA); 1246 delay(10); /* wait 10 us */ 1247 1248 /* clear the reset flag */ 1249 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1250 reg &= ~(TCIC_ILOCK_CRESET); 1251 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1252 1253 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1254 delay(20000); 1255 1256 /* wait for the chip to finish initializing */ 1257 tcic_wait_ready(h); 1258 1259 /* WWW */ 1260 1261 /* reinstall all the memory and io mappings */ 1262 1263 for (win = 0; win < h->memwins; win++) 1264 if (h->memalloc & (1 << win)) 1265 tcic_chip_do_mem_map(h, win); 1266 1267 for (win = 0; win < TCIC_IO_WINS; win++) 1268 if (h->ioalloc & (1 << win)) 1269 tcic_chip_do_io_map(h, win); 1270 } 1271 1272 void 1273 tcic_chip_socket_settype(pch, type) 1274 pcmcia_chipset_handle_t pch; 1275 int type; 1276 { 1277 struct tcic_handle *h = (struct tcic_handle *) pch; 1278 int reg; 1279 1280 tcic_sel_sock(h); 1281 1282 /* set the card type */ 1283 1284 reg = 0; 1285 if (type == PCMCIA_IFTYPE_IO) { 1286 reg |= TCIC_SCF1_IOSTS; 1287 reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */ 1288 } 1289 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg); 1290 1291 DPRINTF(("%s: tcic_chip_socket_enable %d cardtype %s 0x%02x\n", 1292 device_xname(&h->sc->dev), h->sock, 1293 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1294 } 1295 1296 void 1297 tcic_chip_socket_disable(pch) 1298 pcmcia_chipset_handle_t pch; 1299 { 1300 struct tcic_handle *h = (struct tcic_handle *) pch; 1301 int val; 1302 1303 DPRINTF(("tcic_chip_socket_disable\n")); 1304 1305 tcic_sel_sock(h); 1306 1307 /* disable interrupts */ 1308 val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1309 val &= TCIC_SCF1_IRQ_MASK; 1310 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val); 1311 1312 /* disable the output signals */ 1313 tcic_write_1(h, TCIC_R_SCTRL, 0); 1314 val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1315 val &= ~TCIC_ILOCK_CRESENA; 1316 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val); 1317 1318 /* power down the socket */ 1319 tcic_write_1(h, TCIC_R_PWR, 0); 1320 } 1321 1322 /* 1323 * XXX The following is Linux driver but doesn't match the table 1324 * in the manual. 1325 */ 1326 int 1327 tcic_ns2wscnt(ns) 1328 int ns; 1329 { 1330 if (ns < 14) { 1331 return 0; 1332 } else { 1333 return (2*(ns-14))/70; /* XXX assumes 14.31818 MHz clock. */ 1334 } 1335 } 1336 1337 int 1338 tcic_log2(val) 1339 u_int val; 1340 { 1341 int i, l2; 1342 1343 l2 = i = 0; 1344 while (val) { 1345 if (val & 1) 1346 l2 = i; 1347 i++; 1348 val >>= 1; 1349 } 1350 return l2; 1351 }
Cache object: 57ccb68b8f1f2c9f675f313de47333a6
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]