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sys/dev/ic/tcic2reg.h
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1 /* $NetBSD: tcic2reg.h,v 1.3 2005/02/27 00:27:02 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Christoph Badura. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * All information is from the Databook DB86082 TCIC PC Card Controller for 41 * Notebook PCs -- Hardware Design Guide, March 22, 1994. 42 */ 43 44 #ifndef _TCIC2REG_H 45 #define _TCIC2REG_H 46 #define TCIC_IOSIZE 16 47 48 /* TCIC primary registers */ 49 #define TCIC_R_DATA 0 /* Data register, 16 bit */ 50 #define TCIC_R_ADDR 2 /* Address register, 32 bit */ 51 #define TCIC_R_ADDR2 (TCIC_R_ADDR+2) /* high word of addr. reg. */ 52 #define TCIC_R_SCTRL 6 /* Socket control reg., 8 bit */ 53 #define TCIC_R_SSTAT 7 /* Socket status reg., 8 bit */ 54 #define TCIC_R_MODE 8 /* Mode register, 8 bit */ 55 #define TCIC_R_PWR 9 /* Power control reg., 8 bit */ 56 #define TCIC_R_EDC 0xA /* Error detect code, 16 bit */ 57 #define TCIC_R_ICSR 0xC /* Interrupt ctrl/status, 8 bit */ 58 #define TCIC_R_IENA 0xD /* Interrupt enable, 8 bit */ 59 #define TCIC_R_AUX 0xE /* Auxiliary Register, 16 bit */ 60 61 /* 62 * TCIC auxiliary registers. 63 * These are all 16 bit registers. 64 * They are accessed by selecting the appropriate index in 65 * bits 7:5 of the mode register. 66 */ 67 #define TCIC_AR_MASK 0xe0 /* for masking the mode reg. */ 68 #define TCIC_AR_TCTL 0x00 /* timing control register */ 69 #define TCIC_AR_PCTL 0x20 /* programming pulse ctrl. */ 70 #define TCIC_AR_WCTL 0x40 /* wait state control */ 71 #define TCIC_AR_EXTERN 0x60 /* external access */ 72 #define TCIC_AR_PDATA 0x80 /* programming data */ 73 #define TCIC_AR_SYSCFG 0xA0 /* system configuration */ 74 #define TCIC_AR_ILOCK 0xC0 /* interlock control/status */ 75 #define TCIC_AR_TEST 0xE0 /* test */ 76 77 /* 78 * TCIC indirect registers. 79 * These are all 16 bit. 80 * They are accessed by selecting the appropriate address in 81 * bits 9:0 of the address register with indirect register access mode 82 * enabled. 83 */ 84 #define TCIC_WR_MEM_BASE 0x100 /* base address */ 85 #define TCIC_WR_MEM_SHFT 3 /* log2 size of one reg set */ 86 #define TCIC_WR_MEXT_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+0) 87 #define TCIC_WR_MBASE_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+2) 88 #define TCIC_WR_MMAP_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+4) 89 #define TCIC_WR_MCTL_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+6) 90 91 #define TCIC_WR_IO_BASE 0x200 /* base address */ 92 #define TCIC_WR_IO_SHFT 2 /* log2 size of one reg set */ 93 #define TCIC_WR_IBASE_N(n) ((TCIC_WR_IO_BASE+((n)<<TCIC_WR_IO_SHFT))+0) 94 #define TCIC_WR_ICTL_N(n) ((TCIC_WR_IO_BASE+((n)<<TCIC_WR_IO_SHFT))+2) 95 96 #define TCIC_IR_SCF_BASE 0 /* base address */ 97 #define TCIC_IR_SCF_SHFT 3 /* log2 size of one reg set */ 98 #define TCIC_IR_SCF1_N(n) ((TCIC_IR_SCF_BASE+((n)<<TCIC_IR_SCF_SHFT))+0) 99 #define TCIC_IR_SCF2_N(n) ((TCIC_IR_SCF_BASE+((n)<<TCIC_IR_SCF_SHFT))+2) 100 101 102 /* Bits in the ADDR2 register */ 103 #define TCIC_SS_SHIFT 12 /* location of socket select bits */ 104 #define TCIC_SS_MASK (7<<(TCIC_SS_SHIFT)) /* socket select mask */ 105 106 #define TCIC_ADDR2_REG (1 << 15) /* select REG space */ 107 #define TCIC_ADDR2_SS_SHFT TCIC_SS_SHIFT /* select sockets the usual way */ 108 #define TCIC_ADDR2_SS_MASK TCIC_SS_MASK /* ditto */ 109 #define TCIC_ADDR2_INDREG (1 << 11) /* access indirect registers 110 * (not card data) 111 */ 112 #define TCIC_ADDR2_IO (1 << 10) /* select I/O cycles, readback 113 * card /IORD, /IOWR in diag- 114 * nostic mode. 115 */ 116 117 /* Bits in address register */ 118 #define TCIC_ADDR_REG (u_int32_t) TCIC_ADDR2_REG << 16) /* OR with this for REG space */ 119 #define TCIC_ADDR_SS_SHFT ((u_int32_t) TCIC_ADDR2_SS_SHFT + 16) 120 /* shift count, cast so that 121 * you'll get the right type 122 * if you use it but forget 123 * to cast the left arg. 124 */ 125 #define TCIC_ADDR_SS_MASK ((u_int32_t) TCIC_ADDR2_SS_MASK << 16) 126 #define TCIC_ADDR_INDREG ((u_int32_t) TCIC_ADDR2_INDREG << 16) 127 #define TCIC_ADDR_IO ((u_int32_t) TCIC_ADDR2_IO << 16) 128 129 #define TCIC_ADDR_SPACE_SIZE ((u_int32_t) 1 << 26) 130 #define TCIC_ADDR_MASK (ADDR_SPACE_SIZE - 1) 131 132 /* The following bits are defined in diagnostic mode */ 133 #define TCIC_ADDR_DIAG_NREG ((u_int32_t) 1 << 31) /* inverted! */ 134 #define TCIC_ADDR_DIAG_NCEH ((u_int32_t) 1 << 30) 135 #define TCIC_ADDR_DIAG_NCEL ((u_int32_t) 1 << 29) 136 #define TCIC_ADDR_DIAG_NCWR ((u_int32_t) 1 << 28) 137 #define TCIC_ADDR_DIAG_NCRD ((u_int32_t) 1 << 27) 138 #define TCIC_ADDR_DIAG_CRESET ((u_int32_t) 1 << 26) 139 140 /* Bits in socket control register */ 141 #define TCIC_SCTRL_ENA (1 << 0) /* enable access to card */ 142 #define TCIC_SCTRL_INCMODE (3 << 3) /* mask for increment mode: */ 143 #define TCIC_SCTRL_INCMODE_AUTO (3 << 3) /* auto-increment mode */ 144 #define TCIC_SCTRL_INCMODE_HOLD (0 << 3) /* byte hold mode */ 145 #define TCIC_SCTRL_INCMODE_WORD (1 << 3) /* word hold mode */ 146 #define TCIC_SCTRL_INCMODE_REG (2 << 3) /* reg-space increment mode */ 147 #define TCIC_SCTRL_EDCSUM (1 << 5) /* if set, use checksum (not CRC) */ 148 #define TCIC_SCTRL_RESET (1 << 7) /* internal software reset */ 149 #define TCIC_SCTRL_RSVD 0x46 /* reserved bits, MBZ */ 150 151 /* Bits in the socket status register */ 152 #define TCIC_SSTAT_6US (1<<0) /* 6 usec have elapsed */ 153 #define TCIC_SSTAT_10US (1<<1) /* 10 usec have elapsed */ 154 #define TCIC_SSTAT_PROGTIME (1<<2) /* programming pulse timeout */ 155 #define TCIC_SSTAT_LBAT1 (1<<3) /* low battery 1 */ 156 #define TCIC_SSTAT_LBAT2 (1<<4) /* low battery 2 */ 157 #define TCIC_SSTAT_BATOK (0<<3) /* battery is OK */ 158 #define TCIC_SSTAT_BATBAD1 (1<<3) /* battery is low */ 159 #define TCIC_SSTAT_BATLO (2<<3) /* battery is getting low */ 160 #define TCIC_SSTAT_BATBAD2 (3<<3) /* battery is low */ 161 #define TCIC_SSTAT_RDY (1<<5) /* card is ready (not busy) */ 162 #define TCIC_SSTAT_WP (1<<6) /* card is write-protected */ 163 #define TCIC_SSTAT_CD (1<<7) /* card present */ 164 #define TCIC_SSTAT_STAT_MASK 0xf8 165 166 /* Mode register contents (R_MODE) */ 167 #define TCIC_MODE_PGMMASK (0x1F) /* the programming mode bits */ 168 #define TCIC_MODE_NORMAL (0) /* normal mode */ 169 #define TCIC_MODE_PGMWR (1 << 0) /* assert /WR */ 170 #define TCIC_MODE_PGMRD (1 << 1) /* assert /RD */ 171 #define TCIC_MODE_PGMCE (1 << 2) /* assert /CEx */ 172 #define TCIC_MODE_PGMDBW (1 << 3) /* databus in write mode */ 173 #define TCIC_MODE_PGMWORD (1 << 4) /* word programming mode */ 174 175 /* Power control register contents (R_PWR) */ 176 #define TCIC_PWR_VCC_SHFT (0) /* the VCC ctl shift */ 177 #define TCIC_PWR_VCC_MASK (3 << TCIC_PWR_VCC_SHFT) 178 179 #define TCIC_PWR_VPP_SHFT (3) /* the VPP ctl shift */ 180 #define TCIC_PWR_VPP_MASK (3 << TCIC_PWR_VPP_SHFT) 181 #define TCIC_PWR_ENA (1 << 5) /* on 084, successors, this 182 * must be set to turn on 183 * power. 184 */ 185 #define TCIC_PWR_VCC5V (1 << 2) /* enable +5 (not +3) */ 186 #if 0 187 #define TCIC_PWR_VOFF_POFF (0) /* turn off VCC, VPP */ 188 #define TCIC_PWR_VON_PVCC (1) /* turn on VCC, VPP=VCC */ 189 #define TCIC_PWR_VON_PVPP (2) /* turn on VCC, VPP=12V */ 190 #define TCIC_PWR_VON_POFF (3) /* turn on VCC, VPP=0V */ 191 #endif 192 #define TCIC_PWR_VCC_N(n) (1<<((n))) /* VCCSEL for socket n */ 193 #define TCIC_PWR_VPP_N(n) (1<<(3+(n))) /* VPPSEL for socket n */ 194 195 #define TCIC_PWR_CLIMENA (1 << 6) /* the current-limit enable */ 196 #define TCIC_PWR_CLIMSTAT (1 << 7) /* current limit sense (r/o) */ 197 198 /* Bits in the icsr register. */ 199 #define TCIC_ICSR_IOCHK (1<<7) /* I/O check */ 200 #define TCIC_ICSR_CDCHG (1<<6) /* card status change, see SSTAT */ 201 #define TCIC_ICSR_ERR (1<<5) /* error condition */ 202 #define TCIC_ICSR_PROGTIME (1<<4) /* program timer ding */ 203 #define TCIC_ICSR_ILOCK (1<<3) /* interlock change */ 204 #define TCIC_ICSR_STOPCPU (1<<2) /* Stop CPU was asserted */ 205 #define TCIC_ICSR_SET (1<<1) /* (w/o) enable writes that set bits */ 206 #define TCIC_ICSR_CLEAR (1<<0) /* (w/o) enable writes that clear */ 207 #define TCIC_ICSR_JAM (TCIC_ICSR_SET|TCIC_ICSR_CLEAR) 208 /* jam value into ICSR */ 209 210 /* bits in the interrupt enable register */ 211 #define TCIC_IENA_CDCHG (1 << 6) /* enable INT when ICSR_CDCHG is set */ 212 #define TCIC_IENA_ERR (1 << 5) /* enable INT when ICSR_ERR is set */ 213 #define TCIC_IENA_PROGTIME (1 << 4) /* enable INT when ICSR_PROGTIME " */ 214 #define TCIC_IENA_ILOCK (1 << 3) /* enable INT when ICSR_ILOCK is set */ 215 #define TCIC_IENA_CFG_MASK (3 << 0) /* select the bits for IRQ config: */ 216 #define TCIC_IENA_CFG_OFF (0 << 0) /* IRQ is high-impedance */ 217 #define TCIC_IENA_CFG_OD (1 << 0) /* IRQ is active low, open drain. */ 218 #define TCIC_IENA_CFG_LOW (2 << 0) /* IRQ is active low, totem pole */ 219 #define TCIC_IENA_CFG_HIGH (3 << 0) /* IRQ is active high, totem pole */ 220 #define TCIC_IENA_RSVD 0x84 /* reserved bits, MBZ */ 221 222 223 /* 224 * Bits in the auxiliary registers 225 */ 226 227 /* Bits in the timing control register (AR_TCTL) */ 228 #define TCIC_TCTL_6US_SHFT (0) /* the shift count for the 6 us ctr */ 229 #define TCIC_TCTL_10US_SHFT (8) /* the shift count for the 10 us ctr */ 230 #define TCIC_TCTL_6US_MASK (0xFF << TCIC_TCTL_6US_SHFT) 231 #define TCIC_TCTL_10US_MASK (0xFF << TCIC_TCTL_10US_SHFT) 232 233 #define TCIC_R_TCTL_6US (TCIC_R_AUX + 0) /* the byte access handle */ 234 #define TCIC_R_TCTL_10US (TCIC_R_AUX + 1) /* the byte access handle */ 235 236 /* Bits in the programming pulse register (AR_PCTL) */ 237 #define TCIC_R_PULSE_LO (TCIC_R_AUX + 0) 238 #define TCIC_R_PULSE_HI (TCIC_R_AUX + 1) 239 240 /* Bits in the wait state control register (AR_WCTL) */ 241 #define TCIC_WAIT_COUNT_MASK (0x1F) /* the count of 1/2 wait states */ 242 #define TCIC_WAIT_COUNT_SHFT (0) /* the wait-count shift */ 243 #define TCIC_WAIT_SYNC (1 << 5) /* set for synch, clear for asynch cycles */ 244 #define TCIC_WAIT_ASYNC (0) 245 246 #define TCIC_WAIT_SENSE (1 << 6) /* select rising (1) or falling (0) 247 * edge of wait clock as reference 248 * edge. 249 */ 250 #define TCIC_WAIT_SRC (1 << 7) /* select constant clock (0) or bus 251 * clock (1) as the timing source 252 */ 253 254 /* Some derived constants */ 255 #define TCIC_WAIT_BCLK (1 * TCIC_WAIT_SRC) 256 #define TCIC_WAIT_CCLK (0 * TCIC_WAIT_SRC) 257 #define TCIC_WAIT_RISING (1 * TCIC_WAIT_SENSE) 258 #define TCIC_WAIT_FALLING (0 * TCIC_WAIT_SENSE) 259 260 /* high byte */ 261 #define TCIC_WCTL_WR (1 << 8) /* control: pulse write */ 262 #define TCIC_WCTL_RD (1 << 9) /* control: pulse read */ 263 #define TCIC_WCTL_CE (1 << 10) /* control: pulse chip ena */ 264 #define TCIC_WCTL_LLBAT1 (1 << 11) /* status: latched LBAT1 */ 265 #define TCIC_WCTL_LLBAT2 (1 << 12) /* status: latched LBAT2 */ 266 #define TCIC_WCTL_LRDY (1 << 13) /* status: latched RDY */ 267 #define TCIC_WCTL_LWP (1 << 14) /* status: latched WP */ 268 #define TCIC_WCTL_LCD (1 << 15) /* status: latched CD */ 269 270 /* The same thing, from a byte perspective */ 271 #define TCIC_R_WCTL_WAIT (TCIC_R_AUX + 0) /* the wait state control byte */ 272 #define TCIC_R_WCTL_XCSR (TCIC_R_AUX + 1) /* extended control/status */ 273 274 #define TCIC_XCSR_WR (1 << 0) /* control: pulse write */ 275 #define TCIC_XCSR_RD (1 << 1) /* control: pulse read */ 276 #define TCIC_XCSR_CE (1 << 2) /* control: pulse chip ena */ 277 #define TCIC_XCSR_LLBAT1 (1 << 3) /* status: latched LBAT1 */ 278 #define TCIC_XCSR_LLBAT2 (1 << 4) /* status: latched LBAT2 */ 279 #define TCIC_XCSR_LRDY (1 << 5) /* status: latched RDY */ 280 #define TCIC_XCSR_LWP (1 << 6) /* status: latched WP */ 281 #define TCIC_XCSR_LCD (1 << 7) /* status: latched CD */ 282 #define TCIC_XCSR_STAT_MASK 0xf8 283 284 /* Bits in the programming data register (AR_PDATA) */ 285 #define TCIC_R_PDATA_LO (TCIC_R_AUX + 0) 286 #define TCIC_R_PDATA_HI (TCIC_R_AUX + 1) 287 288 /* Bits in the system configuration register (AR_SYSCFG) */ 289 /* 290 * The bottom four bits specify the steering of the socket IRQ. On 291 * the 2N, the socket IRQ is (by default) pointed at the dedicated 292 * pin. 293 */ 294 #define TCIC_SYSCFG_IRQ_MASK (0xF) /* mask for this bit field. */ 295 #define TCIC_SYSCFG_SSIRQDFLT (0) /* default: use SKTIRQ (2/N) 296 * disable (2/P) 297 */ 298 #define TCIC_SYSCFG_SSIRQ (0x1) /* use SKTIRQ (explicit) (2/N) 299 * do not use (2/P) 300 */ 301 #define TCIC_SYSCFG_SIRQ3 (0x3) /* use IRQ3 */ 302 #define TCIC_SYSCFG_SIRQ4 (0x4) /* use IRQ4 */ 303 #define TCIC_SYSCFG_SIRQ5 (0x5) /* use IRQ5 (2/N) */ 304 #define TCIC_SYSCFG_SIRQ6 (0x6) /* use IRQ6 (2/N) */ 305 #define TCIC_SYSCFG_SIRQ7 (0x7) /* use IRQ7 (2/N) */ 306 #define TCIC_SYSCFG_SIRQ10 (0xA) /* use IRQ10 */ 307 #define TCIC_SYSCFG_SIRQ14 (0xE) /* use IRQ14 */ 308 309 #define TCIC_SYSCFG_MCSFULL (1 << 4) 310 /* 311 * If set, use full address (a[12:23]) for MCS16 generation. 312 * If clear, run in ISA-compatible mode (only using a[17:23]). 313 * With many chip sets, the TCIC-2/N's timing will will allow full 314 * address decoding to be used rather than limiting us to LA[17:23]; 315 * thus we can get around the ISA spec which limits the granularity 316 * of bus sizing to 128K blocks. 317 */ 318 #define TCIC_SYSCFG_IO1723 (1 << 5) 319 /* 320 * Flag indicating that LA[17:23] can be trusted to be zero during a 321 * true I/O cycle. Setting this bit will allow us to reduce power 322 * consumption further by eliminating I/O address broadcasts for 323 * memory cycles. 324 * 325 * Unfortunately, you cannot trust LA[17:23] to be zero on all systems, 326 * because the ISA specs do not require that LA[17:23] be zero when an 327 * alternate bus master runs an I/O cycle. However, on a palmtop or 328 * notebook, it is a good guess. 329 */ 330 331 #define TCIC_SYSCFG_MCSXB (1 << 6) 332 /* 333 * If set, assume presence of an external buffer for MCS16: operate 334 * the driver as a totem-pole output. 335 * 336 * If clear, run in pseudo-ISA mode; output is open drain. But note 337 * that on the 082 the output buffers cannot drive a 300-ohm 338 * load. 339 */ 340 #define TCIC_SYSCFG_ICSXB (1 << 7) 341 /* 342 * If set, assume presence of an external buffer for IOCS16*; operate 343 * the buffer as a totem-pole output. 344 * 345 * If clear, run in pseudo-ISA mode; output is open drain. But note 346 * that on the 082 the output buffers cannot drive a 300-ohm 347 * load. 348 */ 349 #define TCIC_SYSCFG_NOPDN (1 << 8) 350 /* 351 * If set, disable the auto power-down sequencing. The chip will 352 * run card cycles somewhat more quickly (though perhaps not 353 * significantly so); but it will dissipate significantly more power. 354 * 355 * If clear, the low-power operating modes are enabled. This 356 * causes the part to go into low-power mode automatically at 357 * system reset. 358 */ 359 #define TCIC_SYSCFG_MPSEL_SHFT (9) 360 #define TCIC_SYSCFG_MPSEL_MASK (7 << 9) 361 /* 362 * This field controls the operation of the multipurpose pin on the 363 * 86082. It has the following codes: 364 */ 365 #define TCIC_SYSCFG_MPSEL_OFF (0 << TCIC_SYSCFG_MPSEL_SHFT) 366 /* 367 * This is the reset state; it indicates that the Multi-purpose 368 * pin is not used. The pin will be held in a high-impedance 369 * state. It can be read by monitoring SYSCFG_MPSENSE. 370 */ 371 #define TCIC_SYSCFG_MPSEL_NEEDCLK (1 << TCIC_SYSCFG_MPSEL_SHFT) 372 /* 373 * NMULTI is an output. 374 * External indication that CCLK or BCLK are needed in order 375 * to complete an internal operation. External logic can use 376 * this to control the clocks coming to the chip. 377 */ 378 #define TCIC_SYSCFG_MPSEL_MIO (2 << TCIC_SYSCFG_MPSEL_SHFT) 379 /* 380 * NMULTI is an input; it is an unambiguous M/IO signal, issued 381 * with timing similar to the LA[] lines. 382 */ 383 #define TCIC_SYSCFG_MPSEL_EXTSEL (3 << TCIC_SYSCFG_MPSEL_SHFT) 384 /* 385 * NMULTI is an output; it is the external register select 386 * pulse, generated whenever software attempts to access 387 * aux register AR_EXTRN. Of course, the 86082 will ignore 388 * writes to AR_EXTRN, and will float the data bus if 389 * the CPU reads from AR_EXTRN. 390 */ 391 392 /* (4 << TCIC_SYSCFG_MPSEL_SHFT) is reserved */ 393 394 #define TCIC_SYSCFG_MPSEL_RI (5 << TCIC_SYSCFG_MPSEL_SHFT) 395 /* 396 * NMULTI is an output; it indicates a RI (active-going) 397 * transition has occurred lately on a an appropriately- 398 * configured socket. The output is active low. 399 */ 400 /* 401 * Codes 4, 6 and 7 are reserved, and must NOT be output. It is 402 * indeed possibly hazardous to your system to encode values in 403 * this field that do not match your hardware! 404 */ 405 406 /* 1 << 12 reserved */ 407 408 #define TCIC_SYSCFG_MPSENSE (1 << 13) 409 /* 410 * This bit, when read, returns the sense of the multi-purpose pin. 411 */ 412 413 #define TCIC_SYSCFG_AUTOBUSY (1 << 14) 414 /* 415 * This bit, when set, causes the busy led to be gated with the 416 * SYSCFG_ACC bit. When clear, the busy led reflects whether the 417 * socket is actually enabled. If AUTOBUSY is set and ACC is clear, 418 * then the busy light will be off, even if a socket is enabled. 419 * If AUTOBUSY is clear, then the busy light will be on if either 420 * socket is enabled. 421 * 422 * Note, that when in a programming mode, you should either clear this 423 * bit (causing the busy light to be on whenever the socket is enabled) 424 * or set both this bit and the ACC bit (causing the light to be on 425 * all the time). 426 * 427 * On the '084 and '184, this bit is per-socket. 428 */ 429 430 #define TCIC_SYSCFG_ACC (1<<15) 431 /* 432 * This bit will be set automatically by the hardware whenever the CPU 433 * accesses data on a card. It can be cleared under software control. 434 * 435 * In AUTOBUSY mode, it has the additional effect of turning on the 436 * busy light. 437 * 438 * Since we'll tristate the command lines as the card is going out of 439 * the socket, and since the shared lines idle low, there's no real 440 * danger if the busy light is off even though the socket is enabled. 441 * 442 * On the '084 and '184, this bit is per-socket. 443 */ 444 445 446 /* Bits in the ilock aux. register. */ 447 #define TCIC_ILOCK_OUT (1 << 0) /* interlock output 448 * per-socket on x84 449 */ 450 #define TCIC_ILOCK_SENSE (1 << 1) /* (r/o) interlock sense 451 * 0 -> /cilock not asserted; 452 * 1 -> /cilock is asserted. 453 * per-socket on x84. 454 */ 455 #define TCIC_ILOCK_CRESET (1 << 2) /* card reset output level(S) */ 456 #define TCIC_ILOCK_CRESENA (1 << 3) /* enable card reset output (S) */ 457 #define TCIC_ILOCK_CWAIT (1 << 4) /* enable card wait (S) */ 458 #define TCIC_ILOCK_CWAITSNS (1 << 5) /* (r/o) sense current state of wait 459 * 0 -> /cwait not asserted; 460 * 1 -> /cwait is asserted 461 * (S) 462 */ 463 /* The shift count & mask for the hold-time control */ 464 #define TCIC_ILOCK_HOLD_SHIFT 6 /* shift count for the hold-time ctl (G) */ 465 #define TCIC_ILOCK_HOLD_MASK (3 << TCIC_ILOCK_HOLD_SHIFT) 466 467 /* 468 * Quick hold mode waits until we observe that the strobe is high, 469 * guaranteeing 10ns or so of hold time. 470 */ 471 #define TCIC_ILOCK_HOLD_QUICK (0 << TCIC_ILOCK_HOLD_SHIFT) 472 473 /* 474 * CCLK hold mode waits (asynchronously) for an edge on CCLK. Minimum is 1 475 * CCLK + epsilon; maximum is 2 CCLKs + epsilon. 476 * 477 * for the 86081 & '82, this mode enables the multi-step 478 * sequencer that generates setup and hold times based on CCLK. This 479 * is the recommended mode of operation for the '81 and '82. 480 * 481 */ 482 #define TCIC_ILOCK_HOLD_CCLK (3 << TCIC_ILOCK_HOLD_SHIFT) 483 484 /* The following bits are only present on the x84 and later parts */ 485 #define TCIC_ILOCK_INPACK (1 << 11) /* (r/o, S) this bit is a diagnostic 486 * read-back for card input 487 * acknowledge. 488 * The sense is inverted from 489 * the level at the pin. 490 */ 491 #define TCIC_ILOCK_CP0 (1 << 12) /* (r/o, S) this bit is a diagnostic 492 * monitor for card present pin 0. 493 * The sense is inverted from the 494 * level at the pin. 495 */ 496 #define TCIC_ILOCK_CP1 (1 << 13) /* (r/o, S) this bit is a diagnostic 497 * monitor for card present pin 1. 498 * The sense is inverted from the 499 * level at the pin. 500 */ 501 #define TCIC_ILOCK_VS1 (1 << 14) /* (r/o, S) this bit is the primary 502 * monitor for Card Voltage Sense 503 * pin 1. 504 * The sense is inverted from the 505 * level at the pin. 506 */ 507 #define TCIC_ILOCK_VS2 (1 << 15) /* (r/o, S) this bit is the primary 508 * monitor for Card Voltage Sense 509 * pin 2. 510 * The sense is inverted from the 511 * level at the pin. 512 */ 513 /* 514 * Silicon Version Register 515 * 516 * In diagnostic mode, the high byte of the interlock register is defined 517 * as the silicon identity byte. 518 * 519 * In order to read this byte, the chip must be placed in diagnostic 520 * mode by setting bit 15 of the TESTDIAG register. (This may or may 521 * not be enforced by the silicon.) 522 * 523 * The layout is: 524 * 525 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 526 * m <-------ID-------> <----ILOCK----> 527 * 528 * The fields are: 529 * 530 * m Always reset. 531 * 532 * ID This field is one of the following: 533 * 534 * 0x02 the db86082 535 * 0x03 the db86082a 536 * 0x04 the db86084 537 * 0x05 the DB86072ES, (Engineering Sample) 538 * 0x07 the db86082bES, (Engineering Sample) 539 * 0x08 the db86084a 540 * 0x14 the DB86184 541 * 0x15 the DB86072, (Production) 542 * 0x17 the db86082b, (Production) 543 */ 544 545 /* 546 * Defines for Chip IDs described above. 547 * 548 * Use the following convention for defining TCIC_CHIPID_DBxxxxxY: 549 * 550 * TCIC_CHIPID_DBxxxxx_1 The First step of chip. 551 * TCIC_CHIPID_DBxxxxxA The Second step of chip. 552 * TCIC_CHIPID_DBxxxxxB The Third step of chip. 553 * TCIC_CHIPID_DBxxxxx... The ... step of chip. 554 * 555 * TCIC_CHIPID_DBxxxxx"step of chip"_ES An Engineering Sample of chip. 556 * 557 */ 558 #define TCIC_CHIPID_DB86082_1 (0x02) 559 #define TCIC_CHIPID_DB86082A (0x03) 560 #define TCIC_CHIPID_DB86082B_ES (0x07) 561 #define TCIC_CHIPID_DB86082B (0x17) 562 563 #define TCIC_CHIPID_DB86084_1 (0x04) 564 #define TCIC_CHIPID_DB86084A (0x08) 565 566 #define TCIC_CHIPID_DB86184_1 (0x14) 567 568 #define TCIC_CHIPID_DB86072_1_ES (0x05) 569 #define TCIC_CHIPID_DB86072_1 (0x15) 570 571 572 /* the high order bits (in diag mode) give the chip version */ 573 #define TCIC_R_ILOCK_ID (TCIC_R_AUX + 1) 574 575 #define TCIC_ILOCKTEST_ID_SHFT 8 /* the shift count */ 576 #define TCIC_ILOCKTEST_ID_MASK (0x7F << TCIC_ILOCKTEST_ID_SHFT) 577 /* the mask for the field */ 578 /* 579 * Use the following convention for defining TCIC_ILOCKTEST_DBxxxxxY: 580 * 581 * TCIC_ILOCKTEST_DBxxxxx_1 The First step of chip. 582 * TCIC_ILOCKTEST_DBxxxxxA The Second step of chip. 583 * TCIC_ILOCKTEST_DBxxxxxB The Third step of chip. 584 * TCIC_ILOCKTEST_DBxxxxx... The ... step of chip. 585 * 586 * TCIC_ILOCKTEST_DBxxxxx"step of chip"_ES An Engineering Sample of chip. 587 * 588 */ 589 #define TCIC_ILOCKTEST_TCIC2N_1 ((TCIC_CHIPID_DB86082_1) << TCIC_ILOCKTEST_ID_SHFT) 590 #define TCIC_ILOCKTEST_DB86082_1 TCIC_ILOCKTEST_TCIC2N_1 591 #define TCIC_ILOCKTEST_TCIC2N_2 ((TCIC_CHIPID_DB86082A) << TCIC_ILOCKTEST_ID_SHFT) 592 #define TCIC_ILOCKTEST_DB86082A TCIC_ILOCKTEST_TCIC2N_2 593 #define TCIC_ILOCKTEST_TCIC2N_3 ((TCIC_CHIPID_DB86082B_ES) << TCIC_ILOCKTEST_ID_SHFT) 594 #define TCIC_ILOCKTEST_DB86082B_ES TCIC_ILOCKTEST_TCIC2N_3 595 596 #define TCIC_ILOCKTEST_DB86082B ((TCIC_CHIPID_DB86082B) << TCIC_ILOCKTEST_ID_SHFT) 597 598 #define TCIC_ILOCKTEST_DB86084_1 ((TCIC_CHIPID_DB86084_1) << TCIC_ILOCKTEST_ID_SHFT) 599 #define TCIC_ILOCKTEST_DB86084A ((TCIC_CHIPID_DB86084A) << TCIC_ILOCKTEST_ID_SHFT) 600 601 #define TCIC_ILOCKTEST_DB86184_1 ((TCIC_CHIPID_DB86184_1) << TCIC_ILOCKTEST_ID_SHFT) 602 603 #define TCIC_ILOCKTEST_DB86072_1 ((TCIC_CHIPID_DB86072_1) << TCIC_ILOCKTEST_ID_SHFT) 604 #define TCIC_ILOCKTEST_DB86072_1_ES ((TCIC_CHIPID_DB86072_1_ES) << TCIC_ILOCKTEST_ID_SHFT) 605 606 607 /* Bits in the test control register (AR_TEST) */ 608 #define TCIC_R_TEST (TCIC_R_AUX + 0) 609 #define TCIC_TEST_AEN (1 << 0) /* force card AEN */ 610 #define TCIC_TEST_CEN (1 << 1) /* force card CEN */ 611 #define TCIC_TEST_CTR (1 << 2) /* test programming pulse, address ctrs */ 612 #define TCIC_TEST_ENA (1 << 3) /* force card-present (for test), and 613 * special VPP test mode 614 */ 615 #define TCIC_TEST_IO (1 << 4) /* feed back some I/O signals 616 * internally. 617 */ 618 #define TCIC_TEST_OUT1 (1 << 5) /* force special address output mode */ 619 #define TCIC_TEST_ZPB (1 << 6) /* enter ZPB test mode */ 620 #define TCIC_TEST_WAIT (1 << 7) /* force-enable WAIT pin */ 621 #define TCIC_TEST_PCTR (1 << 8) /* program counter in read-test mode */ 622 #define TCIC_TEST_VCTL (1 << 9) /* force-enable power-supply controls */ 623 #define TCIC_TEST_EXTA (1 << 10) /* external access doesn't override 624 || internal decoding. 625 */ 626 #define TCIC_TEST_DRIVECDB (1 << 11) /* drive the card data bus all the time */ 627 #define TCIC_TEST_ISTP (1 << 12) /* turn off CCLK to the interrupt CSR */ 628 #define TCIC_TEST_BSTP (1 << 13) /* turn off BCLK internal to the chip */ 629 #define TCIC_TEST_CSTP (1 << 14) /* turn off CCLK except to int CSR */ 630 #define TCIC_TEST_DIAG (1 << 15) /* enable diagnostic read-back mode */ 631 632 /* Bits in the SCF1 register */ 633 #define TCIC_SCF1_IRQ_MASK (0xF) /* mask for this bit field */ 634 #define TCIC_SCF1_IRQOFF (0) /* disable */ 635 #define TCIC_SCF1_SIRQ (0x1) /* use SKTIRQ (2/N) */ 636 #define TCIC_SCF1_IRQ3 (0x3) /* use IRQ3 */ 637 #define TCIC_SCF1_IRQ4 (0x4) /* use IRQ4 */ 638 #define TCIC_SCF1_IRQ5 (0x5) /* use IRQ5 */ 639 #define TCIC_SCF1_IRQ6 (0x6) /* use IRQ6 */ 640 #define TCIC_SCF1_IRQ7 (0x7) /* use IRQ7 */ 641 #define TCIC_SCF1_IRQ9 (0x9) /* use IRQ9 */ 642 #define TCIC_SCF1_IRQ10 (0xA) /* use IRQ10 */ 643 #define TCIC_SCF1_IRQ11 (0xB) /* use IRQ11 */ 644 #define TCIC_SCF1_IRQ12 (0xC) /* use IRQ12 */ 645 #define TCIC_SCF1_IRQ14 (0xE) /* use IRQ14 */ 646 #define TCIC_SCF1_IRQ15 (0xF) /* use IRQ15 */ 647 648 /* XXX doc bug? -chb */ 649 #define TCIC_SCF1_IRQOD (1 << 4) 650 #define TCIC_SCF1_IRQOC (0) /* selected IRQ is 651 * open-collector, and active 652 * low; otherwise it's totem- 653 * pole and active hi. 654 */ 655 #define TCIC_SCF1_PCVT (1 << 5) /* convert level-mode IRQ 656 * to pulse mode, or stretch 657 * pulses from card. 658 */ 659 #define TCIC_SCF1_IRDY (1 << 6) /* interrupt from RDY (not 660 * from /IREQ). Used with 661 * ATA drives. 662 */ 663 #define TCIC_SCF1_ATA (1 << 7) /* Special ATA drive mode. 664 * CEL/H become CE1/2 in 665 * the IDE sense; CEL is 666 * activated for even window 667 * matches, and CEH for 668 * odd window matches. 669 */ 670 #define TCIC_SCF1_DMA_SHIFT 8 /* offset to DMA selects; */ 671 #define TCIC_SCF1_DMA_MASK (0x7 << IRSCFG_DMA_SHIFT) 672 673 #define TCIC_SCF1_DMAOFF (0 << IRSCFG_DMA_SHIFT) /* disable DMA */ 674 #define TCIC_SCF1_DREQ2 (2 << IRSCFG_DMA_SHIFT) /* enable DMA on DRQ2 */ 675 676 #define TCIC_SCF1_IOSTS (1 << 11) /* enable I/O status mode; 677 * allows CIORD/CIOWR to 678 * become low-Z. 679 */ 680 #define TCIC_SCF1_SPKR (1 << 12) /* enable SPKR output from 681 * this card 682 */ 683 #define TCIC_SCF1_FINPACK (1 << 13) /* force card input 684 * acknowledge during I/O 685 * cycles. Has no effect 686 * if no windows map to card 687 */ 688 #define TCIC_SCF1_DELWR (1 << 14) /* force -all- data to 689 * meet 60ns setup time 690 * ("DELay WRite") 691 */ 692 #define TCIC_SCF1_HD7IDE (1 << 15) /* Enable special IDE 693 * data register mode: odd 694 * byte addresses in odd 695 * I/O windows will not 696 * drive HD7. 697 */ 698 699 /* Bits in the scrf2 register */ 700 #define TCIC_SCF2_RI (1 << 0) /* enable RI pin from STSCHG 701 * (2/N) 702 `*/ 703 #define TCIC_SCF2_IDBR (1 << 1) /* force I/O data bus routing 704 * for this socket, regardless 705 * of cycle type. (2/N) 706 `*/ 707 #define TCIC_SCF2_MDBR (1 << 2) /* force memory window data 708 * bus routing for this 709 * socket, regardless of cycle 710 * type. (2/N) 711 */ 712 #define TCIC_SCF2_MLBAT1 (1 << 3) /* disable status change 713 * ints from LBAT1 (or 714 * "STSCHG" 715 */ 716 #define TCIC_SCF2_MLBAT2 (1 << 4) /* disable status change 717 * ints from LBAT2 (or "SPKR") 718 */ 719 #define TCIC_SCF2_MRDY (1 << 5) /* disable status change ints 720 * from RDY/BSY (or /IREQ). 721 * note that you get ints on 722 * both high- and low-going 723 * edges if this is enabled. 724 */ 725 #define TCIC_SCF2_MWP (1 << 6) /* disable status-change ints 726 * from WP (or /IOIS16). 727 * If you're using status 728 * change ints, you better set 729 * this once an I/O window is 730 * enabled, before accessing 731 * it. 732 */ 733 #define TCIC_SCF2_MCD (1 << 7) /* disable status-change ints 734 * from Card Detect. 735 */ 736 737 /* 738 * note that these bits match the top 5 bits of the socket status register 739 * in order and sense. 740 */ 741 #define TCIC_SCF2_DMASRC_MASK (0x3 << 8) /* mask for this bit field */ 742 /*-- DMA Source --*/ 743 #define TCIC_SCF2_DRQ_BVD2 (0x0 << 8) /* BVD2 */ 744 #define TCIC_SCF2_DRQ_IOIS16 (0x1 << 8) /* IOIS16 */ 745 #define TCIC_SCF2_DRQ_INPACK (0x2 << 8) /* INPACK */ 746 #define TCIC_SCF2_DRQ_FORCE (0x3 << 8) /* Force it */ 747 748 #define TCIC_SCFS2_RSVD (0xFC00) /* top 6 bits are RFU */ 749 750 /* Bits in the MBASE window registers */ 751 #define TCIC_MBASE_4K (1 << 14) /* window size is 4K */ 752 #define TCIC_MBASE_ADDR_MASK 0x0fff /* bits holding the address */ 753 754 /* Bits in the MMAP window registers */ 755 #define TCIC_MMAP_ATTR (1 << 15) /* map attr or common space */ 756 #define TCIC_MMAP_ADDR_MASK 0x3fff /* bits holding the address */ 757 758 /* Bits in the MCTL window registers */ 759 #define TCIC_MCTL_ENA (1 << 15) /* enable this window */ 760 #define TCIC_MCTL_SS_SHIFT 12 761 #define TCIC_MCTL_SS_MASK (7 << TCIC_MCTL_SS_SHIFT) /* which socket does this window map to */ 762 #define TCIC_MCTL_B8 (1 << 11) /* 8/16 bit access select */ 763 #define TCIC_MCTL_EDC (1 << 10) /* do EDC calc. on access */ 764 #define TCIC_MCTL_KE (1 << 9) /* accesses are cacheable */ 765 #define TCIC_MCTL_ACC (1 << 8) /* window has been accessed */ 766 #define TCIC_MCTL_WP (1 << 7) /* window is write protected */ 767 #define TCIC_MCTL_QUIET (1 << 6) /* enable quiet socket mode */ 768 #define TCIC_MCTL_WSCNT_MASK 0x0f /* wait state counter */ 769 770 /* Bits in the ICTL window registers */ 771 #define TCIC_ICTL_ENA (1 << 15) /* enable this windo */ 772 #define TCIC_ICTL_SS_SHIFT 12 773 #define TCIC_ICTL_SS_MASK (7 << TCIC_ICTL_SS_SHIFT) /* which socket does this window map to */ 774 #define TCIC_ICTL_AUTOSZ 0 /* auto size 8/16 bit acc. */ 775 #define TCIC_ICTL_B8 (1 << 11) /* all accesses 8 bit */ 776 #define TCIC_ICTL_B16 (1 << 10) /* all accesses 16 bit */ 777 #define TCIC_ICTL_ATA (3 << 10) /* special ATA mode */ 778 #define TCIC_ICTL_TINY (1 << 9) /* window size 1 byte */ 779 #define TCIC_ICTL_ACC (1 << 8) /* window has been accessed */ 780 #define TCIC_ICTL_1K (1 << 7) /* only 10 bits io decoding */ 781 #define TCIC_ICTL_QUIET (1 << 6) /* enable quiet socket mode */ 782 #define TCIC_ICTL_PASS16 (1 << 5) /* pass all 16 bits to card */ 783 #define TCIC_ICTL_WSCNT_MASK 0x0f /* wait state counter */ 784 785 /* Various validity tests */ 786 /* 787 * From Databook sample source: 788 * MODE_AR_SYSCFG must have, with j = ***read*** (***, R_AUX) 789 * and k = (j>>9)&7: 790 * if (k&4) k == 5 791 * And also: 792 * j&0x0f is none of 2, 8, 9, b, c, d, f 793 * if (j&8) must have (j&3 == 2) 794 * Can't have j==2 795 */ 796 #if 0 797 /* this is from the Databook sample code and apparently is wrong */ 798 #define INVALID_AR_SYSCFG(x) ((((x)&0x1000) && (((x)&0x0c00) != 0x0200)) \ 799 || (((((x)&0x08) == 0) || (((x)&0x03) == 2)) \ 800 && ((x) != 0x02))) 801 #else 802 #define INVALID_AR_SYSCFG(x) ((((x)&0x0800) && (((x)&0x0600) != 0x0100)) \ 803 || ((((((x)&0x08) == 0) && (((x)&0x03) == 2)) \ 804 || (((x)&0x03) == 2)) \ 805 && ((x) != 0x02))) 806 #endif 807 /* AR_ILOCK must have bits 6 and 7 the same: */ 808 #define INVALID_AR_ILOCK(x) (((x)&0xc0)==0 || (((x)&0xc0)==0xc0)) 809 810 /* AR_TEST has some reserved bits: */ 811 #define INVALID_AR_TEST(x) (((x)&0154) != 0) 812 813 814 #define TCIC_IO_WINS 2 815 #define TCIC_MAX_MEM_WINS 5 816 817 /* 818 * Memory window addresses refer to bits A23-A12 of the ISA system memory 819 * address. This is a shift of 12 bits. The LSB contains A19-A12, and the 820 * MSB contains A23-A20, plus some other bits. 821 */ 822 823 #define TCIC_MEM_SHIFT 12 824 #define TCIC_MEM_PAGESIZE (1<<TCIC_MEM_SHIFT) 825 826 #endif /* _TCIC2REG_H */
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