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sys/dev/ic/tcic2reg.h
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1 /* $OpenBSD: tcic2reg.h,v 1.5 2022/01/09 05:42:42 jsg Exp $ */ 2 /* $NetBSD: tcic2reg.h,v 1.1 1999/03/23 20:04:14 bad Exp $ */ 3 4 /*- 5 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Christoph Badura. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * All information is from the Databook DB86082 TCIC PC Card Controller for 35 * Notebook PCs -- Hardware Design Guide, March 22, 1994. 36 */ 37 38 #ifndef _TCIC2REG_H 39 #define _TCIC2REG_H 40 #define TCIC_IOSIZE 16 41 42 /* TCIC primary registers */ 43 #define TCIC_R_DATA 0 /* Data register, 16 bit */ 44 #define TCIC_R_ADDR 2 /* Address register, 32 bit */ 45 #define TCIC_R_ADDR2 (TCIC_R_ADDR+2) /* high word of addr. reg. */ 46 #define TCIC_R_SCTRL 6 /* Socket control reg., 8 bit */ 47 #define TCIC_R_SSTAT 7 /* Socket status reg., 8 bit */ 48 #define TCIC_R_MODE 8 /* Mode register, 8 bit */ 49 #define TCIC_R_PWR 9 /* Power control reg., 8 bit */ 50 #define TCIC_R_EDC 0xA /* Error detect code, 16 bit */ 51 #define TCIC_R_ICSR 0xC /* Interrupt ctrl/status, 8 bit */ 52 #define TCIC_R_IENA 0xD /* Interrupt enable, 8 bit */ 53 #define TCIC_R_AUX 0xE /* Auxiliary Register, 16 bit */ 54 55 /* 56 * TCIC auxiliary registers. 57 * These are all 16 bit registers. 58 * They are accessed by selecting the appropriate index in 59 * bits 7:5 of the mode register. 60 */ 61 #define TCIC_AR_MASK 0xe0 /* for masking the mode reg. */ 62 #define TCIC_AR_TCTL 0x00 /* timing control register */ 63 #define TCIC_AR_PCTL 0x20 /* programming pulse ctrl. */ 64 #define TCIC_AR_WCTL 0x40 /* wait state control */ 65 #define TCIC_AR_EXTERN 0x60 /* external access */ 66 #define TCIC_AR_PDATA 0x80 /* programming data */ 67 #define TCIC_AR_SYSCFG 0xA0 /* system configuration */ 68 #define TCIC_AR_ILOCK 0xC0 /* interlock control/status */ 69 #define TCIC_AR_TEST 0xE0 /* test */ 70 71 /* 72 * TCIC indirect registers. 73 * These are all 16 bit. 74 * They are accessed by selecting the appropriate address in 75 * bits 9:0 of the address register with indirect register access mode 76 * enabled. 77 */ 78 #define TCIC_WR_MEM_BASE 0x100 /* base address */ 79 #define TCIC_WR_MEM_SHFT 3 /* log2 size of one reg set */ 80 #define TCIC_WR_MEXT_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+0) 81 #define TCIC_WR_MBASE_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+2) 82 #define TCIC_WR_MMAP_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+4) 83 #define TCIC_WR_MCTL_N(n) ((TCIC_WR_MEM_BASE+((n)<<TCIC_WR_MEM_SHFT))+6) 84 85 #define TCIC_WR_IO_BASE 0x200 /* base address */ 86 #define TCIC_WR_IO_SHFT 2 /* log2 size of one reg set */ 87 #define TCIC_WR_IBASE_N(n) ((TCIC_WR_IO_BASE+((n)<<TCIC_WR_IO_SHFT))+0) 88 #define TCIC_WR_ICTL_N(n) ((TCIC_WR_IO_BASE+((n)<<TCIC_WR_IO_SHFT))+2) 89 90 #define TCIC_IR_SCF_BASE 0 /* base address */ 91 #define TCIC_IR_SCF_SHFT 3 /* log2 size of one reg set */ 92 #define TCIC_IR_SCF1_N(n) ((TCIC_IR_SCF_BASE+((n)<<TCIC_IR_SCF_SHFT))+0) 93 #define TCIC_IR_SCF2_N(n) ((TCIC_IR_SCF_BASE+((n)<<TCIC_IR_SCF_SHFT))+2) 94 95 96 /* Bits in the ADDR2 register */ 97 #define TCIC_SS_SHIFT 12 /* location of socket select bits */ 98 #define TCIC_SS_MASK (7<<(TCIC_SS_SHIFT)) /* socket select mask */ 99 100 #define TCIC_ADDR2_REG (1 << 15) /* select REG space */ 101 #define TCIC_ADDR2_SS_SHFT TCIC_SS_SHIFT /* select sockets the usual way */ 102 #define TCIC_ADDR2_SS_MASK TCIC_SS_MASK /* ditto */ 103 #define TCIC_ADDR2_INDREG (1 << 11) /* access indirect registers 104 * (not card data) 105 */ 106 #define TCIC_ADDR2_IO (1 << 10) /* select I/O cycles, readback 107 * card /IORD, /IOWR in diag- 108 * nostic mode. 109 */ 110 111 /* Bits in address register */ 112 #define TCIC_ADDR_REG (u_int32_t) TCIC_ADDR2_REG << 16) /* OR with this for REG space */ 113 #define TCIC_ADDR_SS_SHFT ((u_int32_t) TCIC_ADDR2_SS_SHFT + 16) 114 /* shift count, cast so that 115 * you'll get the right type 116 * if you use it but forget 117 * to cast the left arg. 118 */ 119 #define TCIC_ADDR_SS_MASK ((u_int32_t) TCIC_ADDR2_SS_MASK << 16) 120 #define TCIC_ADDR_INDREG ((u_int32_t) TCIC_ADDR2_INDREG << 16) 121 #define TCIC_ADDR_IO ((u_int32_t) TCIC_ADDR2_IO << 16) 122 123 #define TCIC_ADDR_SPACE_SIZE ((u_int32_t) 1 << 26) 124 #define TCIC_ADDR_MASK (ADDR_SPACE_SIZE - 1) 125 126 /* The following bits are defined in diagnostic mode */ 127 #define TCIC_ADDR_DIAG_NREG ((u_int32_t) 1U << 31) /* inverted! */ 128 #define TCIC_ADDR_DIAG_NCEH ((u_int32_t) 1U << 30) 129 #define TCIC_ADDR_DIAG_NCEL ((u_int32_t) 1U << 29) 130 #define TCIC_ADDR_DIAG_NCWR ((u_int32_t) 1U << 28) 131 #define TCIC_ADDR_DIAG_NCRD ((u_int32_t) 1U << 27) 132 #define TCIC_ADDR_DIAG_CRESET ((u_int32_t) 1U << 26) 133 134 /* Bits in socket control register */ 135 #define TCIC_SCTRL_ENA (1 << 0) /* enable access to card */ 136 #define TCIC_SCTRL_INCMODE (3 << 3) /* mask for increment mode: */ 137 #define TCIC_SCTRL_INCMODE_AUTO (3 << 3) /* auto-increment mode */ 138 #define TCIC_SCTRL_INCMODE_HOLD (0 << 3) /* byte hold mode */ 139 #define TCIC_SCTRL_INCMODE_WORD (1 << 3) /* word hold mode */ 140 #define TCIC_SCTRL_INCMODE_REG (2 << 3) /* reg-space increment mode */ 141 #define TCIC_SCTRL_EDCSUM (1 << 5) /* if set, use checksum (not CRC) */ 142 #define TCIC_SCTRL_RESET (1 << 7) /* internal software reset */ 143 #define TCIC_SCTRL_RSVD 0x46 /* reserved bits, MBZ */ 144 145 /* Bits in the socket status register */ 146 #define TCIC_SSTAT_6US (1<<0) /* 6 usec have elapsed */ 147 #define TCIC_SSTAT_10US (1<<1) /* 10 usec have elapsed */ 148 #define TCIC_SSTAT_PROGTIME (1<<2) /* programming pulse timeout */ 149 #define TCIC_SSTAT_LBAT1 (1<<3) /* low battery 1 */ 150 #define TCIC_SSTAT_LBAT2 (1<<4) /* low battery 2 */ 151 #define TCIC_SSTAT_BATOK (0<<3) /* battery is OK */ 152 #define TCIC_SSTAT_BATBAD1 (1<<3) /* battery is low */ 153 #define TCIC_SSTAT_BATLO (2<<3) /* battery is getting low */ 154 #define TCIC_SSTAT_BATBAD2 (3<<3) /* battery is low */ 155 #define TCIC_SSTAT_RDY (1<<5) /* card is ready (not busy) */ 156 #define TCIC_SSTAT_WP (1<<6) /* card is write-protected */ 157 #define TCIC_SSTAT_CD (1<<7) /* card present */ 158 #define TCIC_SSTAT_STAT_MASK 0xf8 159 160 /* Mode register contents (R_MODE) */ 161 #define TCIC_MODE_PGMMASK (0x1F) /* the programming mode bits */ 162 #define TCIC_MODE_NORMAL (0) /* normal mode */ 163 #define TCIC_MODE_PGMWR (1 << 0) /* assert /WR */ 164 #define TCIC_MODE_PGMRD (1 << 1) /* assert /RD */ 165 #define TCIC_MODE_PGMCE (1 << 2) /* assert /CEx */ 166 #define TCIC_MODE_PGMDBW (1 << 3) /* databus in write mode */ 167 #define TCIC_MODE_PGMWORD (1 << 4) /* word programming mode */ 168 169 /* Power control register contents (R_PWR) */ 170 #define TCIC_PWR_VCC_SHFT (0) /* the VCC ctl shift */ 171 #define TCIC_PWR_VCC_MASK (3 << TCIC_PWR_VCC_SHFT) 172 173 #define TCIC_PWR_VPP_SHFT (3) /* the VPP ctl shift */ 174 #define TCIC_PWR_VPP_MASK (3 << TCIC_PWR_VPP_SHFT) 175 #define TCIC_PWR_ENA (1 << 5) /* on 084, successors, this 176 * must be set to turn on 177 * power. 178 */ 179 #define TCIC_PWR_VCC5V (1 << 2) /* enable +5 (not +3) */ 180 #if 0 181 #define TCIC_PWR_VOFF_POFF (0) /* turn off VCC, VPP */ 182 #define TCIC_PWR_VON_PVCC (1) /* turn on VCC, VPP=VCC */ 183 #define TCIC_PWR_VON_PVPP (2) /* turn on VCC, VPP=12V */ 184 #define TCIC_PWR_VON_POFF (3) /* turn on VCC, VPP=0V */ 185 #endif 186 #define TCIC_PWR_VCC_N(n) (1<<((n))) /* VCCSEL for socket n */ 187 #define TCIC_PWR_VPP_N(n) (1<<(3+(n))) /* VPPSEL for socket n */ 188 189 #define TCIC_PWR_CLIMENA (1 << 6) /* the current-limit enable */ 190 #define TCIC_PWR_CLIMSTAT (1 << 7) /* current limit sense (r/o) */ 191 192 /* Bits in the icsr register. */ 193 #define TCIC_ICSR_IOCHK (1<<7) /* I/O check */ 194 #define TCIC_ICSR_CDCHG (1<<6) /* card status change, see SSTAT */ 195 #define TCIC_ICSR_ERR (1<<5) /* error condition */ 196 #define TCIC_ICSR_PROGTIME (1<<4) /* program timer ding */ 197 #define TCIC_ICSR_ILOCK (1<<3) /* interlock change */ 198 #define TCIC_ICSR_STOPCPU (1<<2) /* Stop CPU was asserted */ 199 #define TCIC_ICSR_SET (1<<1) /* (w/o) enable writes that set bits */ 200 #define TCIC_ICSR_CLEAR (1<<0) /* (w/o) enable writes that clear */ 201 #define TCIC_ICSR_JAM (TCIC_ICSR_SET|TCIC_ICSR_CLEAR) 202 /* jam value into ICSR */ 203 204 /* bits in the interrupt enable register */ 205 #define TCIC_IENA_CDCHG (1 << 6) /* enable INT when ICSR_CDCHG is set */ 206 #define TCIC_IENA_ERR (1 << 5) /* enable INT when ICSR_ERR is set */ 207 #define TCIC_IENA_PROGTIME (1 << 4) /* enable INT when ICSR_PROGTIME " */ 208 #define TCIC_IENA_ILOCK (1 << 3) /* enable INT when ICSR_ILOCK is set */ 209 #define TCIC_IENA_CFG_MASK (3 << 0) /* select the bits for IRQ config: */ 210 #define TCIC_IENA_CFG_OFF (0 << 0) /* IRQ is high-impedance */ 211 #define TCIC_IENA_CFG_OD (1 << 0) /* IRQ is active low, open drain. */ 212 #define TCIC_IENA_CFG_LOW (2 << 0) /* IRQ is active low, totem pole */ 213 #define TCIC_IENA_CFG_HIGH (3 << 0) /* IRQ is active high, totem pole */ 214 #define TCIC_IENA_RSVD 0x84 /* reserved bits, MBZ */ 215 216 217 /* 218 * Bits in the auxiliary registers 219 */ 220 221 /* Bits in the timing control register (AR_TCTL) */ 222 #define TCIC_TCTL_6US_SHFT (0) /* the shift count for the 6 us ctr */ 223 #define TCIC_TCTL_10US_SHFT (8) /* the shift count for the 10 us ctr */ 224 #define TCIC_TCTL_6US_MASK (0xFF << TCIC_TCTL_6US_SHFT) 225 #define TCIC_TCTL_10US_MASK (0xFF << TCIC_TCTL_10US_SHFT) 226 227 #define TCIC_R_TCTL_6US (TCIC_R_AUX + 0) /* the byte access handle */ 228 #define TCIC_R_TCTL_10US (TCIC_R_AUX + 1) /* the byte access handle */ 229 230 /* Bits in the programming pulse register (AR_PCTL) */ 231 #define TCIC_R_PULSE_LO (TCIC_R_AUX + 0) 232 #define TCIC_R_PULSE_HI (TCIC_R_AUX + 1) 233 234 /* Bits in the wait state control register (AR_WCTL) */ 235 #define TCIC_WAIT_COUNT_MASK (0x1F) /* the count of 1/2 wait states */ 236 #define TCIC_WAIT_COUNT_SHFT (0) /* the wait-count shift */ 237 #define TCIC_WAIT_SYNC (1 << 5) /* set for synch, clear for asynch cycles */ 238 #define TCIC_WAIT_ASYNC (0) 239 240 #define TCIC_WAIT_SENSE (1 << 6) /* select rising (1) or falling (0) 241 * edge of wait clock as reference 242 * edge. 243 */ 244 #define TCIC_WAIT_SRC (1 << 7) /* select constant clock (0) or bus 245 * clock (1) as the timing source 246 */ 247 248 /* Some derived constants */ 249 #define TCIC_WAIT_BCLK (1 * TCIC_WAIT_SRC) 250 #define TCIC_WAIT_CCLK (0 * TCIC_WAIT_SRC) 251 #define TCIC_WAIT_RISING (1 * TCIC_WAIT_SENSE) 252 #define TCIC_WAIT_FALLING (0 * TCIC_WAIT_SENSE) 253 254 /* high byte */ 255 #define TCIC_WCTL_WR (1 << 8) /* control: pulse write */ 256 #define TCIC_WCTL_RD (1 << 9) /* control: pulse read */ 257 #define TCIC_WCTL_CE (1 << 10) /* control: pulse chip ena */ 258 #define TCIC_WCTL_LLBAT1 (1 << 11) /* status: latched LBAT1 */ 259 #define TCIC_WCTL_LLBAT2 (1 << 12) /* status: latched LBAT2 */ 260 #define TCIC_WCTL_LRDY (1 << 13) /* status: latched RDY */ 261 #define TCIC_WCTL_LWP (1 << 14) /* status: latched WP */ 262 #define TCIC_WCTL_LCD (1 << 15) /* status: latched CD */ 263 264 /* The same thing, from a byte perspective */ 265 #define TCIC_R_WCTL_WAIT (TCIC_R_AUX + 0) /* the wait state control byte */ 266 #define TCIC_R_WCTL_XCSR (TCIC_R_AUX + 1) /* extended control/status */ 267 268 #define TCIC_XCSR_WR (1 << 0) /* control: pulse write */ 269 #define TCIC_XCSR_RD (1 << 1) /* control: pulse read */ 270 #define TCIC_XCSR_CE (1 << 2) /* control: pulse chip ena */ 271 #define TCIC_XCSR_LLBAT1 (1 << 3) /* status: latched LBAT1 */ 272 #define TCIC_XCSR_LLBAT2 (1 << 4) /* status: latched LBAT2 */ 273 #define TCIC_XCSR_LRDY (1 << 5) /* status: latched RDY */ 274 #define TCIC_XCSR_LWP (1 << 6) /* status: latched WP */ 275 #define TCIC_XCSR_LCD (1 << 7) /* status: latched CD */ 276 #define TCIC_XCSR_STAT_MASK 0xf8 277 278 /* Bits in the programming data register (AR_PDATA) */ 279 #define TCIC_R_PDATA_LO (TCIC_R_AUX + 0) 280 #define TCIC_R_PDATA_HI (TCIC_R_AUX + 1) 281 282 /* Bits in the system configuration register (AR_SYSCFG) */ 283 /* 284 * The bottom four bits specify the steering of the socket IRQ. On 285 * the 2N, the socket IRQ is (by default) pointed at the dedicated 286 * pin. 287 */ 288 #define TCIC_SYSCFG_IRQ_MASK (0xF) /* mask for this bit field. */ 289 #define TCIC_SYSCFG_SSIRQDFLT (0) /* default: use SKTIRQ (2/N) 290 * disable (2/P) 291 */ 292 #define TCIC_SYSCFG_SSIRQ (0x1) /* use SKTIRQ (explicit) (2/N) 293 * do not use (2/P) 294 */ 295 #define TCIC_SYSCFG_SIRQ3 (0x3) /* use IRQ3 */ 296 #define TCIC_SYSCFG_SIRQ4 (0x4) /* use IRQ4 */ 297 #define TCIC_SYSCFG_SIRQ5 (0x5) /* use IRQ5 (2/N) */ 298 #define TCIC_SYSCFG_SIRQ6 (0x6) /* use IRQ6 (2/N) */ 299 #define TCIC_SYSCFG_SIRQ7 (0x7) /* use IRQ7 (2/N) */ 300 #define TCIC_SYSCFG_SIRQ10 (0xA) /* use IRQ10 */ 301 #define TCIC_SYSCFG_SIRQ14 (0xE) /* use IRQ14 */ 302 303 #define TCIC_SYSCFG_MCSFULL (1 << 4) 304 /* 305 * If set, use full address (a[12:23]) for MCS16 generation. 306 * If clear, run in ISA-compatible mode (only using a[17:23]). 307 * With many chip sets, the TCIC-2/N's timing will will allow full 308 * address decoding to be used rather than limiting us to LA[17:23]; 309 * thus we can get around the ISA spec which limits the granularity 310 * of bus sizing to 128K blocks. 311 */ 312 #define TCIC_SYSCFG_IO1723 (1 << 5) 313 /* 314 * Flag indicating that LA[17:23] can be trusted to be zero during a 315 * true I/O cycle. Setting this bit will allow us to reduce power 316 * consumption further by eliminating I/O address broadcasts for 317 * memory cycles. 318 * 319 * Unfortunately, you cannot trust LA[17:23] to be zero on all systems, 320 * because the ISA specs do not require that LA[17:23] be zero when an 321 * alternate bus master runs an I/O cycle. However, on a palmtop or 322 * notebook, it is a good guess. 323 */ 324 325 #define TCIC_SYSCFG_MCSXB (1 << 6) 326 /* 327 * If set, assume presence of an external buffer for MCS16: operate 328 * the driver as a totem-pole output. 329 * 330 * If clear, run in pseudo-ISA mode; output is open drain. But note 331 * that on the 082 the output buffers cannot drive a 300-ohm 332 * load. 333 */ 334 #define TCIC_SYSCFG_ICSXB (1 << 7) 335 /* 336 * If set, assume presence of an external buffer for IOCS16*; operate 337 * the buffer as a totem-pole output. 338 * 339 * If clear, run in pseudo-ISA mode; output is open drain. But note 340 * that on the 082 the output buffers cannot drive a 300-ohm 341 * load. 342 */ 343 #define TCIC_SYSCFG_NOPDN (1 << 8) 344 /* 345 * If set, disable the auto power-down sequencing. The chip will 346 * run card cycles somewhat more quickly (though perhaps not 347 * significantly so); but it will dissipate significantly more power. 348 * 349 * If clear, the low-power operating modes are enabled. This 350 * causes the part to go into low-power mode automatically at 351 * system reset. 352 */ 353 #define TCIC_SYSCFG_MPSEL_SHFT (9) 354 #define TCIC_SYSCFG_MPSEL_MASK (7 << 9) 355 /* 356 * This field controls the operation of the multipurpose pin on the 357 * 86082. It has the following codes: 358 */ 359 #define TCIC_SYSCFG_MPSEL_OFF (0 << TCIC_SYSCFG_MPSEL_SHFT) 360 /* 361 * This is the reset state; it indicates that the Multi-purpose 362 * pin is not used. The pin will be held in a high-impedance 363 * state. It can be read by monitoring SYSCFG_MPSENSE. 364 */ 365 #define TCIC_SYSCFG_MPSEL_NEEDCLK (1 << TCIC_SYSCFG_MPSEL_SHFT) 366 /* 367 * NMULTI is an output. 368 * External indication that CCLK or BCLK are needed in order 369 * to complete an internal operation. External logic can use 370 * this to control the clocks coming to the chip. 371 */ 372 #define TCIC_SYSCFG_MPSEL_MIO (2 << TCIC_SYSCFG_MPSEL_SHFT) 373 /* 374 * NMULTI is an input; it is an unambiguous M/IO signal, issued 375 * with timing similar to the LA[] lines. 376 */ 377 #define TCIC_SYSCFG_MPSEL_EXTSEL (3 << TCIC_SYSCFG_MPSEL_SHFT) 378 /* 379 * NMULTI is an output; it is the external register select 380 * pulse, generated whenever software attempts to access 381 * aux register AR_EXTRN. Of course, the 86082 will ignore 382 * writes to AR_EXTRN, and will float the data bus if 383 * the CPU reads from AR_EXTRN. 384 */ 385 386 /* (4 << TCIC_SYSCFG_MPSEL_SHFT) is reserved */ 387 388 #define TCIC_SYSCFG_MPSEL_RI (5 << TCIC_SYSCFG_MPSEL_SHFT) 389 /* 390 * NMULTI is an output; it indicates a RI (active-going) 391 * transition has occurred lately on a an appropriately- 392 * configured socket. The output is active low. 393 */ 394 /* 395 * Codes 4, 6 and 7 are reserved, and must NOT be output. It is 396 * indeed possibly hazardous to your system to encode values in 397 * this field that do not match your hardware! 398 */ 399 400 /* 1 << 12 reserved */ 401 402 #define TCIC_SYSCFG_MPSENSE (1 << 13) 403 /* 404 * This bit, when read, returns the sense of the multi-purpose pin. 405 */ 406 407 #define TCIC_SYSCFG_AUTOBUSY (1 << 14) 408 /* 409 * This bit, when set, causes the busy led to be gated with the 410 * SYSCFG_ACC bit. When clear, the busy led reflects whether the 411 * socket is actually enabled. If AUTOBUSY is set and ACC is clear, 412 * then the busy light will be off, even if a socket is enabled. 413 * If AUTOBUSY is clear, then the busy light will be on if either 414 * socket is enabled. 415 * 416 * Note, that when in a programming mode, you should either clear this 417 * bit (causing the busy light to be on whenever the socket is enabled) 418 * or set both this bit and the ACC bit (causing the light to be on 419 * all the time). 420 * 421 * On the '084 and '184, this bit is per-socket. 422 */ 423 424 #define TCIC_SYSCFG_ACC (1<<15) 425 /* 426 * This bit will be set automatically by the hardware whenever the CPU 427 * accesses data on a card. It can be cleared under software control. 428 * 429 * In AUTOBUSY mode, it has the additional effect of turning on the 430 * busy light. 431 * 432 * Since we'll tristate the command lines as the card is going out of 433 * the socket, and since the shared lines idle low, there's no real 434 * danger if the busy light is off even though the socket is enabled. 435 * 436 * On the '084 and '184, this bit is per-socket. 437 */ 438 439 440 /* Bits in the ilock aux. register. */ 441 #define TCIC_ILOCK_OUT (1 << 0) /* interlock output 442 * per-socket on x84 443 */ 444 #define TCIC_ILOCK_SENSE (1 << 1) /* (r/o) interlock sense 445 * 0 -> /cilock not asserted; 446 * 1 -> /cilock is asserted. 447 * per-socket on x84. 448 */ 449 #define TCIC_ILOCK_CRESET (1 << 2) /* card reset output level(S) */ 450 #define TCIC_ILOCK_CRESENA (1 << 3) /* enable card reset output (S) */ 451 #define TCIC_ILOCK_CWAIT (1 << 4) /* enable card wait (S) */ 452 #define TCIC_ILOCK_CWAITSNS (1 << 5) /* (r/o) sense current state of wait 453 * 0 -> /cwait not asserted; 454 * 1 -> /cwait is asserted 455 * (S) 456 */ 457 /* The shift count & mask for the hold-time control */ 458 #define TCIC_ILOCK_HOLD_SHIFT 6 /* shift count for the hold-time ctl (G) */ 459 #define TCIC_ILOCK_HOLD_MASK (3 << TCIC_ILOCK_HOLD_SHIFT) 460 461 /* 462 * Quick hold mode waits until we observe that the strobe is high, 463 * guaranteeing 10ns or so of hold time. 464 */ 465 #define TCIC_ILOCK_HOLD_QUICK (0 << TCIC_ILOCK_HOLD_SHIFT) 466 467 /* 468 * CCLK hold mode waits (asynchronously) for an edge on CCLK. Minimum is 1 469 * CCLK + epsilon; maximum is 2 CCLKs + epsilon. 470 * 471 * for the 86081 & '82, this mode enables the multi-step 472 * sequencer that generates setup and hold times based on CCLK. This 473 * is the recommended mode of operation for the '81 and '82. 474 * 475 */ 476 #define TCIC_ILOCK_HOLD_CCLK (3 << TCIC_ILOCK_HOLD_SHIFT) 477 478 /* The following bits are only present on the x84 and later parts */ 479 #define TCIC_ILOCK_INPACK (1 << 11) /* (r/o, S) this bit is a diagnostic 480 * read-back for card input 481 * acknowledge. 482 * The sense is inverted from 483 * the level at the pin. 484 */ 485 #define TCIC_ILOCK_CP0 (1 << 12) /* (r/o, S) this bit is a diagnostic 486 * monitor for card present pin 0. 487 * The sense is inverted from the 488 * level at the pin. 489 */ 490 #define TCIC_ILOCK_CP1 (1 << 13) /* (r/o, S) this bit is a diagnostic 491 * monitor for card present pin 1. 492 * The sense is inverted from the 493 * level at the pin. 494 */ 495 #define TCIC_ILOCK_VS1 (1 << 14) /* (r/o, S) this bit is the primary 496 * monitor for Card Voltage Sense 497 * pin 1. 498 * The sense is inverted from the 499 * level at the pin. 500 */ 501 #define TCIC_ILOCK_VS2 (1 << 15) /* (r/o, S) this bit is the primary 502 * monitor for Card Voltage Sense 503 * pin 2. 504 * The sense is inverted from the 505 * level at the pin. 506 */ 507 /* 508 * Silicon Version Register 509 * 510 * In diagnostic mode, the high byte of the interlock register is defined 511 * as the silicon identity byte. 512 * 513 * In order to read this byte, the chip must be placed in diagnostic 514 * mode by setting bit 15 of the TESTDIAG register. (This may or may 515 * not be enforced by the silicon.) 516 * 517 * The layout is: 518 * 519 * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 520 * m <-------ID-------> <----ILOCK----> 521 * 522 * The fields are: 523 * 524 * m Always reset. 525 * 526 * ID This field is one of the following: 527 * 528 * 0x02 the db86082 529 * 0x03 the db86082a 530 * 0x04 the db86084 531 * 0x05 the DB86072ES, (Engineering Sample) 532 * 0x07 the db86082bES, (Engineering Sample) 533 * 0x08 the db86084a 534 * 0x14 the DB86184 535 * 0x15 the DB86072, (Production) 536 * 0x17 the db86082b, (Production) 537 */ 538 539 /* 540 * Defines for Chip IDs described above. 541 * 542 * Use the following convention for defining TCIC_CHIPID_DBxxxxxY: 543 * 544 * TCIC_CHIPID_DBxxxxx_1 The First step of chip. 545 * TCIC_CHIPID_DBxxxxxA The Second step of chip. 546 * TCIC_CHIPID_DBxxxxxB The Third step of chip. 547 * TCIC_CHIPID_DBxxxxx... The ... step of chip. 548 * 549 * TCIC_CHIPID_DBxxxxx"step of chip"_ES An Engineering Sample of chip. 550 * 551 */ 552 #define TCIC_CHIPID_DB86082_1 (0x02) 553 #define TCIC_CHIPID_DB86082A (0x03) 554 #define TCIC_CHIPID_DB86082B_ES (0x07) 555 #define TCIC_CHIPID_DB86082B (0x17) 556 557 #define TCIC_CHIPID_DB86084_1 (0x04) 558 #define TCIC_CHIPID_DB86084A (0x08) 559 560 #define TCIC_CHIPID_DB86184_1 (0x14) 561 562 #define TCIC_CHIPID_DB86072_1_ES (0x05) 563 #define TCIC_CHIPID_DB86072_1 (0x15) 564 565 566 /* the high order bits (in diag mode) give the chip version */ 567 #define TCIC_R_ILOCK_ID (TCIC_R_AUX + 1) 568 569 #define TCIC_ILOCKTEST_ID_SHFT 8 /* the shift count */ 570 #define TCIC_ILOCKTEST_ID_MASK (0x7F << TCIC_ILOCKTEST_ID_SHFT) 571 /* the mask for the field */ 572 /* 573 * Use the following convention for defining TCIC_ILOCKTEST_DBxxxxxY: 574 * 575 * TCIC_ILOCKTEST_DBxxxxx_1 The First step of chip. 576 * TCIC_ILOCKTEST_DBxxxxxA The Second step of chip. 577 * TCIC_ILOCKTEST_DBxxxxxB The Third step of chip. 578 * TCIC_ILOCKTEST_DBxxxxx... The ... step of chip. 579 * 580 * TCIC_ILOCKTEST_DBxxxxx"step of chip"_ES An Engineering Sample of chip. 581 * 582 */ 583 #define TCIC_ILOCKTEST_TCIC2N_1 ((TCIC_CHIPID_DB86082_1) << TCIC_ILOCKTEST_ID_SHFT) 584 #define TCIC_ILOCKTEST_DB86082_1 TCIC_ILOCKTEST_TCIC2N_1 585 #define TCIC_ILOCKTEST_TCIC2N_2 ((TCIC_CHIPID_DB86082A) << TCIC_ILOCKTEST_ID_SHFT) 586 #define TCIC_ILOCKTEST_DB86082A TCIC_ILOCKTEST_TCIC2N_2 587 #define TCIC_ILOCKTEST_TCIC2N_3 ((TCIC_CHIPID_DB86082B_ES) << TCIC_ILOCKTEST_ID_SHFT) 588 #define TCIC_ILOCKTEST_DB86082B_ES TCIC_ILOCKTEST_TCIC2N_3 589 590 #define TCIC_ILOCKTEST_DB86082B ((TCIC_CHIPID_DB86082B) << TCIC_ILOCKTEST_ID_SHFT) 591 592 #define TCIC_ILOCKTEST_DB86084_1 ((TCIC_CHIPID_DB86084_1) << TCIC_ILOCKTEST_ID_SHFT) 593 #define TCIC_ILOCKTEST_DB86084A ((TCIC_CHIPID_DB86084A) << TCIC_ILOCKTEST_ID_SHFT) 594 595 #define TCIC_ILOCKTEST_DB86184_1 ((TCIC_CHIPID_DB86184_1) << TCIC_ILOCKTEST_ID_SHFT) 596 597 #define TCIC_ILOCKTEST_DB86072_1 ((TCIC_CHIPID_DB86072_1) << TCIC_ILOCKTEST_ID_SHFT) 598 #define TCIC_ILOCKTEST_DB86072_1_ES ((TCIC_CHIPID_DB86072_1_ES) << TCIC_ILOCKTEST_ID_SHFT) 599 600 601 /* Bits in the test control register (AR_TEST) */ 602 #define TCIC_R_TEST (TCIC_R_AUX + 0) 603 #define TCIC_TEST_AEN (1 << 0) /* force card AEN */ 604 #define TCIC_TEST_CEN (1 << 1) /* force card CEN */ 605 #define TCIC_TEST_CTR (1 << 2) /* test programming pulse, address ctrs */ 606 #define TCIC_TEST_ENA (1 << 3) /* force card-present (for test), and 607 * special VPP test mode 608 */ 609 #define TCIC_TEST_IO (1 << 4) /* feed back some I/O signals 610 * internally. 611 */ 612 #define TCIC_TEST_OUT1 (1 << 5) /* force special address output mode */ 613 #define TCIC_TEST_ZPB (1 << 6) /* enter ZPB test mode */ 614 #define TCIC_TEST_WAIT (1 << 7) /* force-enable WAIT pin */ 615 #define TCIC_TEST_PCTR (1 << 8) /* program counter in read-test mode */ 616 #define TCIC_TEST_VCTL (1 << 9) /* force-enable power-supply controls */ 617 #define TCIC_TEST_EXTA (1 << 10) /* external access doesn't override 618 || internal decoding. 619 */ 620 #define TCIC_TEST_DRIVECDB (1 << 11) /* drive the card data bus all the time */ 621 #define TCIC_TEST_ISTP (1 << 12) /* turn off CCLK to the interrupt CSR */ 622 #define TCIC_TEST_BSTP (1 << 13) /* turn off BCLK internal to the chip */ 623 #define TCIC_TEST_CSTP (1 << 14) /* turn off CCLK except to int CSR */ 624 #define TCIC_TEST_DIAG (1 << 15) /* enable diagnostic read-back mode */ 625 626 /* Bits in the SCF1 register */ 627 #define TCIC_SCF1_IRQ_MASK (0xF) /* mask for this bit field */ 628 #define TCIC_SCF1_IRQOFF (0) /* disable */ 629 #define TCIC_SCF1_SIRQ (0x1) /* use SKTIRQ (2/N) */ 630 #define TCIC_SCF1_IRQ3 (0x3) /* use IRQ3 */ 631 #define TCIC_SCF1_IRQ4 (0x4) /* use IRQ4 */ 632 #define TCIC_SCF1_IRQ5 (0x5) /* use IRQ5 */ 633 #define TCIC_SCF1_IRQ6 (0x6) /* use IRQ6 */ 634 #define TCIC_SCF1_IRQ7 (0x7) /* use IRQ7 */ 635 #define TCIC_SCF1_IRQ9 (0x9) /* use IRQ9 */ 636 #define TCIC_SCF1_IRQ10 (0xA) /* use IRQ10 */ 637 #define TCIC_SCF1_IRQ11 (0xB) /* use IRQ11 */ 638 #define TCIC_SCF1_IRQ12 (0xC) /* use IRQ12 */ 639 #define TCIC_SCF1_IRQ14 (0xE) /* use IRQ14 */ 640 #define TCIC_SCF1_IRQ15 (0xF) /* use IRQ15 */ 641 642 /* XXX doc bug? -chb */ 643 #define TCIC_SCF1_IRQOD (1 << 4) 644 #define TCIC_SCF1_IRQOC (0) /* selected IRQ is 645 * open-collector, and active 646 * low; otherwise it's totem- 647 * pole and active hi. 648 */ 649 #define TCIC_SCF1_PCVT (1 << 5) /* convert level-mode IRQ 650 * to pulse mode, or stretch 651 * pulses from card. 652 */ 653 #define TCIC_SCF1_IRDY (1 << 6) /* interrupt from RDY (not 654 * from /IREQ). Used with 655 * ATA drives. 656 */ 657 #define TCIC_SCF1_ATA (1 << 7) /* Special ATA drive mode. 658 * CEL/H become CE1/2 in 659 * the IDE sense; CEL is 660 * activated for even window 661 * matches, and CEH for 662 * odd window matches. 663 */ 664 #define TCIC_SCF1_DMA_SHIFT 8 /* offset to DMA selects; */ 665 #define TCIC_SCF1_DMA_MASK (0x7 << IRSCFG_DMA_SHIFT) 666 667 #define TCIC_SCF1_DMAOFF (0 << IRSCFG_DMA_SHIFT) /* disable DMA */ 668 #define TCIC_SCF1_DREQ2 (2 << IRSCFG_DMA_SHIFT) /* enable DMA on DRQ2 */ 669 670 #define TCIC_SCF1_IOSTS (1 << 11) /* enable I/O status mode; 671 * allows CIORD/CIOWR to 672 * become low-Z. 673 */ 674 #define TCIC_SCF1_SPKR (1 << 12) /* enable SPKR output from 675 * this card 676 */ 677 #define TCIC_SCF1_FINPACK (1 << 13) /* force card input 678 * acknowledge during I/O 679 * cycles. Has no effect 680 * if no windows map to card 681 */ 682 #define TCIC_SCF1_DELWR (1 << 14) /* force -all- data to 683 * meet 60ns setup time 684 * ("DELay WRite") 685 */ 686 #define TCIC_SCF1_HD7IDE (1 << 15) /* Enable special IDE 687 * data register mode: odd 688 * byte addresses in odd 689 * I/O windows will not 690 * drive HD7. 691 */ 692 693 /* Bits in the scrf2 register */ 694 #define TCIC_SCF2_RI (1 << 0) /* enable RI pin from STSCHG 695 * (2/N) 696 `*/ 697 #define TCIC_SCF2_IDBR (1 << 1) /* force I/O data bus routing 698 * for this socket, regardless 699 * of cycle type. (2/N) 700 `*/ 701 #define TCIC_SCF2_MDBR (1 << 2) /* force memory window data 702 * bus routing for this 703 * socket, regardless of cycle 704 * type. (2/N) 705 */ 706 #define TCIC_SCF2_MLBAT1 (1 << 3) /* disable status change 707 * ints from LBAT1 (or 708 * "STSCHG" 709 */ 710 #define TCIC_SCF2_MLBAT2 (1 << 4) /* disable status change 711 * ints from LBAT2 (or "SPKR") 712 */ 713 #define TCIC_SCF2_MRDY (1 << 5) /* disable status change ints 714 * from RDY/BSY (or /IREQ). 715 * note that you get ints on 716 * both high- and low-going 717 * edges if this is enabled. 718 */ 719 #define TCIC_SCF2_MWP (1 << 6) /* disable status-change ints 720 * from WP (or /IOIS16). 721 * If you're using status 722 * change ints, you better set 723 * this once an I/O window is 724 * enabled, before accessing 725 * it. 726 */ 727 #define TCIC_SCF2_MCD (1 << 7) /* disable status-change ints 728 * from Card Detect. 729 */ 730 731 /* 732 * note that these bits match the top 5 bits of the socket status register 733 * in order and sense. 734 */ 735 #define TCIC_SCF2_DMASRC_MASK (0x3 << 8) /* mask for this bit field */ 736 /*-- DMA Source --*/ 737 #define TCIC_SCF2_DRQ_BVD2 (0x0 << 8) /* BVD2 */ 738 #define TCIC_SCF2_DRQ_IOIS16 (0x1 << 8) /* IOIS16 */ 739 #define TCIC_SCF2_DRQ_INPACK (0x2 << 8) /* INPACK */ 740 #define TCIC_SCF2_DRQ_FORCE (0x3 << 8) /* Force it */ 741 742 #define TCIC_SCFS2_RSVD (0xFC00) /* top 6 bits are RFU */ 743 744 /* Bits in the MBASE window registers */ 745 #define TCIC_MBASE_4K (1 << 14) /* window size is 4K */ 746 #define TCIC_MBASE_ADDR_MASK 0x0fff /* bits holding the address */ 747 748 /* Bits in the MMAP window registers */ 749 #define TCIC_MMAP_ATTR (1 << 15) /* map attr or common space */ 750 #define TCIC_MMAP_ADDR_MASK 0x3fff /* bits holding the address */ 751 752 /* Bits in the MCTL window registers */ 753 #define TCIC_MCTL_ENA (1 << 15) /* enable this window */ 754 #define TCIC_MCTL_SS_SHIFT 12 755 #define TCIC_MCTL_SS_MASK (7 << TCIC_MCTL_SS_SHIFT) /* which socket does this window map to */ 756 #define TCIC_MCTL_B8 (1 << 11) /* 8/16 bit access select */ 757 #define TCIC_MCTL_EDC (1 << 10) /* do EDC calc. on access */ 758 #define TCIC_MCTL_KE (1 << 9) /* accesses are cacheable */ 759 #define TCIC_MCTL_ACC (1 << 8) /* window has been accessed */ 760 #define TCIC_MCTL_WP (1 << 7) /* window is write protected */ 761 #define TCIC_MCTL_QUIET (1 << 6) /* enable quiet socket mode */ 762 #define TCIC_MCTL_WSCNT_MASK 0x0f /* wait state counter */ 763 764 /* Bits in the ICTL window registers */ 765 #define TCIC_ICTL_ENA (1 << 15) /* enable this window */ 766 #define TCIC_ICTL_SS_SHIFT 12 767 #define TCIC_ICTL_SS_MASK (7 << TCIC_ICTL_SS_SHIFT) /* which socket does this window map to */ 768 #define TCIC_ICTL_AUTOSZ 0 /* auto size 8/16 bit acc. */ 769 #define TCIC_ICTL_B8 (1 << 11) /* all accesses 8 bit */ 770 #define TCIC_ICTL_B16 (1 << 10) /* all accesses 16 bit */ 771 #define TCIC_ICTL_ATA (3 << 10) /* special ATA mode */ 772 #define TCIC_ICTL_TINY (1 << 9) /* window size 1 byte */ 773 #define TCIC_ICTL_ACC (1 << 8) /* window has been accessed */ 774 #define TCIC_ICTL_1K (1 << 7) /* only 10 bits io decoding */ 775 #define TCIC_ICTL_QUIET (1 << 6) /* enable quiet socket mode */ 776 #define TCIC_ICTL_PASS16 (1 << 5) /* pass all 16 bits to card */ 777 #define TCIC_ICTL_WSCNT_MASK 0x0f /* wait state counter */ 778 779 /* Various validity tests */ 780 /* 781 * From Databook sample source: 782 * MODE_AR_SYSCFG must have, with j = ***read*** (***, R_AUX) 783 * and k = (j>>9)&7: 784 * if (k&4) k == 5 785 * And also: 786 * j&0x0f is none of 2, 8, 9, b, c, d, f 787 * if (j&8) must have (j&3 == 2) 788 * Can't have j==2 789 */ 790 #if 0 791 /* this is from the Databook sample code and apparently is wrong */ 792 #define INVALID_AR_SYSCFG(x) ((((x)&0x1000) && (((x)&0x0c00) != 0x0200)) \ 793 || (((((x)&0x08) == 0) || (((x)&0x03) == 2)) \ 794 && ((x) != 0x02))) 795 #else 796 #define INVALID_AR_SYSCFG(x) ((((x)&0x0800) && (((x)&0x0600) != 0x0100)) \ 797 || ((((((x)&0x08) == 0) && (((x)&0x03) == 2)) \ 798 || (((x)&0x03) == 2)) \ 799 && ((x) != 0x02))) 800 #endif 801 /* AR_ILOCK must have bits 6 and 7 the same: */ 802 #define INVALID_AR_ILOCK(x) (((x)&0xc0)==0 || (((x)&0xc0)==0xc0)) 803 804 /* AR_TEST has some reserved bits: */ 805 #define INVALID_AR_TEST(x) (((x)&0154) != 0) 806 807 808 #define TCIC_IO_WINS 2 809 #define TCIC_MAX_MEM_WINS 5 810 811 /* 812 * Memory window addresses refer to bits A23-A12 of the ISA system memory 813 * address. This is a shift of 12 bits. The LSB contains A19-A12, and the 814 * MSB contains A23-A20, plus some other bits. 815 */ 816 817 #define TCIC_MEM_SHIFT 12 818 #define TCIC_MEM_PAGESIZE (1<<TCIC_MEM_SHIFT) 819 820 #endif /* _TCIC2REG_H */
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