Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/tcic2var.h
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1 /* $OpenBSD: tcic2var.h,v 1.5 2021/03/07 06:21:38 jsg Exp $ */ 2 /* $NetBSD: tcic2var.h,v 1.1 1999/03/23 20:04:14 bad Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 1999 Christoph Badura. All rights reserved. 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _TCIC2VAR_H 35 #define _TCIC2VAR_H 36 37 #include <sys/device.h> 38 39 #include <dev/pcmcia/pcmciareg.h> 40 #include <dev/pcmcia/pcmciachip.h> 41 42 #include <dev/ic/tcic2reg.h> 43 44 struct proc; 45 46 struct tcic_event { 47 SIMPLEQ_ENTRY(tcic_event) pe_q; 48 int pe_type; 49 }; 50 51 /* pe_type */ 52 #define TCIC_EVENT_INSERTION 0 53 #define TCIC_EVENT_REMOVAL 1 54 55 56 struct tcic_handle { 57 struct tcic_softc *sc; 58 int sock; /* socket number */ 59 int flags; 60 int sstat; /* last value of R_SSTAT */ 61 int memalloc; 62 int memwins; 63 struct { 64 bus_addr_t addr; 65 bus_size_t size; 66 int size2; /* size as 2^n scaled by 4K */ 67 long offset; 68 int speed; /* in ns */ 69 int kind; 70 } mem[TCIC_MAX_MEM_WINS]; 71 int ioalloc; 72 struct { 73 bus_addr_t addr; 74 bus_size_t size; 75 int width; 76 int speed; /* in ns */ 77 } io[TCIC_IO_WINS]; 78 int ih_irq; 79 struct device *pcmcia; 80 81 int shutdown; 82 struct proc *event_thread; 83 SIMPLEQ_HEAD(, tcic_event) events; 84 }; 85 86 #define TCIC_FLAG_SOCKETP 0x0001 87 #define TCIC_FLAG_CARDP 0x0002 88 89 /* 90 * This is sort of arbitrary. It merely needs to be "enough". It can be 91 * overridden in the conf file, anyway. 92 */ 93 94 #define TCIC_MEM_PAGES 4 95 #define TCIC_MEMSIZE TCIC_MEM_PAGES*TCIC_MEM_PAGESIZE 96 97 #define TCIC_NSLOTS 2 98 99 struct tcic_softc { 100 struct device dev; 101 102 bus_space_tag_t memt; 103 bus_space_handle_t memh; 104 bus_space_tag_t iot; 105 bus_space_handle_t ioh; 106 107 int chipid; 108 int validirqs; 109 int pwrena; /* holds TCIC_PWR_ENA on'084 and successors */ 110 111 /* XXX isa_chipset_tag_t, pci_chipset_tag_t, etc. */ 112 void *intr_est; 113 114 pcmcia_chipset_tag_t pct; 115 116 /* this needs to be large enough to hold TCIC_MEM_PAGES bits */ 117 int subregionmask; 118 119 /* used by memory window mapping functions */ 120 bus_addr_t membase; 121 int memsize2; /* int(log2(memsize)) */ 122 123 /* 124 * used by io window mapping functions. These can actually overlap 125 * with another tcic, since the underlying extent mapper will deal 126 * with individual allocations. This is here to deal with the fact 127 * that different busses have different real widths (different pc 128 * hardware seems to use 10 or 12 bits for the I/O bus). 129 */ 130 bus_addr_t iobase; 131 bus_size_t iosize; 132 133 int irq; 134 void *ih; 135 136 struct tcic_handle handle[TCIC_NSLOTS]; 137 }; 138 139 int tcic_log2(u_int); 140 int tcic_ns2wscnt(int); 141 142 int tcic_check_reserved_bits(bus_space_tag_t, bus_space_handle_t); 143 int tcic_chipid(bus_space_tag_t, bus_space_handle_t); 144 int tcic_chipid_known(int); 145 char *tcic_chipid_to_string(int); 146 int tcic_validirqs(int); 147 148 void tcic_attach(struct tcic_softc *); 149 void tcic_attach_sockets(struct tcic_softc *); 150 int tcic_intr(void *arg); 151 152 static __inline__ int tcic_read_1(struct tcic_handle *, int); 153 static __inline__ int tcic_read_2(struct tcic_handle *, int); 154 static __inline__ int tcic_read_4(struct tcic_handle *, int); 155 static __inline__ void tcic_write_1(struct tcic_handle *, int, int); 156 static __inline__ void tcic_write_2(struct tcic_handle *, int, int); 157 static __inline__ void tcic_write_4(struct tcic_handle *, int, int); 158 static __inline__ int tcic_read_ind_2(struct tcic_handle *, int); 159 static __inline__ void tcic_write_ind_2(struct tcic_handle *, int, int); 160 static __inline__ void tcic_sel_sock(struct tcic_handle *); 161 static __inline__ void tcic_wait_ready(struct tcic_handle *); 162 static __inline__ int tcic_read_aux_1(bus_space_tag_t, bus_space_handle_t, int, int); 163 static __inline__ int tcic_read_aux_2(bus_space_tag_t, bus_space_handle_t, int); 164 static __inline__ void tcic_write_aux_1(bus_space_tag_t, bus_space_handle_t, int, int, int); 165 static __inline__ void tcic_write_aux_2(bus_space_tag_t, bus_space_handle_t, int, int); 166 167 int tcic_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 168 struct pcmcia_mem_handle *); 169 void tcic_chip_mem_free(pcmcia_chipset_handle_t, 170 struct pcmcia_mem_handle *); 171 int tcic_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 172 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 173 void tcic_chip_mem_unmap(pcmcia_chipset_handle_t, int); 174 175 int tcic_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 176 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 177 void tcic_chip_io_free(pcmcia_chipset_handle_t, 178 struct pcmcia_io_handle *); 179 int tcic_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 180 bus_size_t, struct pcmcia_io_handle *, int *); 181 void tcic_chip_io_unmap(pcmcia_chipset_handle_t, int); 182 183 void tcic_chip_socket_enable(pcmcia_chipset_handle_t); 184 void tcic_chip_socket_disable(pcmcia_chipset_handle_t); 185 186 static __inline__ int tcic_read_1(struct tcic_handle *, int); 187 static __inline__ int 188 tcic_read_1(struct tcic_handle *h, int reg) 189 { 190 return (bus_space_read_1(h->sc->iot, h->sc->ioh, reg)); 191 } 192 193 static __inline__ int tcic_read_2(struct tcic_handle *, int); 194 static __inline__ int 195 tcic_read_2(struct tcic_handle *h, int reg) 196 { 197 return (bus_space_read_2(h->sc->iot, h->sc->ioh, reg)); 198 } 199 200 static __inline__ int tcic_read_4(struct tcic_handle *, int); 201 static __inline__ int 202 tcic_read_4(struct tcic_handle *h, int reg) 203 { 204 int val; 205 val = bus_space_read_2(h->sc->iot, h->sc->ioh, reg); 206 val |= bus_space_read_2(h->sc->iot, h->sc->ioh, reg+2) << 16; 207 return val; 208 } 209 210 static __inline__ void tcic_write_1(struct tcic_handle *, int, int); 211 static __inline__ void 212 tcic_write_1(struct tcic_handle *h, int reg, int data) 213 { 214 bus_space_write_1(h->sc->iot, h->sc->ioh, reg, (data)); 215 } 216 217 static __inline__ void tcic_write_2(struct tcic_handle *, int, int); 218 static __inline__ void 219 tcic_write_2(struct tcic_handle *h, int reg, int data) 220 { 221 bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data)); 222 } 223 224 static __inline__ void tcic_write_4(struct tcic_handle *, int, int); 225 static __inline__ void 226 tcic_write_4(struct tcic_handle *h, int reg, int data) 227 { 228 bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data)); 229 bus_space_write_2(h->sc->iot, h->sc->ioh, reg+2, (data)>>16); 230 } 231 232 static __inline__ int tcic_read_ind_2(struct tcic_handle *, int); 233 static __inline__ int 234 tcic_read_ind_2(struct tcic_handle *h, int reg) 235 { 236 int r_addr, val; 237 r_addr = tcic_read_4(h, TCIC_R_ADDR); 238 tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG); 239 val = bus_space_read_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA); 240 tcic_write_4(h, TCIC_R_ADDR, r_addr); 241 return val; 242 } 243 244 static __inline__ void tcic_write_ind_2(struct tcic_handle *, int, int); 245 static __inline__ void 246 tcic_write_ind_2(struct tcic_handle *h, int reg, int data) 247 { 248 int r_addr; 249 r_addr = tcic_read_4(h, TCIC_R_ADDR); 250 tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG); 251 bus_space_write_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA, (data)); 252 tcic_write_4(h, TCIC_R_ADDR, r_addr); 253 } 254 255 static __inline__ void tcic_sel_sock(struct tcic_handle *); 256 static __inline__ void 257 tcic_sel_sock(struct tcic_handle *h) 258 { 259 int r_addr; 260 r_addr = tcic_read_2(h, TCIC_R_ADDR2); 261 tcic_write_2(h, TCIC_R_ADDR2, 262 (h->sock<<TCIC_ADDR2_SS_SHFT)|(r_addr & ~TCIC_ADDR2_SS_MASK)); 263 } 264 265 static __inline__ void tcic_wait_ready(struct tcic_handle *); 266 static __inline__ void 267 tcic_wait_ready(struct tcic_handle *h) 268 { 269 int i; 270 271 /* XXX appropriate socket must have been selected already. */ 272 for (i = 0; i < 10000; i++) { 273 if (tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_RDY) 274 return; 275 delay(500); 276 } 277 278 #ifdef DIAGNOSTIC 279 printf("tcic_wait_ready ready never happened\n"); 280 #endif 281 } 282 283 static __inline__ int tcic_read_aux_1(bus_space_tag_t, bus_space_handle_t, int, int); 284 static __inline__ int 285 tcic_read_aux_1(bus_space_tag_t iot, bus_space_handle_t ioh, int auxreg, 286 int reg) 287 { 288 int mode, val; 289 mode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 290 bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg); 291 val = bus_space_read_1(iot, ioh, reg); 292 return val; 293 } 294 295 static __inline__ int tcic_read_aux_2(bus_space_tag_t, bus_space_handle_t, int); 296 static __inline__ int 297 tcic_read_aux_2(bus_space_tag_t iot, bus_space_handle_t ioh, int auxreg) 298 { 299 int mode, val; 300 mode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 301 bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg); 302 val = bus_space_read_2(iot, ioh, TCIC_R_AUX); 303 return val; 304 } 305 306 static __inline__ void tcic_write_aux_1(bus_space_tag_t, bus_space_handle_t, int, int, int); 307 static __inline__ void 308 tcic_write_aux_1(bus_space_tag_t iot, bus_space_handle_t ioh, int auxreg, 309 int reg, int val) 310 { 311 int mode; 312 mode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 313 bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg); 314 bus_space_write_1(iot, ioh, reg, val); 315 } 316 317 static __inline__ void tcic_write_aux_2(bus_space_tag_t, bus_space_handle_t, int, int); 318 static __inline__ void 319 tcic_write_aux_2(bus_space_tag_t iot, bus_space_handle_t ioh, int auxreg, 320 int val) 321 { 322 int mode; 323 mode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 324 bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg); 325 bus_space_write_2(iot, ioh, TCIC_R_AUX, val); 326 } 327 328 #endif /* _TCIC2VAR_H */
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