The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/tms9914reg.h

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    1 /*      $NetBSD: tms9914reg.h,v 1.1 2003/06/02 03:55:04 gmcgarry Exp $  */
    2 
    3 /*-
    4  * Copyright (c) 2002 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Gregory McGarry.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *        This product includes software developed by the NetBSD
   21  *        Foundation, Inc. and its contributors.
   22  * 4. Neither the name of The NetBSD Foundation nor the names of its
   23  *    contributors may be used to endorse or promote products derived
   24  *    from this software without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   36  * POSSIBILITY OF SUCH DAMAGE.
   37  */
   38 
   39 #define TMS9914_IOSIZE          8
   40 
   41 /*
   42  * Direct-access Registers (write only)
   43  */
   44 
   45 #define TMS9914_IMR0            0       /* (W) interrupt mask 0 */
   46 #define         IMR0_MAC        0x01    /* my address change */
   47 #define         IMR0_RLC        0x02    /* remote/local address change */
   48 #define         IMR0_SPAS       0x04    /* serial poll active state */
   49 #define         IMR0_END        0x08    /* EOI or EOS */
   50 #define         IMR0_BO         0x10    /* byte out */
   51 #define         IMR0_BI         0x20    /* byte in */
   52 #define TMS9914_IMR1            1       /* (W) interrupt mask 1 */
   53 #define         IMR1_IFC        0x01    /* IFC asserted */
   54 #define         IMR1_SRQ        0x02    /* SRQ asserted */
   55 #define         IMR1_MA         0x04    /* my address */
   56 #define         IMR1_DCAS       0x08    /* device clear active state */
   57 #define         IMR1_APT        0x10    /* address pass-through */
   58 #define         IMR1_UCG        0x20    /* unrecognised command */
   59 #define         IMR1_ERR        0x40    /* data transmission error */
   60 #define         IMR1_GET        0x80    /* group execute trigger */
   61 #define TMS9914_AUXCR           3       /* (W) auxiliary command */
   62 #define TMS9914_ADDR            4       /* (W) address register */
   63 #define         ADDR_DAT        0x20
   64 #define         ADDR_DAL        0x40
   65 #define         ADDR_EDPA       0x80
   66 #define TMS9914_SPMR            5       /* (W) serial poll register */
   67 #define TMS9914_PPR             6       /* (W) parallel poll */
   68 #define TMS9914_CDOR            7       /* (W) data-out register */
   69 
   70 /*
   71  * Direct-access Registers (read only)
   72  */
   73 
   74 #define TMS9914_ISR0            0       /* (R) interrupt status 0 */
   75 #define         ISR0_MAC        0x01    /* my address change */
   76 #define         ISR0_RLC        0x02    /* remote/local address change */
   77 #define         ISR0_SPAS       0x04    /* serial poll active state */
   78 #define         ISR0_END        0x08    /* EOI or EOS */
   79 #define         ISR0_BO         0x10    /* byte out */
   80 #define         ISR0_BI         0x20    /* byte in */
   81 #define TMS9914_ISR1            1       /* (R) interrupt status 1 */
   82 #define         ISR1_IFC        0x01    /* IFC asserted */
   83 #define         ISR1_SRQ        0x02    /* SRQ asserted */
   84 #define         ISR1_MA         0x04    /* my address */
   85 #define         ISR1_DCAS       0x08    /* device clear active state */
   86 #define         ISR1_APT        0x10    /* address pass-through */
   87 #define         ISR1_UCG        0x20    /* unrecognised command */
   88 #define         ISR1_ERR        0x40    /* data transmission error */
   89 #define         ISR1_GET        0x80    /* group execute trigger */
   90 #define TMS9914_ADSR            2       /* (R) address status */
   91 #define         ADSR_ULPA       0x01    /* store last address LSB */
   92 #define         ADSR_TADS       0x02    /* talker addressed */
   93 #define         ADSR_LADS       0x04    /* listener addressed */
   94 #define         ADSR_TPAS       0x08    /* talker primary address state */
   95 #define         ADSR_LPAS       0x10    /* listener primary address state */
   96 #define         ADSR_ATN        0x20    /* ATN active */
   97 #define         ADSR_LLO        0x40    /* LLO active */
   98 #define         ADSR_REM        0x80    /* REM active */
   99 #define TMS9914_CPTR            6       /* (R) command pass-through */
  100 #define TMS9914_DIR             7       /* (R) data-in register */
  101 
  102 /*
  103  * Auxiliary Commands
  104  *
  105  * Two basic type of commands are implemented: pulsed and static.
  106  * Static commands enable (set) or disable (clear) chip features.
  107  * Pulsed commands stay active for one clock pulse.
  108  *
  109  */
  110 
  111 /* pulsed commands */
  112 #define AUXCMD_RHDF     0x02    /* release RFD holdoff */
  113 #define AUXCMD_NBAF     0x05    /* new byte available false */
  114 #define AUXCMD_SEOI     0x08    /* send EOI with next byte */
  115 #define AUXCMD_GTS      0x0b    /* go to standby (clear ATN line) */
  116 #define AUXCMD_TCA      0x0c    /* take control (async) */
  117 #define AUXCMD_TCS      0x0d    /* take control (sync) */
  118 
  119 /* static commands */
  120 #define AUXCMD_SET      0x80
  121 #define AUXCMD_CLEAR    0x00
  122 #define AUXCMD_SWRST    0x00    /* Software reset */
  123 #define AUXCMD_HDFA     0x03    /* holdoff on all data */
  124 #define AUXCMD_HDFE     0x04    /* holdoff on EOI data only */
  125 #define AUXCMD_RTL      0x07    /* return to local */
  126 #define AUXCMD_LON      0x09    /* listen only */
  127 #define AUXCMD_TON      0x0a    /* talk only */
  128 #define AUXCMD_RPP      0x0e    /* request parallel poll */
  129 #define AUXCMD_SIC      0x0f    /* IFC (interface clear) line */
  130 #define AUXCMD_SRE      0x10    /* REN (remote enable) line */
  131 #define AUXCMD_DAI      0x13    /* interrupt disable */
  132 #define AUXCMD_STD1     0x15    /* 1200ns T1 delay */
  133 #define AUXCMD_SHDW     0x16    /* shadow handshake */
  134 #define AUXCMD_VSTD1    0x17    /* 600ns T1 delay */

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