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sys/dev/ic/trm.c
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1 /* $OpenBSD: trm.c,v 1.44 2022/01/09 05:42:42 jsg Exp $ 2 * ------------------------------------------------------------ 3 * O.S : OpenBSD 4 * File Name : trm.c 5 * Device Driver for Tekram DC395U/UW/F,DC315/U 6 * PCI SCSI Bus Master Host Adapter 7 * (SCSI chip set used Tekram ASIC TRM-S1040) 8 * 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 * (C)Copyright 2001-2002 Ashley R. Martens and Kenneth R Westerback 11 * ------------------------------------------------------------ 12 * HISTORY: 13 * 14 * REV# DATE NAME DESCRIPTION 15 * 1.00 05/01/99 ERICH CHEN First released for NetBSD 1.4.x 16 * 1.01 00/00/00 MARTIN AKESSON Port to OpenBSD 2.8 17 * 1.02 09/19/01 ASHLEY MARTENS Cleanup and formatting 18 * 2.00 01/00/02 KENNETH R WESTERBACK Rewrite of the bus and code logic 19 * ------------------------------------------------------------ 20 * 21 * Redistribution and use in source and binary forms, with or without 22 * modification, are permitted provided that the following conditions 23 * are met: 24 * 1. Redistributions of source code must retain the above copyright 25 * notice, this list of conditions and the following disclaimer. 26 * 2. Redistributions in binary form must reproduce the above copyright 27 * notice, this list of conditions and the following disclaimer in the 28 * documentation and/or other materials provided with the distribution. 29 * 3. The name of the author may not be used to endorse or promote products 30 * derived from this software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 33 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 34 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 35 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 36 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 37 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 38 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 39 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 40 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 41 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 * 43 * ------------------------------------------------------------ 44 */ 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/malloc.h> 50 #include <sys/buf.h> 51 #include <sys/device.h> 52 53 #include <machine/bus.h> 54 55 #include <scsi/scsi_all.h> 56 #include <scsi/scsiconf.h> 57 #include <scsi/scsi_message.h> 58 59 #include <dev/pci/pcidevs.h> 60 #include <dev/ic/trm.h> 61 62 /* #define TRM_DEBUG0 */ 63 64 void trm_initSRB(struct trm_scsi_req_q *); 65 66 void trm_check_eeprom(struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 67 void trm_read_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 68 void trm_write_all (struct trm_adapter_nvram *, bus_space_tag_t, bus_space_handle_t); 69 70 void trm_set_data (bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 71 void trm_write_cmd(bus_space_tag_t, bus_space_handle_t, u_int8_t, u_int8_t); 72 73 u_int8_t trm_get_data(bus_space_tag_t, bus_space_handle_t, u_int8_t); 74 75 void trm_wait_30us(bus_space_tag_t, bus_space_handle_t); 76 77 void *trm_srb_alloc(void *); 78 79 void trm_DataOutPhase0(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 80 void trm_DataInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 81 void trm_StatusPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 82 void trm_MsgOutPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 83 void trm_MsgInPhase0 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 84 void trm_DataOutPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 85 void trm_DataInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 86 void trm_CommandPhase1(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 87 void trm_StatusPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 88 void trm_MsgOutPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 89 void trm_MsgInPhase1 (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 90 void trm_Nop (struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 91 92 void trm_SetXferParams (struct trm_softc *, struct trm_dcb *, int); 93 94 void trm_DataIO_transfer(struct trm_softc *, struct trm_scsi_req_q *, u_int16_t); 95 96 int trm_StartSRB (struct trm_softc *, struct trm_scsi_req_q *); 97 void trm_srb_reinit (struct trm_softc *, struct trm_scsi_req_q *); 98 void trm_srb_free (void *, void *); 99 void trm_RewaitSRB (struct trm_softc *, struct trm_scsi_req_q *); 100 void trm_FinishSRB (struct trm_softc *, struct trm_scsi_req_q *); 101 void trm_RequestSense(struct trm_softc *, struct trm_scsi_req_q *); 102 103 void trm_initAdapter (struct trm_softc *); 104 void trm_Disconnect (struct trm_softc *); 105 void trm_Reselect (struct trm_softc *); 106 void trm_GoingSRB_Done (struct trm_softc *, struct trm_dcb *); 107 void trm_ScsiRstDetect (struct trm_softc *); 108 void trm_ResetSCSIBus (struct trm_softc *); 109 void trm_reset (struct trm_softc *); 110 void trm_StartWaitingSRB (struct trm_softc *); 111 void trm_ResetAllDevParam(struct trm_softc *); 112 void trm_RecoverSRB (struct trm_softc *); 113 void trm_linkSRB (struct trm_softc *); 114 115 void trm_initACB(struct trm_softc *, int); 116 117 void trm_ResetDevParam(struct trm_softc *, struct trm_dcb *, u_int8_t); 118 119 void trm_EnableMsgOut(struct trm_softc *, u_int8_t); 120 121 void trm_timeout(void *); 122 123 void trm_print_info(struct trm_softc *, struct trm_dcb *); 124 125 /* 126 * ------------------------------------------------------------ 127 * 128 * stateV = (void *) trm_SCSI_phase0[phase] 129 * 130 * ------------------------------------------------------------ 131 */ 132 static void *trm_SCSI_phase0[8] = { 133 trm_DataOutPhase0, /* phase:0 */ 134 trm_DataInPhase0, /* phase:1 */ 135 trm_Nop, /* phase:2 */ 136 trm_StatusPhase0, /* phase:3 */ 137 trm_Nop, /* phase:4 */ 138 trm_Nop, /* phase:5 */ 139 trm_MsgOutPhase0, /* phase:6 */ 140 trm_MsgInPhase0, /* phase:7 */ 141 }; 142 143 /* 144 * ------------------------------------------------------------ 145 * 146 * stateV = (void *) trm_SCSI_phase1[phase] 147 * 148 * ------------------------------------------------------------ 149 */ 150 static void *trm_SCSI_phase1[8] = { 151 trm_DataOutPhase1, /* phase:0 */ 152 trm_DataInPhase1, /* phase:1 */ 153 trm_CommandPhase1, /* phase:2 */ 154 trm_StatusPhase1, /* phase:3 */ 155 trm_Nop, /* phase:4 */ 156 trm_Nop, /* phase:5 */ 157 trm_MsgOutPhase1, /* phase:6 */ 158 trm_MsgInPhase1, /* phase:7 */ 159 }; 160 161 162 struct trm_adapter_nvram trm_eepromBuf[TRM_MAX_ADAPTER_NUM]; 163 /* 164 *Fast20: 000 50ns, 20.0 Mbytes/s 165 * 001 75ns, 13.3 Mbytes/s 166 * 010 100ns, 10.0 Mbytes/s 167 * 011 125ns, 8.0 Mbytes/s 168 * 100 150ns, 6.6 Mbytes/s 169 * 101 175ns, 5.7 Mbytes/s 170 * 110 200ns, 5.0 Mbytes/s 171 * 111 250ns, 4.0 Mbytes/s 172 * 173 *Fast40: 000 25ns, 40.0 Mbytes/s 174 * 001 50ns, 20.0 Mbytes/s 175 * 010 75ns, 13.3 Mbytes/s 176 * 011 100ns, 10.0 Mbytes/s 177 * 100 125ns, 8.0 Mbytes/s 178 * 101 150ns, 6.6 Mbytes/s 179 * 110 175ns, 5.7 Mbytes/s 180 * 111 200ns, 5.0 Mbytes/s 181 */ 182 183 /* 184 * real period: 185 */ 186 u_int8_t trm_clock_period[8] = { 187 /* nanosecond divided by 4 */ 188 12, /* 48 ns 20 MB/sec */ 189 18, /* 72 ns 13.3 MB/sec */ 190 25, /* 100 ns 10.0 MB/sec */ 191 31, /* 124 ns 8.0 MB/sec */ 192 37, /* 148 ns 6.6 MB/sec */ 193 43, /* 172 ns 5.7 MB/sec */ 194 50, /* 200 ns 5.0 MB/sec */ 195 62 /* 248 ns 4.0 MB/sec */ 196 }; 197 198 /* 199 * ------------------------------------------------------------ 200 * Function : trm_srb_alloc 201 * Purpose : Get the first free SRB 202 * Inputs : 203 * Return : NULL or a free SCSI Request block 204 * ------------------------------------------------------------ 205 */ 206 void * 207 trm_srb_alloc(void *xsc) 208 { 209 struct trm_softc *sc = xsc; 210 struct trm_scsi_req_q *pSRB; 211 212 mtx_enter(&sc->sc_srb_mtx); 213 pSRB = TAILQ_FIRST(&sc->freeSRB); 214 if (pSRB != NULL) 215 TAILQ_REMOVE(&sc->freeSRB, pSRB, link); 216 mtx_leave(&sc->sc_srb_mtx); 217 218 #ifdef TRM_DEBUG0 219 printf("%s: trm_srb_alloc. pSRB = %p, next pSRB = %p\n", 220 sc->sc_device.dv_xname, pSRB, TAILQ_FIRST(&sc->freeSRB)); 221 #endif 222 223 return pSRB; 224 } 225 226 /* 227 * ------------------------------------------------------------ 228 * Function : trm_RewaitSRB 229 * Purpose : Q back to pending Q 230 * Inputs : struct trm_dcb * - 231 * struct trm_scsi_req_q * - 232 * ------------------------------------------------------------ 233 */ 234 void 235 trm_RewaitSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 236 { 237 int intflag; 238 239 intflag = splbio(); 240 241 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 242 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 243 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 244 } 245 246 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 247 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 248 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 249 } 250 251 pSRB->SRBState = TRM_READY; 252 pSRB->TargetStatus = SCSI_OK; 253 pSRB->AdaptStatus = TRM_STATUS_GOOD; 254 255 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 256 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 257 258 splx(intflag); 259 } 260 261 /* 262 * ------------------------------------------------------------ 263 * Function : trm_StartWaitingSRB 264 * Purpose : If there is no active DCB then run robin through 265 * the DCB's to find the next waiting SRB 266 * and move it to the going list. 267 * Inputs : struct trm_softc * - 268 * ------------------------------------------------------------ 269 */ 270 void 271 trm_StartWaitingSRB(struct trm_softc *sc) 272 { 273 struct trm_scsi_req_q *pSRB, *next; 274 int intflag; 275 276 intflag = splbio(); 277 278 if ((sc->pActiveDCB != NULL) || 279 (TAILQ_EMPTY(&sc->waitingSRB)) || 280 (sc->sc_Flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) != 0) 281 goto out; 282 283 for (pSRB = TAILQ_FIRST(&sc->waitingSRB); pSRB != NULL; pSRB = next) { 284 next = TAILQ_NEXT(pSRB, link); 285 if (trm_StartSRB(sc, pSRB) == 0) { 286 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 287 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 288 pSRB->SRBFlag |= TRM_ON_GOING_SRB; 289 TAILQ_INSERT_TAIL(&sc->goingSRB, pSRB, link); 290 break; 291 } 292 } 293 294 out: 295 splx(intflag); 296 } 297 298 /* 299 * ------------------------------------------------------------ 300 * Function : trm_scsi_cmd 301 * Purpose : enqueues a SCSI command 302 * Inputs : 303 * Call By : GENERIC SCSI driver 304 * ------------------------------------------------------------ 305 */ 306 void 307 trm_scsi_cmd(struct scsi_xfer *xs) 308 { 309 struct trm_scsi_req_q *pSRB; 310 bus_space_handle_t ioh; 311 struct trm_softc *sc; 312 bus_space_tag_t iot; 313 struct trm_dcb *pDCB; 314 u_int8_t target, lun; 315 int i, error, intflag, timeout, xferflags; 316 317 target = xs->sc_link->target; 318 lun = xs->sc_link->lun; 319 320 sc = xs->sc_link->bus->sb_adapter_softc; 321 ioh = sc->sc_iohandle; 322 iot = sc->sc_iotag; 323 324 #ifdef TRM_DEBUG0 325 if ((xs->flags & SCSI_POLL) != 0) { 326 sc_print_addr(xs->sc_link); 327 printf("trm_scsi_cmd. sc = %p, xs = %p, opcode = 0x%02x\n", 328 sc, xs, lun, xs->cmd.opcode); 329 } 330 #endif 331 332 if (target >= TRM_MAX_TARGETS) { 333 sc_print_addr(xs->sc_link); 334 printf("target >= %d\n", TRM_MAX_TARGETS); 335 xs->error = XS_DRIVER_STUFFUP; 336 scsi_done(xs); 337 return; 338 } 339 if (lun >= TRM_MAX_LUNS) { 340 sc_print_addr(xs->sc_link); 341 printf("lun >= %d\n", TRM_MAX_LUNS); 342 xs->error = XS_DRIVER_STUFFUP; 343 scsi_done(xs); 344 return; 345 } 346 347 pDCB = sc->pDCB[target][lun]; 348 if (pDCB == NULL) { 349 /* Removed as a result of INQUIRY proving no device present */ 350 xs->error = XS_DRIVER_STUFFUP; 351 scsi_done(xs); 352 return; 353 } 354 355 xferflags = xs->flags; 356 if (xferflags & SCSI_RESET) { 357 #ifdef TRM_DEBUG0 358 sc_print_addr(xs->sc_link); 359 printf("trm_reset via SCSI_RESET\n"); 360 #endif 361 trm_reset(sc); 362 xs->error = XS_NOERROR; 363 scsi_done(xs); 364 return; 365 } 366 367 pSRB = xs->io; 368 trm_srb_reinit(sc, pSRB); 369 370 xs->error = XS_NOERROR; 371 xs->status = SCSI_OK; 372 xs->resid = 0; 373 374 intflag = splbio(); 375 376 /* 377 * BuildSRB(pSRB,pDCB); 378 */ 379 if (xs->datalen != 0) { 380 #ifdef TRM_DEBUG0 381 sc_print_addr(xs->sc_link); 382 printf("xs->datalen=%x\n", (u_int32_t)&xs->datalen); 383 sc_print_addr(xs->sc_link); 384 printf("sc->sc_dmatag=0x%x\n", (u_int32_t)sc->sc_dmatag); 385 sc_print_addr(xs->sc_link); 386 printf("pSRB->dmamapxfer=0x%x\n", (u_int32_t)pSRB->dmamapxfer); 387 sc_print_addr(xs->sc_link); 388 printf("xs->data=0x%x\n", (u_int32_t)&xs->data); 389 #endif 390 if ((error = bus_dmamap_load(sc->sc_dmatag, pSRB->dmamapxfer, 391 xs->data, xs->datalen, NULL, 392 (xferflags & SCSI_NOSLEEP) ? BUS_DMA_NOWAIT : 393 BUS_DMA_WAITOK)) != 0) { 394 sc_print_addr(xs->sc_link); 395 printf("DMA transfer map unable to load, error = %d\n", 396 error); 397 xs->error = XS_DRIVER_STUFFUP; 398 splx(intflag); 399 scsi_done(xs); 400 return; 401 } 402 403 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 404 0, pSRB->dmamapxfer->dm_mapsize, 405 (xferflags & SCSI_DATA_IN) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 406 407 /* 408 * Set up the scatter gather list 409 */ 410 for (i = 0; i < pSRB->dmamapxfer->dm_nsegs; i++) { 411 pSRB->SegmentX[i].address = pSRB->dmamapxfer->dm_segs[i].ds_addr; 412 pSRB->SegmentX[i].length = pSRB->dmamapxfer->dm_segs[i].ds_len; 413 } 414 pSRB->SRBTotalXferLength = xs->datalen; 415 pSRB->SRBSGCount = pSRB->dmamapxfer->dm_nsegs; 416 } 417 418 pSRB->pSRBDCB = pDCB; 419 pSRB->xs = xs; 420 pSRB->ScsiCmdLen = xs->cmdlen; 421 422 memcpy(pSRB->CmdBlock, &xs->cmd, xs->cmdlen); 423 424 timeout_set(&xs->stimeout, trm_timeout, pSRB); 425 426 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 427 TAILQ_INSERT_TAIL(&sc->waitingSRB, pSRB, link); 428 trm_StartWaitingSRB(sc); 429 430 if ((xferflags & SCSI_POLL) == 0) { 431 timeout_add_msec(&xs->stimeout, xs->timeout); 432 splx(intflag); 433 return; 434 } 435 436 splx(intflag); 437 for (timeout = xs->timeout; timeout > 0; timeout--) { 438 intflag = splbio(); 439 trm_Interrupt(sc); 440 splx(intflag); 441 if (ISSET(xs->flags, ITSDONE)) 442 break; 443 DELAY(1000); 444 } 445 446 if (!ISSET(xs->flags, ITSDONE) && timeout == 0) 447 trm_timeout(pSRB); 448 449 scsi_done(xs); 450 } 451 452 /* 453 * ------------------------------------------------------------ 454 * Function : trm_ResetAllDevParam 455 * Purpose : 456 * Inputs : struct trm_softc * 457 * ------------------------------------------------------------ 458 */ 459 void 460 trm_ResetAllDevParam(struct trm_softc *sc) 461 { 462 struct trm_adapter_nvram *pEEpromBuf; 463 int target, quirks; 464 465 pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 466 467 for (target = 0; target < TRM_MAX_TARGETS; target++) { 468 if (target == sc->sc_AdaptSCSIID || sc->pDCB[target][0] == NULL) 469 continue; 470 471 if ((sc->pDCB[target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0) 472 quirks = SDEV_NOWIDE | SDEV_NOSYNC | SDEV_NOTAGS; 473 else if (sc->pDCB[target][0]->sc_link != NULL) 474 quirks = sc->pDCB[target][0]->sc_link->quirks; 475 476 trm_ResetDevParam(sc, sc->pDCB[target][0], quirks); 477 } 478 } 479 480 /* 481 * ------------------------------------------------------------ 482 * Function : trm_ResetDevParam 483 * Purpose : 484 * Inputs : 485 * ------------------------------------------------------------ 486 */ 487 void 488 trm_ResetDevParam(struct trm_softc *sc, struct trm_dcb *pDCB, u_int8_t quirks) 489 { 490 struct trm_adapter_nvram *pEEpromBuf = &trm_eepromBuf[sc->sc_AdapterUnit]; 491 u_int8_t PeriodIndex; 492 const int target = pDCB->target; 493 494 pDCB->DCBFlag &= TRM_QUIRKS_VALID; 495 pDCB->DCBFlag |= (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE); 496 497 pDCB->SyncPeriod = 0; 498 pDCB->SyncOffset = 0; 499 pDCB->MaxNegoPeriod = 0; 500 501 pDCB->DevMode = pEEpromBuf->NvramTarget[target].NvmTarCfg0; 502 503 pDCB->IdentifyMsg = MSG_IDENTIFY(pDCB->lun, ((pDCB->DevMode & TRM_DISCONNECT) != 0)); 504 505 if (((quirks & SDEV_NOWIDE) == 0) && 506 (pDCB->DevMode & TRM_WIDE) && 507 ((sc->sc_config & HCC_WIDE_CARD) != 0)) 508 pDCB->DCBFlag |= TRM_WIDE_NEGO_16BIT; 509 510 if (((quirks & SDEV_NOSYNC) == 0) && 511 ((pDCB->DevMode & TRM_SYNC) != 0)) { 512 PeriodIndex = pEEpromBuf->NvramTarget[target].NvmTarPeriod & 0x07; 513 pDCB->MaxNegoPeriod = trm_clock_period[PeriodIndex]; 514 } 515 516 if (((quirks & SDEV_NOTAGS) == 0) && 517 ((pDCB->DevMode & TRM_TAG_QUEUING) != 0) && 518 ((pDCB->DevMode & TRM_DISCONNECT) != 0)) 519 /* TODO XXXX: Every device(lun) gets to queue TagMaxNum commands? */ 520 pDCB->DCBFlag |= TRM_USE_TAG_QUEUING; 521 522 trm_SetXferParams(sc, pDCB, 0); 523 } 524 525 /* 526 * ------------------------------------------------------------ 527 * Function : trm_RecoverSRB 528 * Purpose : Moves all SRBs from Going to Waiting for all the Link DCBs 529 * Inputs : struct trm_softc * - 530 * ------------------------------------------------------------ 531 */ 532 void 533 trm_RecoverSRB(struct trm_softc *sc) 534 { 535 struct trm_scsi_req_q *pSRB; 536 537 /* ASSUME we are inside splbio()/splx() */ 538 539 while ((pSRB = TAILQ_FIRST(&sc->goingSRB)) != NULL) { 540 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 541 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 542 pSRB->SRBFlag |= TRM_ON_WAITING_SRB; 543 TAILQ_INSERT_HEAD(&sc->waitingSRB, pSRB, link); 544 } 545 } 546 547 /* 548 * ------------------------------------------------------------ 549 * Function : trm_reset 550 * Purpose : perform a hard reset on the SCSI bus (and TRM_S1040 chip). 551 * Inputs : 552 * ------------------------------------------------------------ 553 */ 554 void 555 trm_reset (struct trm_softc *sc) 556 { 557 const bus_space_handle_t ioh = sc->sc_iohandle; 558 const bus_space_tag_t iot = sc->sc_iotag; 559 int i, intflag; 560 561 intflag = splbio(); 562 563 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 564 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 565 566 trm_ResetSCSIBus(sc); 567 for (i = 0; i < 500; i++) 568 DELAY(1000); 569 570 /* 571 * Enable all SCSI interrupts except EN_SCAM 572 */ 573 bus_space_write_1(iot, ioh, 574 TRM_S1040_SCSI_INTEN, 575 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 576 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 577 /* 578 * Enable DMA interrupt 579 */ 580 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 581 /* 582 * Clear DMA FIFO 583 */ 584 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, CLRXFIFO); 585 /* 586 * Clear SCSI FIFO 587 */ 588 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 589 590 trm_ResetAllDevParam(sc); 591 trm_GoingSRB_Done(sc, NULL); 592 sc->pActiveDCB = NULL; 593 594 /* 595 * RESET_DETECT, RESET_DONE, RESET_DEV 596 */ 597 sc->sc_Flag = 0; 598 trm_StartWaitingSRB(sc); 599 600 splx(intflag); 601 } 602 603 /* 604 * ------------------------------------------------------------ 605 * Function : trm_timeout 606 * Purpose : Prints a timeout message and aborts the timed out SCSI request 607 * Inputs : void * - A struct trm_scsi_req_q * structure pointer 608 * ------------------------------------------------------------ 609 */ 610 void 611 trm_timeout(void *arg1) 612 { 613 struct trm_scsi_req_q *pSRB; 614 struct scsi_xfer *xs; 615 struct trm_softc *sc; 616 617 pSRB = (struct trm_scsi_req_q *)arg1; 618 xs = pSRB->xs; 619 620 if (xs != NULL) { 621 sc = xs->sc_link->bus->sb_adapter_softc; 622 sc_print_addr(xs->sc_link); 623 printf("SCSI OpCode 0x%02x ", xs->cmd.opcode); 624 if (pSRB->SRBFlag & TRM_AUTO_REQSENSE) 625 printf("REQUEST SENSE "); 626 printf("timed out\n"); 627 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 628 trm_FinishSRB(sc, pSRB); 629 #ifdef TRM_DEBUG0 630 sc_print_addr(xs->sc_link); 631 printf("trm_reset via trm_timeout()\n"); 632 #endif 633 trm_reset(sc); 634 trm_StartWaitingSRB(sc); 635 } 636 } 637 638 /* 639 * ------------------------------------------------------------ 640 * Function : trm_StartSRB 641 * Purpose : Send the commands in the SRB to the device 642 * Inputs : struct trm_softc * - 643 * struct trm_scsi_req_q * - 644 * Return : 0 - SCSI processor is unoccupied 645 * 1 - SCSI processor is occupied with an SRB 646 * ------------------------------------------------------------ 647 */ 648 int 649 trm_StartSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 650 { 651 const bus_space_handle_t ioh = sc->sc_iohandle; 652 const bus_space_tag_t iot = sc->sc_iotag; 653 struct trm_dcb *pDCB = pSRB->pSRBDCB; 654 u_int32_t tag_mask; 655 u_int8_t tag_id, scsicommand; 656 657 #ifdef TRM_DEBUG0 658 printf("%s: trm_StartSRB. sc = %p, pDCB = %p, pSRB = %p\n", 659 sc->sc_device.dv_xname, sc, pDCB, pSRB); 660 #endif 661 /* 662 * If the queue is full or the SCSI processor has a pending interrupt 663 * then try again later. 664 */ 665 if ((pDCB->DCBFlag & TRM_QUEUE_FULL) || (bus_space_read_2(iot, ioh, 666 TRM_S1040_SCSI_STATUS) & SCSIINTERRUPT)) 667 return (1); 668 669 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 670 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, pDCB->target); 671 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 672 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 673 674 if ((sc->pDCB[pDCB->target][0]->sc_link != NULL) && 675 ((sc->pDCB[pDCB->target][0]->DCBFlag & TRM_QUIRKS_VALID) == 0)) { 676 sc->pDCB[pDCB->target][0]->DCBFlag |= TRM_QUIRKS_VALID; 677 trm_ResetDevParam(sc, sc->pDCB[pDCB->target][0], sc->pDCB[pDCB->target][0]->sc_link->quirks); 678 } 679 680 /* 681 * Flush FIFO 682 */ 683 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 684 685 sc->MsgCnt = 1; 686 sc->MsgBuf[0] = pDCB->IdentifyMsg; 687 if (((pSRB->xs->flags & SCSI_POLL) != 0) || 688 (pSRB->CmdBlock[0] == INQUIRY) || 689 (pSRB->CmdBlock[0] == REQUEST_SENSE)) 690 sc->MsgBuf[0] &= ~MSG_IDENTIFY_DISCFLAG; 691 692 scsicommand = SCMD_SEL_ATN; 693 694 if ((pDCB->DCBFlag & (TRM_WIDE_NEGO_ENABLE | TRM_SYNC_NEGO_ENABLE)) != 0) { 695 scsicommand = SCMD_SEL_ATNSTOP; 696 pSRB->SRBState = TRM_MSGOUT; 697 698 } else if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) == 0) { 699 pDCB->DCBFlag |= TRM_QUEUE_FULL; 700 701 } else if ((sc->MsgBuf[0] & MSG_IDENTIFY_DISCFLAG) != 0) { 702 if (pSRB->TagNumber == TRM_NO_TAG) { 703 for (tag_id=1, tag_mask=2; tag_id < 32; tag_id++, tag_mask <<= 1) 704 if ((tag_mask & pDCB->TagMask) == 0) { 705 pDCB->TagMask |= tag_mask; 706 pSRB->TagNumber = tag_id; 707 break; 708 } 709 710 if (tag_id >= 32) { 711 pDCB->DCBFlag |= TRM_QUEUE_FULL; 712 sc->MsgCnt = 0; 713 return 1; 714 } 715 } 716 717 /* TODO XXXX: Should send ORDERED_Q_TAG if metadata (non-block) i/o!? */ 718 sc->MsgBuf[sc->MsgCnt++] = MSG_SIMPLE_Q_TAG; 719 sc->MsgBuf[sc->MsgCnt++] = pSRB->TagNumber; 720 721 scsicommand = SCMD_SEL_ATN3; 722 } 723 724 pSRB->SRBState = TRM_START; 725 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 726 sc->pActiveDCB = pDCB; 727 pDCB->pActiveSRB = pSRB; 728 729 if (sc->MsgCnt > 0) { 730 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_FIFO, sc->MsgBuf[0]); 731 if (sc->MsgCnt > 1) { 732 DELAY(30); 733 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[1], sc->MsgCnt - 1); 734 } 735 sc->MsgCnt = 0; 736 } 737 738 /* 739 * it's important for atn stop 740 */ 741 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH | DO_HWRESELECT); 742 /* 743 * SCSI command 744 */ 745 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, scsicommand); 746 747 return 0; 748 } 749 750 /* 751 * ------------------------------------------------------------ 752 * Function : trm_Interrupt 753 * Purpose : Catch an interrupt from the adapter 754 * Process pending device interrupts. 755 * Inputs : void * - struct trm_softc * structure pointer 756 * ------------------------------------------------------------ 757 */ 758 int 759 trm_Interrupt(void *vsc) 760 { 761 void (*stateV)(struct trm_softc *, struct trm_scsi_req_q *, u_int8_t *); 762 struct trm_scsi_req_q *pSRB; 763 bus_space_handle_t ioh; 764 struct trm_softc *sc = (struct trm_softc *)vsc; 765 bus_space_tag_t iot; 766 u_int16_t phase; 767 u_int8_t scsi_status, scsi_intstatus; 768 769 if (sc == NULL) 770 return 0; 771 772 ioh = sc->sc_iohandle; 773 iot = sc->sc_iotag; 774 775 scsi_status = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_STATUS); 776 if (!(scsi_status & SCSIINTERRUPT)) 777 return 0; 778 scsi_intstatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 779 780 #ifdef TRM_DEBUG0 781 printf("%s: trm_interrupt - scsi_status=0x%02x, scsi_intstatus=0x%02x\n", 782 sc->sc_device.dv_xname, scsi_status, scsi_intstatus); 783 #endif 784 if ((scsi_intstatus & (INT_SELTIMEOUT | INT_DISCONNECT)) != 0) 785 trm_Disconnect(sc); 786 787 else if ((scsi_intstatus & INT_RESELECTED) != 0) 788 trm_Reselect(sc); 789 790 else if ((scsi_intstatus & INT_SCSIRESET) != 0) 791 trm_ScsiRstDetect(sc); 792 793 else if ((sc->pActiveDCB != NULL) && ((scsi_intstatus & (INT_BUSSERVICE | INT_CMDDONE)) != 0)) { 794 pSRB = sc->pActiveDCB->pActiveSRB; 795 /* 796 * software sequential machine 797 */ 798 phase = (u_int16_t) pSRB->ScsiPhase; /* phase: */ 799 /* 800 * 62037 or 62137 801 * call trm_SCSI_phase0[]... "phase entry" 802 * handle every phase before start transfer 803 */ 804 stateV = trm_SCSI_phase0[phase]; 805 stateV(sc, pSRB, &scsi_status); 806 /* 807 * if any exception occurred 808 * scsi_status will be modified to bus free phase 809 * new scsi_status transfer out from previous stateV 810 */ 811 /* 812 * phase:0,1,2,3,4,5,6,7 813 */ 814 pSRB->ScsiPhase = scsi_status & PHASEMASK; 815 phase = (u_int16_t) scsi_status & PHASEMASK; 816 /* 817 * call trm_SCSI_phase1[]... "phase entry" 818 * handle every phase do transfer 819 */ 820 stateV = trm_SCSI_phase1[phase]; 821 stateV(sc, pSRB, &scsi_status); 822 823 } else { 824 return 0; 825 } 826 827 return 1; 828 } 829 830 /* 831 * ------------------------------------------------------------ 832 * Function : trm_MsgOutPhase0 833 * Purpose : Check the state machine before sending a message out 834 * Inputs : struct trm_softc * - 835 * struct trm_scsi_req_q * - 836 * u_int8_t * - scsi status, set to PH_BUS_FREE if not ready 837 * ------------------------------------------------------------ 838 */ 839 void 840 trm_MsgOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 841 { 842 switch (pSRB->SRBState) { 843 case TRM_UNEXPECT_RESEL: 844 case TRM_ABORT_SENT: 845 *pscsi_status = PH_BUS_FREE; /* initial phase */ 846 break; 847 848 default: 849 break; 850 } 851 } 852 853 /* 854 * ------------------------------------------------------------ 855 * Function : trm_MsgOutPhase1 856 * Purpose : Write the message out to the bus 857 * Inputs : struct trm_softc * - 858 * struct trm_scsi_req_q * - 859 * u_int8_t * - unused 860 * ------------------------------------------------------------ 861 */ 862 void 863 trm_MsgOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 864 { 865 const bus_space_handle_t ioh = sc->sc_iohandle; 866 const bus_space_tag_t iot = sc->sc_iotag; 867 struct trm_dcb *pDCB = sc->pActiveDCB; 868 869 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 870 871 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_ENABLE) != 0) { 872 /* 873 * WIDE DATA TRANSFER REQUEST code (03h) 874 */ 875 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 876 pDCB->DCBFlag |= TRM_DOING_WIDE_NEGO; 877 878 sc->MsgBuf[0] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 879 sc->MsgBuf[1] = MSG_EXTENDED; 880 sc->MsgBuf[2] = MSG_EXT_WDTR_LEN; 881 sc->MsgBuf[3] = MSG_EXT_WDTR; 882 883 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 884 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_8_BIT; 885 else 886 sc->MsgBuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 887 888 sc->MsgCnt = 5; 889 890 } else if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 891 892 pDCB->DCBFlag &= ~TRM_SYNC_NEGO_ENABLE; 893 pDCB->DCBFlag |= TRM_DOING_SYNC_NEGO; 894 895 sc->MsgCnt = 0; 896 897 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_DONE) == 0) 898 sc->MsgBuf[sc->MsgCnt++] = pDCB->IdentifyMsg & ~MSG_IDENTIFY_DISCFLAG; 899 900 sc->MsgBuf[sc->MsgCnt++] = MSG_EXTENDED; 901 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR_LEN; 902 sc->MsgBuf[sc->MsgCnt++] = MSG_EXT_SDTR; 903 sc->MsgBuf[sc->MsgCnt++] = pDCB->MaxNegoPeriod; 904 905 if (pDCB->MaxNegoPeriod > 0) 906 sc->MsgBuf[sc->MsgCnt++] = TRM_MAX_SYNC_OFFSET; 907 else 908 sc->MsgBuf[sc->MsgCnt++] = 0; 909 } 910 911 if (sc->MsgCnt > 0) { 912 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &sc->MsgBuf[0], sc->MsgCnt); 913 if (sc->MsgBuf[0] == MSG_ABORT) 914 pSRB->SRBState = TRM_ABORT_SENT; 915 sc->MsgCnt = 0; 916 } 917 /* 918 * it's important for atn stop 919 */ 920 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 921 /* 922 * Transfer information out 923 */ 924 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 925 } 926 927 /* 928 * ------------------------------------------------------------ 929 * Function : trm_CommandPhase1 930 * Purpose : Send commands to bus 931 * Inputs : 932 * ------------------------------------------------------------ 933 */ 934 void 935 trm_CommandPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 936 { 937 const bus_space_handle_t ioh = sc->sc_iohandle; 938 const bus_space_tag_t iot = sc->sc_iotag; 939 940 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 941 942 bus_space_write_multi_1(iot, ioh, TRM_S1040_SCSI_FIFO, &pSRB->CmdBlock[0], pSRB->ScsiCmdLen); 943 944 pSRB->SRBState = TRM_COMMAND; 945 /* 946 * it's important for atn stop 947 */ 948 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 949 /* 950 * Transfer information out 951 */ 952 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_OUT); 953 } 954 955 /* 956 * ------------------------------------------------------------ 957 * Function : trm_DataOutPhase0 958 * Purpose : Ready for Data Out, clear FIFO 959 * Inputs : u_int8_t * - SCSI status, used but not set 960 * ------------------------------------------------------------ 961 */ 962 void 963 trm_DataOutPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 964 { 965 const bus_space_handle_t ioh = sc->sc_iohandle; 966 const bus_space_tag_t iot = sc->sc_iotag; 967 struct SGentry *pseg; 968 struct trm_dcb *pDCB; 969 u_int32_t dLeftCounter, TempSRBXferredLength; 970 u_int16_t scsi_status; 971 u_int8_t TempDMAstatus, SGIndexTemp; 972 973 dLeftCounter = 0; 974 975 pDCB = pSRB->pSRBDCB; 976 scsi_status = *pscsi_status; 977 978 if (pSRB->SRBState != TRM_XFERPAD) { 979 if ((scsi_status & PARITYERROR) != 0) 980 pSRB->SRBFlag |= TRM_PARITY_ERROR; 981 if ((scsi_status & SCSIXFERDONE) == 0) { 982 /* 983 * when data transfer from DMA FIFO to SCSI FIFO 984 * if there was some data left in SCSI FIFO 985 */ 986 dLeftCounter = (u_int32_t)(bus_space_read_1( 987 iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x1F); 988 if (pDCB->SyncPeriod & WIDE_SYNC) { 989 /* 990 * if WIDE scsi SCSI FIFOCNT unit is word 991 * so need to * 2 992 */ 993 dLeftCounter <<= 1; 994 } 995 } 996 /* 997 * calculate all the residue data that not yet transferred 998 * SCSI transfer counter + left in SCSI FIFO data 999 * 1000 * .....TRM_S1040_SCSI_COUNTER (24bits) 1001 * The counter always decrement by one for every SCSI byte 1002 * transfer. 1003 * .....TRM_S1040_SCSI_FIFOCNT ( 5bits) 1004 * The counter is SCSI FIFO offset counter 1005 */ 1006 dLeftCounter += bus_space_read_4(iot, ioh, 1007 TRM_S1040_SCSI_COUNTER); 1008 if (dLeftCounter == 1) { 1009 dLeftCounter = 0; 1010 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1011 DO_CLRFIFO); 1012 } 1013 if (dLeftCounter == 0 || 1014 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1015 TempDMAstatus = bus_space_read_1(iot, 1016 ioh, TRM_S1040_DMA_STATUS); 1017 while ((TempDMAstatus & DMAXFERCOMP) == 0) { 1018 TempDMAstatus = bus_space_read_1(iot, 1019 ioh, TRM_S1040_DMA_STATUS); 1020 } 1021 pSRB->SRBTotalXferLength = 0; 1022 } else { 1023 /* 1024 * Update SG list 1025 */ 1026 /* 1027 * if transfer not yet complete 1028 * there were some data residue in SCSI FIFO or 1029 * SCSI transfer counter not empty 1030 */ 1031 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1032 /* 1033 * data that had transferred length 1034 */ 1035 TempSRBXferredLength = pSRB->SRBTotalXferLength 1036 - dLeftCounter; 1037 /* 1038 * next time to be transferred length 1039 */ 1040 pSRB->SRBTotalXferLength = dLeftCounter; 1041 /* 1042 * parsing from last time disconnect SRBSGIndex 1043 */ 1044 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1045 for (SGIndexTemp = pSRB->SRBSGIndex; 1046 SGIndexTemp < pSRB->SRBSGCount; 1047 SGIndexTemp++) { 1048 /* 1049 * find last time which SG transfer be 1050 * disconnect 1051 */ 1052 if (TempSRBXferredLength >= pseg->length) 1053 TempSRBXferredLength -= pseg->length; 1054 else { 1055 /* 1056 * update last time disconnected 1057 * SG list 1058 */ 1059 /* 1060 * residue data length 1061 */ 1062 pseg->length -= 1063 TempSRBXferredLength; 1064 /* 1065 * residue data pointer 1066 */ 1067 pseg->address += 1068 TempSRBXferredLength; 1069 pSRB->SRBSGIndex = SGIndexTemp; 1070 break; 1071 } 1072 pseg++; 1073 } 1074 } 1075 } 1076 } 1077 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 1078 } 1079 1080 /* 1081 * ------------------------------------------------------------ 1082 * Function : trm_DataOutPhase1 1083 * Purpose : Transfers data out, calls trm_DataIO_transfer 1084 * Inputs : 1085 * ------------------------------------------------------------ 1086 */ 1087 void 1088 trm_DataOutPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1089 { 1090 trm_DataIO_transfer(sc, pSRB, XFERDATAOUT); 1091 } 1092 1093 /* 1094 * ------------------------------------------------------------ 1095 * Function : trm_DataInPhase0 1096 * Purpose : Prepare for reading data in from bus 1097 * Inputs : 1098 * ------------------------------------------------------------ 1099 */ 1100 void 1101 trm_DataInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1102 { 1103 const bus_space_handle_t ioh = sc->sc_iohandle; 1104 const bus_space_tag_t iot = sc->sc_iotag; 1105 struct SGentry *pseg; 1106 u_int32_t TempSRBXferredLength, dLeftCounter; 1107 u_int16_t scsi_status; 1108 u_int8_t SGIndexTemp; 1109 1110 dLeftCounter = 0; 1111 1112 scsi_status = *pscsi_status; 1113 if (pSRB->SRBState != TRM_XFERPAD) { 1114 if ((scsi_status & PARITYERROR) != 0) 1115 pSRB->SRBFlag |= TRM_PARITY_ERROR; 1116 dLeftCounter += bus_space_read_4(iot, ioh, 1117 TRM_S1040_SCSI_COUNTER); 1118 if (dLeftCounter == 0 || 1119 (scsi_status & SCSIXFERCNT_2_ZERO) != 0) { 1120 while ((bus_space_read_1(iot, ioh, TRM_S1040_DMA_STATUS) & DMAXFERCOMP) == 0) 1121 ; 1122 pSRB->SRBTotalXferLength = 0; 1123 } else { 1124 /* 1125 * phase changed 1126 * 1127 * parsing the case: 1128 * when a transfer not yet complete 1129 * but be disconnected by uper layer 1130 * if transfer not yet complete 1131 * there were some data residue in SCSI FIFO or 1132 * SCSI transfer counter not empty 1133 */ 1134 if (pSRB->SRBTotalXferLength != dLeftCounter) { 1135 /* 1136 * data that had transferred length 1137 */ 1138 TempSRBXferredLength = pSRB->SRBTotalXferLength 1139 - dLeftCounter; 1140 /* 1141 * next time to be transferred length 1142 */ 1143 pSRB->SRBTotalXferLength = dLeftCounter; 1144 /* 1145 * parsing from last time disconnect SRBSGIndex 1146 */ 1147 pseg = &pSRB->SegmentX[pSRB->SRBSGIndex]; 1148 for (SGIndexTemp = pSRB->SRBSGIndex; 1149 SGIndexTemp < pSRB->SRBSGCount; 1150 SGIndexTemp++) { 1151 /* 1152 * find last time which SG transfer be 1153 * disconnect 1154 */ 1155 if (TempSRBXferredLength >= 1156 pseg->length) { 1157 TempSRBXferredLength -= pseg->length; 1158 } else { 1159 /* 1160 * update last time disconnected 1161 * SG list 1162 * 1163 * residue data length 1164 */ 1165 pseg->length -= TempSRBXferredLength; 1166 /* 1167 * residue data pointer 1168 */ 1169 pseg->address += TempSRBXferredLength; 1170 pSRB->SRBSGIndex = SGIndexTemp; 1171 break; 1172 } 1173 pseg++; 1174 } 1175 } 1176 } 1177 } 1178 } 1179 1180 /* 1181 * ------------------------------------------------------------ 1182 * Function : trm_DataInPhase1 1183 * Purpose : Transfer data in from bus, calls trm_DataIO_transfer 1184 * Inputs : 1185 * ------------------------------------------------------------ 1186 */ 1187 void 1188 trm_DataInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1189 { 1190 trm_DataIO_transfer(sc, pSRB, XFERDATAIN); 1191 } 1192 1193 /* 1194 * ------------------------------------------------------------ 1195 * Function : trm_DataIO_transfer 1196 * Purpose : 1197 * Inputs : 1198 * ------------------------------------------------------------ 1199 */ 1200 void 1201 trm_DataIO_transfer(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int16_t ioDir) 1202 { 1203 const bus_space_handle_t ioh = sc->sc_iohandle; 1204 const bus_space_tag_t iot = sc->sc_iotag; 1205 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1206 u_int8_t bval; 1207 1208 if (pSRB->SRBSGIndex < pSRB->SRBSGCount) { 1209 if (pSRB->SRBTotalXferLength != 0) { 1210 /* 1211 * load what physical address of Scatter/Gather list 1212 * table want to be transfer 1213 */ 1214 pSRB->SRBState = TRM_DATA_XFER; 1215 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XHIGHADDR, 0); 1216 bus_space_write_4(iot, ioh, 1217 TRM_S1040_DMA_XLOWADDR, (pSRB->SRBSGPhyAddr + 1218 ((u_int32_t)pSRB->SRBSGIndex << 3))); 1219 /* 1220 * load how many bytes in the Scatter/Gather list table 1221 */ 1222 bus_space_write_4(iot, ioh, TRM_S1040_DMA_XCNT, 1223 ((u_int32_t)(pSRB->SRBSGCount - 1224 pSRB->SRBSGIndex) << 3)); 1225 /* 1226 * load total transfer length (24bits, 1227 * pSRB->SRBTotalXferLength) max value 16Mbyte 1228 */ 1229 bus_space_write_4(iot, ioh, 1230 TRM_S1040_SCSI_COUNTER, pSRB->SRBTotalXferLength); 1231 /* 1232 * Start DMA transfer 1233 */ 1234 bus_space_write_2(iot,ioh,TRM_S1040_DMA_COMMAND, ioDir); 1235 /* bus_space_write_2(iot, ioh, 1236 TRM_S1040_DMA_CONTROL, STARTDMAXFER);*/ 1237 /* 1238 * Set the transfer bus and direction 1239 */ 1240 bval = ioDir == XFERDATAOUT ? SCMD_DMA_OUT :SCMD_DMA_IN; 1241 } else { 1242 /* 1243 * xfer pad 1244 */ 1245 if (pSRB->SRBSGCount) 1246 pSRB->AdaptStatus = TRM_OVER_UNDER_RUN; 1247 1248 if (pDCB->SyncPeriod & WIDE_SYNC) { 1249 bus_space_write_4(iot, ioh, 1250 TRM_S1040_SCSI_COUNTER, 2); 1251 } else { 1252 bus_space_write_4(iot, ioh, 1253 TRM_S1040_SCSI_COUNTER, 1); 1254 } 1255 1256 if (ioDir == XFERDATAOUT) { 1257 bus_space_write_2(iot, 1258 ioh, TRM_S1040_SCSI_FIFO, 0); 1259 } else { 1260 bus_space_read_2(iot, 1261 ioh, TRM_S1040_SCSI_FIFO); 1262 } 1263 pSRB->SRBState = TRM_XFERPAD; 1264 /* 1265 * Set the transfer bus and direction 1266 */ 1267 bval = ioDir == XFERDATAOUT ? SCMD_FIFO_OUT : SCMD_FIFO_IN; 1268 } 1269 /* 1270 * it's important for atn stop 1271 */ 1272 bus_space_write_2(iot,ioh,TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1273 /* 1274 * Tell the bus to do the transfer 1275 */ 1276 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, bval); 1277 } 1278 } 1279 1280 /* 1281 * ------------------------------------------------------------ 1282 * Function : trm_StatusPhase0 1283 * Purpose : Update Target Status with data from SCSI FIFO 1284 * Inputs : u_int8_t * - Set to PH_BUS_FREE 1285 * ------------------------------------------------------------ 1286 */ 1287 void 1288 trm_StatusPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1289 { 1290 const bus_space_handle_t ioh = sc->sc_iohandle; 1291 const bus_space_tag_t iot = sc->sc_iotag; 1292 1293 pSRB->TargetStatus = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1294 1295 pSRB->SRBState = TRM_COMPLETED; 1296 /* 1297 * initial phase 1298 */ 1299 *pscsi_status = PH_BUS_FREE; 1300 /* 1301 * it's important for atn stop 1302 */ 1303 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1304 /* 1305 * Tell bus that the message was accepted 1306 */ 1307 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1308 } 1309 1310 /* 1311 * ------------------------------------------------------------ 1312 * Function : trm_StatusPhase1 1313 * Purpose : Clear FIFO of DMA and SCSI 1314 * Inputs : 1315 * ------------------------------------------------------------ 1316 */ 1317 void 1318 trm_StatusPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1319 { 1320 const bus_space_handle_t ioh = sc->sc_iohandle; 1321 const bus_space_tag_t iot = sc->sc_iotag; 1322 1323 if ((bus_space_read_2(iot, ioh, TRM_S1040_DMA_COMMAND) & 0x0001) != 0) { 1324 if ((bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFOCNT) & 0x40) 1325 == 0) { 1326 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, 1327 DO_CLRFIFO); 1328 } 1329 if ((bus_space_read_2(iot, ioh, 1330 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1331 bus_space_write_1(iot, ioh, 1332 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1333 } 1334 } else { 1335 if ((bus_space_read_2(iot, ioh, 1336 TRM_S1040_DMA_FIFOCNT) & 0x8000) == 0) { 1337 bus_space_write_1(iot, ioh, 1338 TRM_S1040_DMA_CONTROL, CLRXFIFO); 1339 } 1340 if ((bus_space_read_1(iot, ioh, 1341 TRM_S1040_SCSI_FIFOCNT) & 0x40) == 0) { 1342 bus_space_write_2(iot, ioh, 1343 TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1344 } 1345 } 1346 pSRB->SRBState = TRM_STATUS; 1347 /* 1348 * it's important for atn stop 1349 */ 1350 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1351 /* 1352 * Tell the bus that the command is complete 1353 */ 1354 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_COMP); 1355 } 1356 1357 /* 1358 * ------------------------------------------------------------ 1359 * Function : trm_MsgInPhase0 1360 * Purpose : 1361 * Inputs : 1362 * 1363 * extended message codes: 1364 * code description 1365 * ---- ----------- 1366 * 02h Reserved 1367 * 00h MODIFY DATA POINTER 1368 * 01h SYNCHRONOUS DATA TRANSFER REQUEST 1369 * 03h WIDE DATA TRANSFER REQUEST 1370 * 04h - 7Fh Reserved 1371 * 80h - FFh Vendor specific 1372 * 1373 * ------------------------------------------------------------ 1374 */ 1375 void 1376 trm_MsgInPhase0(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1377 { 1378 const bus_space_handle_t ioh = sc->sc_iohandle; 1379 const bus_space_tag_t iot = sc->sc_iotag; 1380 struct trm_dcb *pDCB; 1381 u_int8_t message_in_code, bIndex, message_in_tag_id; 1382 1383 pDCB = sc->pActiveDCB; 1384 1385 message_in_code = bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1386 1387 if (pSRB->SRBState != TRM_EXTEND_MSGIN) { 1388 switch (message_in_code) { 1389 case MSG_DISCONNECT: 1390 pSRB->SRBState = TRM_DISCONNECTED; 1391 break; 1392 1393 case MSG_EXTENDED: 1394 case MSG_SIMPLE_Q_TAG: 1395 case MSG_HEAD_OF_Q_TAG: 1396 case MSG_ORDERED_Q_TAG: 1397 pSRB->SRBState = TRM_EXTEND_MSGIN; 1398 /* 1399 * extended message (01h) 1400 */ 1401 bzero(&sc->MsgBuf[0], sizeof(sc->MsgBuf)); 1402 sc->MsgBuf[0] = message_in_code; 1403 sc->MsgCnt = 1; 1404 /* 1405 * extended message length (n) 1406 */ 1407 break; 1408 1409 case MSG_MESSAGE_REJECT: 1410 /* 1411 * Reject message 1412 */ 1413 if ((pDCB->DCBFlag & TRM_DOING_WIDE_NEGO) != 0) { 1414 /* 1415 * do wide nego reject 1416 */ 1417 pDCB = pSRB->pSRBDCB; 1418 1419 pDCB->DCBFlag &= ~TRM_DOING_WIDE_NEGO; 1420 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1421 1422 if ((pDCB->DCBFlag & TRM_SYNC_NEGO_ENABLE) != 0) { 1423 /* 1424 * Set ATN, in case ATN was clear 1425 */ 1426 pSRB->SRBState = TRM_MSGOUT; 1427 bus_space_write_2(iot, ioh, 1428 TRM_S1040_SCSI_CONTROL, DO_SETATN); 1429 } else { 1430 /* 1431 * Clear ATN 1432 */ 1433 bus_space_write_2(iot, ioh, 1434 TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1435 } 1436 1437 } else if ((pDCB->DCBFlag & TRM_DOING_SYNC_NEGO) != 0) { 1438 /* 1439 * do sync nego reject 1440 */ 1441 pDCB = pSRB->pSRBDCB; 1442 1443 pDCB->DCBFlag &= ~TRM_DOING_SYNC_NEGO; 1444 1445 pDCB->SyncPeriod = 0; 1446 pDCB->SyncOffset = 0; 1447 1448 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRATN); 1449 goto re_prog; 1450 } 1451 break; 1452 1453 case MSG_IGN_WIDE_RESIDUE: 1454 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1455 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_FIFO); 1456 break; 1457 1458 default: 1459 break; 1460 } 1461 1462 } else { 1463 1464 /* 1465 * We are collecting an extended message. Save the latest byte and then 1466 * check to see if the message is complete. If so, process it. 1467 */ 1468 sc->MsgBuf[sc->MsgCnt++] = message_in_code; 1469 #ifdef TRM_DEBUG0 1470 printf("%s: sc->MsgBuf = 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\n", 1471 sc->sc_device.dv_xname, 1472 sc->MsgBuf[0], sc->MsgBuf[1], sc->MsgBuf[2], sc->MsgBuf[3], sc->MsgBuf[4], sc->MsgBuf[5] ); 1473 #endif 1474 switch (sc->MsgBuf[0]) { 1475 case MSG_SIMPLE_Q_TAG: 1476 case MSG_HEAD_OF_Q_TAG: 1477 case MSG_ORDERED_Q_TAG: 1478 if (sc->MsgCnt == 2) { 1479 pSRB->SRBState = TRM_FREE; 1480 message_in_tag_id = sc->MsgBuf[1]; 1481 sc->MsgCnt = 0; 1482 TAILQ_FOREACH(pSRB, &sc->goingSRB, link) { 1483 if ((pSRB->pSRBDCB == pDCB) && (pSRB->TagNumber == message_in_tag_id)) 1484 break; 1485 } 1486 if ((pSRB != NULL) && (pSRB->SRBState == TRM_DISCONNECTED)) { 1487 pDCB->pActiveSRB = pSRB; 1488 pSRB->SRBState = TRM_DATA_XFER; 1489 } else { 1490 #ifdef TRM_DEBUG0 1491 printf("%s: TRM_UNEXPECT_RESEL!\n", 1492 sc->sc_device.dv_xname); 1493 #endif 1494 pSRB = &sc->SRB[0]; 1495 trm_srb_reinit(sc, pSRB); 1496 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1497 pDCB->pActiveSRB = pSRB; 1498 trm_EnableMsgOut(sc, MSG_ABORT_TAG); 1499 } 1500 } 1501 break; 1502 1503 case MSG_EXTENDED: 1504 /* TODO XXXX: Correctly handling target initiated negotiations? */ 1505 if ((sc->MsgBuf[2] == MSG_EXT_WDTR) && (sc->MsgCnt == 4)) { 1506 /* 1507 * ====================================== 1508 * WIDE DATA TRANSFER REQUEST 1509 * ====================================== 1510 * byte 0 : Extended message (01h) 1511 * byte 1 : Extended message length (02h) 1512 * byte 2 : WIDE DATA TRANSFER code (03h) 1513 * byte 3 : Transfer width exponent 1514 */ 1515 1516 pSRB->SRBState = TRM_FREE; 1517 pDCB->DCBFlag &= ~(TRM_WIDE_NEGO_ENABLE | TRM_DOING_WIDE_NEGO); 1518 1519 if (sc->MsgBuf[1] != MSG_EXT_WDTR_LEN) 1520 goto reject_offer; 1521 1522 switch (sc->MsgBuf[3]) { 1523 case MSG_EXT_WDTR_BUS_32_BIT: 1524 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) 1525 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1526 else 1527 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_16_BIT; 1528 break; 1529 1530 case MSG_EXT_WDTR_BUS_16_BIT: 1531 if ((pDCB->DCBFlag & TRM_WIDE_NEGO_16BIT) == 0) { 1532 sc->MsgBuf[3] = MSG_EXT_WDTR_BUS_8_BIT; 1533 break; 1534 } 1535 pDCB->SyncPeriod |= WIDE_SYNC; 1536 /* FALL THROUGH == ACCEPT OFFER */ 1537 1538 case MSG_EXT_WDTR_BUS_8_BIT: 1539 pSRB->SRBState = TRM_MSGOUT; 1540 pDCB->DCBFlag |= (TRM_SYNC_NEGO_ENABLE | TRM_WIDE_NEGO_DONE); 1541 1542 if (pDCB->MaxNegoPeriod == 0) { 1543 pDCB->SyncPeriod = 0; 1544 pDCB->SyncOffset = 0; 1545 goto re_prog; 1546 } 1547 break; 1548 1549 default: 1550 pDCB->DCBFlag &= ~TRM_WIDE_NEGO_ENABLE; 1551 pDCB->DCBFlag |= TRM_WIDE_NEGO_DONE; 1552 reject_offer: 1553 sc->MsgCnt = 1; 1554 sc->MsgBuf[0] = MSG_MESSAGE_REJECT; 1555 break; 1556 } 1557 1558 /* Echo accepted offer, or send revised offer */ 1559 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_SETATN); 1560 1561 } else if ((sc->MsgBuf[2] == MSG_EXT_SDTR) && (sc->MsgCnt == 5)) { 1562 /* 1563 * ================================= 1564 * SYNCHRONOUS DATA TRANSFER REQUEST 1565 * ================================= 1566 * byte 0 : Extended message (01h) 1567 * byte 1 : Extended message length (03) 1568 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 1569 * byte 3 : Transfer period factor 1570 * byte 4 : REQ/ACK offset 1571 */ 1572 1573 pSRB->SRBState = TRM_FREE; 1574 pDCB->DCBFlag &= ~(TRM_SYNC_NEGO_ENABLE | TRM_DOING_SYNC_NEGO); 1575 1576 if (sc->MsgBuf[1] != MSG_EXT_SDTR_LEN) 1577 goto reject_offer; 1578 1579 if ((sc->MsgBuf[3] == 0) || (sc->MsgBuf[4] == 0)) { 1580 /* 1581 * Asynchronous transfers 1582 */ 1583 pDCB->SyncPeriod = 0; 1584 pDCB->SyncOffset = 0; 1585 1586 } else { 1587 /* 1588 * Synchronous transfers 1589 */ 1590 /* 1591 * REQ/ACK offset 1592 */ 1593 pDCB->SyncOffset = sc->MsgBuf[4]; 1594 1595 for (bIndex = 0; bIndex < 7; bIndex++) 1596 if (sc->MsgBuf[3] <= trm_clock_period[bIndex]) 1597 break; 1598 1599 pDCB->SyncPeriod |= (bIndex | ALT_SYNC); 1600 } 1601 1602 re_prog: /* 1603 * program SCSI control register 1604 */ 1605 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1606 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1607 1608 trm_SetXferParams(sc, pDCB, (pDCB->DCBFlag & TRM_QUIRKS_VALID)); 1609 } 1610 break; 1611 1612 default: 1613 break; 1614 } 1615 } 1616 1617 /* 1618 * initial phase 1619 */ 1620 *pscsi_status = PH_BUS_FREE; 1621 /* 1622 * it's important for atn stop 1623 */ 1624 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1625 /* 1626 * Tell bus that the message was accepted 1627 */ 1628 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1629 } 1630 1631 /* 1632 * ------------------------------------------------------------ 1633 * Function : trm_MsgInPhase1 1634 * Purpose : Clear the FIFO 1635 * Inputs : 1636 * ------------------------------------------------------------ 1637 */ 1638 void 1639 trm_MsgInPhase1(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1640 { 1641 const bus_space_handle_t ioh = sc->sc_iohandle; 1642 const bus_space_tag_t iot = sc->sc_iotag; 1643 1644 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 1645 bus_space_write_4(iot, ioh, TRM_S1040_SCSI_COUNTER, 1); 1646 1647 /* 1648 * it's important for atn stop 1649 */ 1650 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1651 /* 1652 * SCSI command 1653 */ 1654 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_FIFO_IN); 1655 } 1656 1657 /* 1658 * ------------------------------------------------------------ 1659 * Function : trm_Nop 1660 * Purpose : EMPTY 1661 * Inputs : 1662 * ------------------------------------------------------------ 1663 */ 1664 void 1665 trm_Nop(struct trm_softc *sc, struct trm_scsi_req_q *pSRB, u_int8_t *pscsi_status) 1666 { 1667 } 1668 1669 /* 1670 * ------------------------------------------------------------ 1671 * Function : trm_SetXferParams 1672 * Purpose : Set the Sync period, offset and mode for each device that has 1673 * the same target as the given one (struct trm_dcb *) 1674 * Inputs : 1675 * ------------------------------------------------------------ 1676 */ 1677 void 1678 trm_SetXferParams(struct trm_softc *sc, struct trm_dcb *pDCB, int print_info) 1679 { 1680 struct trm_dcb *pDCBTemp; 1681 int lun, target; 1682 1683 /* 1684 * set all lun device's period, offset 1685 */ 1686 #ifdef TRM_DEBUG0 1687 printf("%s: trm_SetXferParams\n", sc->sc_device.dv_xname); 1688 #endif 1689 1690 target = pDCB->target; 1691 for(lun = 0; lun < TRM_MAX_LUNS; lun++) { 1692 pDCBTemp = sc->pDCB[target][lun]; 1693 if (pDCBTemp != NULL) { 1694 pDCBTemp->DevMode = pDCB->DevMode; 1695 pDCBTemp->MaxNegoPeriod = pDCB->MaxNegoPeriod; 1696 pDCBTemp->SyncPeriod = pDCB->SyncPeriod; 1697 pDCBTemp->SyncOffset = pDCB->SyncOffset; 1698 pDCBTemp->DCBFlag = pDCB->DCBFlag; 1699 } 1700 } 1701 1702 if (print_info) 1703 trm_print_info(sc, pDCB); 1704 } 1705 1706 /* 1707 * ------------------------------------------------------------ 1708 * Function : trm_Disconnect 1709 * Purpose : 1710 * Inputs : 1711 * 1712 * ---SCSI bus phase 1713 * PH_DATA_OUT 0x00 Data out phase 1714 * PH_DATA_IN 0x01 Data in phase 1715 * PH_COMMAND 0x02 Command phase 1716 * PH_STATUS 0x03 Status phase 1717 * PH_BUS_FREE 0x04 Invalid phase used as bus free 1718 * PH_BUS_FREE 0x05 Invalid phase used as bus free 1719 * PH_MSG_OUT 0x06 Message out phase 1720 * PH_MSG_IN 0x07 Message in phase 1721 * ------------------------------------------------------------ 1722 */ 1723 void 1724 trm_Disconnect(struct trm_softc *sc) 1725 { 1726 const bus_space_handle_t ioh = sc->sc_iohandle; 1727 struct trm_scsi_req_q *pSRB; 1728 const bus_space_tag_t iot = sc->sc_iotag; 1729 struct trm_dcb *pDCB; 1730 int j; 1731 1732 #ifdef TRM_DEBUG0 1733 printf("%s: trm_Disconnect\n", sc->sc_device.dv_xname); 1734 #endif 1735 1736 pDCB = sc->pActiveDCB; 1737 if (pDCB == NULL) { 1738 /* TODO: Why use a loop? Why not use DELAY(400)? */ 1739 for(j = 400; j > 0; --j) 1740 DELAY(1); /* 1 msec */ 1741 bus_space_write_2(iot, ioh, 1742 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1743 return; 1744 } 1745 1746 pSRB = pDCB->pActiveSRB; 1747 sc->pActiveDCB = NULL; 1748 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1749 bus_space_write_2(iot, ioh, 1750 TRM_S1040_SCSI_CONTROL, (DO_CLRFIFO | DO_HWRESELECT)); 1751 DELAY(100); 1752 1753 switch (pSRB->SRBState) { 1754 case TRM_UNEXPECT_RESEL: 1755 pSRB->SRBState = TRM_FREE; 1756 break; 1757 1758 case TRM_ABORT_SENT: 1759 trm_GoingSRB_Done(sc, pDCB); 1760 break; 1761 1762 case TRM_START: 1763 case TRM_MSGOUT: 1764 /* 1765 * Selection time out 1766 */ 1767 /* If not polling just keep trying until xs->stimeout expires */ 1768 if ((pSRB->xs->flags & SCSI_POLL) == 0) { 1769 trm_RewaitSRB(sc, pSRB); 1770 } else { 1771 pSRB->TargetStatus = TRM_SCSI_SELECT_TIMEOUT; 1772 goto disc1; 1773 } 1774 break; 1775 1776 case TRM_COMPLETED: 1777 disc1: 1778 /* 1779 * TRM_COMPLETED - remove id from mask of active tags 1780 */ 1781 pDCB->pActiveSRB = NULL; 1782 trm_FinishSRB(sc, pSRB); 1783 break; 1784 1785 default: 1786 break; 1787 } 1788 1789 trm_StartWaitingSRB(sc); 1790 } 1791 1792 /* 1793 * ------------------------------------------------------------ 1794 * Function : trm_Reselect 1795 * Purpose : 1796 * Inputs : 1797 * ------------------------------------------------------------ 1798 */ 1799 void 1800 trm_Reselect(struct trm_softc *sc) 1801 { 1802 const bus_space_handle_t ioh = sc->sc_iohandle; 1803 const bus_space_tag_t iot = sc->sc_iotag; 1804 struct trm_scsi_req_q *pSRB; 1805 struct trm_dcb *pDCB; 1806 u_int16_t RselTarLunId; 1807 u_int8_t target, lun; 1808 1809 #ifdef TRM_DEBUG0 1810 printf("%s: trm_Reselect\n", sc->sc_device.dv_xname); 1811 #endif 1812 1813 pDCB = sc->pActiveDCB; 1814 if (pDCB != NULL) { 1815 /* 1816 * Arbitration lost but Reselection win 1817 */ 1818 pSRB = pDCB->pActiveSRB; 1819 trm_RewaitSRB(sc, pSRB); 1820 } 1821 1822 /* 1823 * Read Reselected Target Id and LUN 1824 */ 1825 RselTarLunId = bus_space_read_2(iot, ioh, TRM_S1040_SCSI_TARGETID) & 0x1FFF; 1826 /* TODO XXXX: Make endian independent! */ 1827 target = RselTarLunId & 0xff; 1828 lun = (RselTarLunId >> 8) & 0xff; 1829 1830 #ifdef TRM_DEBUG0 1831 printf("%s: reselect - target = %d, lun = %d\n", 1832 sc->sc_device.dv_xname, target, lun); 1833 #endif 1834 1835 if ((target < TRM_MAX_TARGETS) && (lun < TRM_MAX_LUNS)) 1836 pDCB = sc->pDCB[target][lun]; 1837 else 1838 pDCB = NULL; 1839 1840 if (pDCB == NULL) 1841 printf("%s: reselect - target = %d, lun = %d not found\n", 1842 sc->sc_device.dv_xname, target, lun); 1843 1844 sc->pActiveDCB = pDCB; 1845 1846 /* TODO XXXX: This will crash if pDCB is ever NULL */ 1847 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) { 1848 pSRB = &sc->SRB[0]; 1849 pDCB->pActiveSRB = pSRB; 1850 } else { 1851 pSRB = pDCB->pActiveSRB; 1852 if (pSRB == NULL || (pSRB->SRBState != TRM_DISCONNECTED)) { 1853 /* 1854 * abort command 1855 */ 1856 pSRB = &sc->SRB[0]; 1857 pSRB->SRBState = TRM_UNEXPECT_RESEL; 1858 pDCB->pActiveSRB = pSRB; 1859 trm_EnableMsgOut(sc, MSG_ABORT); 1860 } else 1861 pSRB->SRBState = TRM_DATA_XFER; 1862 } 1863 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 1864 1865 /* 1866 * Program HA ID, target ID, period and offset 1867 */ 1868 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TARGETID, target); 1869 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, sc->sc_AdaptSCSIID); 1870 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_SYNC, pDCB->SyncPeriod); 1871 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, pDCB->SyncOffset); 1872 1873 /* 1874 * it's important for atn stop 1875 */ 1876 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_DATALATCH); 1877 DELAY(30); 1878 1879 /* 1880 * SCSI command 1881 * to rls the /ACK signal 1882 */ 1883 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_COMMAND, SCMD_MSGACCEPT); 1884 } 1885 1886 /* 1887 * ------------------------------------------------------------ 1888 * Function : trm_FinishSRB 1889 * Purpose : Complete execution of a SCSI command 1890 * Inputs : 1891 * ------------------------------------------------------------ 1892 */ 1893 void 1894 trm_FinishSRB(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 1895 { 1896 struct scsi_inquiry_data *ptr; 1897 struct scsi_sense_data *s1, *s2; 1898 struct scsi_xfer *xs = pSRB->xs; 1899 struct trm_dcb *pDCB = pSRB->pSRBDCB; 1900 int target, lun, intflag; 1901 1902 #ifdef TRM_DEBUG0 1903 printf("%s: trm_FinishSRB. sc = %p, pSRB = %p\n", 1904 sc->sc_device.dv_xname, sc, pSRB); 1905 #endif 1906 pDCB->DCBFlag &= ~TRM_QUEUE_FULL; 1907 1908 intflag = splbio(); 1909 if (pSRB->TagNumber != TRM_NO_TAG) { 1910 pSRB->pSRBDCB->TagMask &= ~(1 << pSRB->TagNumber); 1911 pSRB->TagNumber = TRM_NO_TAG; 1912 } 1913 /* SRB may have started & finished, or be waiting and timed out */ 1914 if ((pSRB->SRBFlag & TRM_ON_WAITING_SRB) != 0) { 1915 pSRB->SRBFlag &= ~TRM_ON_WAITING_SRB; 1916 TAILQ_REMOVE(&sc->waitingSRB, pSRB, link); 1917 } 1918 if ((pSRB->SRBFlag & TRM_ON_GOING_SRB) != 0) { 1919 pSRB->SRBFlag &= ~TRM_ON_GOING_SRB; 1920 TAILQ_REMOVE(&sc->goingSRB, pSRB, link); 1921 } 1922 splx(intflag); 1923 1924 if (xs == NULL) { 1925 return; 1926 } 1927 1928 timeout_del(&xs->stimeout); 1929 1930 xs->status = pSRB->TargetStatus; 1931 if (xs->datalen != 0) { 1932 bus_dmamap_sync(sc->sc_dmatag, pSRB->dmamapxfer, 1933 0, pSRB->dmamapxfer->dm_mapsize, 1934 (xs->flags & SCSI_DATA_IN) ? BUS_DMASYNC_POSTREAD : 1935 BUS_DMASYNC_POSTWRITE); 1936 bus_dmamap_unload(sc->sc_dmatag, pSRB->dmamapxfer); 1937 } 1938 1939 switch (xs->status) { 1940 case SCSI_INTERM_COND_MET: 1941 case SCSI_COND_MET: 1942 case SCSI_INTERM: 1943 case SCSI_OK: 1944 switch (pSRB->AdaptStatus) { 1945 case TRM_STATUS_GOOD: 1946 if ((pSRB->SRBFlag & TRM_PARITY_ERROR) != 0) { 1947 #ifdef TRM_DEBUG0 1948 sc_print_addr(xs->sc_link); 1949 printf(" trm_FinishSRB. TRM_PARITY_ERROR\n"); 1950 #endif 1951 xs->error = XS_DRIVER_STUFFUP; 1952 1953 } else if ((pSRB->SRBFlag & TRM_SCSI_TIMED_OUT) != 0) { 1954 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) == 0) 1955 xs->error = XS_TIMEOUT; 1956 else { 1957 bzero(&xs->sense, sizeof(xs->sense)); 1958 xs->status = SCSI_CHECK; 1959 xs->error = XS_SENSE; 1960 } 1961 1962 } else if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) { 1963 s1 = &pSRB->scsisense; 1964 s2 = &xs->sense; 1965 1966 *s2 = *s1; 1967 1968 xs->status = SCSI_CHECK; 1969 xs->error = XS_SENSE; 1970 1971 } else 1972 xs->error = XS_NOERROR; 1973 break; 1974 1975 case TRM_OVER_UNDER_RUN: 1976 #ifdef TRM_DEBUG0 1977 sc_print_addr(xs->sc_link); 1978 printf("trm_FinishSRB. TRM_OVER_UNDER_RUN\n"); 1979 #endif 1980 xs->error = XS_DRIVER_STUFFUP; 1981 break; 1982 1983 default: 1984 #ifdef TRM_DEBUG0 1985 sc_print_addr(xs->sc_link); 1986 printf("trm_FinishSRB. AdaptStatus Error = 0x%02x\n", 1987 pSRB->AdaptStatus); 1988 #endif 1989 xs->error = XS_DRIVER_STUFFUP; 1990 break; 1991 } 1992 break; 1993 1994 case SCSI_TERMINATED: 1995 case SCSI_ACA_ACTIVE: 1996 case SCSI_CHECK: 1997 if ((pSRB->SRBFlag & TRM_AUTO_REQSENSE) != 0) 1998 xs->error = XS_DRIVER_STUFFUP; 1999 else { 2000 trm_RequestSense(sc, pSRB); 2001 return; 2002 } 2003 break; 2004 2005 case SCSI_QUEUE_FULL: 2006 /* this says no more until someone completes */ 2007 pDCB->DCBFlag |= TRM_QUEUE_FULL; 2008 trm_RewaitSRB(sc, pSRB); 2009 return; 2010 2011 case SCSI_RESV_CONFLICT: 2012 case SCSI_BUSY: 2013 xs->error = XS_BUSY; 2014 break; 2015 2016 case TRM_SCSI_UNEXP_BUS_FREE: 2017 xs->status = SCSI_OK; 2018 xs->error = XS_DRIVER_STUFFUP; 2019 break; 2020 2021 case TRM_SCSI_BUS_RST_DETECTED: 2022 xs->status = SCSI_OK; 2023 xs->error = XS_RESET; 2024 break; 2025 2026 case TRM_SCSI_SELECT_TIMEOUT: 2027 xs->status = SCSI_OK; 2028 xs->error = XS_SELTIMEOUT; 2029 break; 2030 2031 default: 2032 xs->error = XS_DRIVER_STUFFUP; 2033 break; 2034 } 2035 2036 target = xs->sc_link->target; 2037 lun = xs->sc_link->lun; 2038 2039 if ((xs->flags & SCSI_POLL) != 0) { 2040 2041 if (xs->cmd.opcode == INQUIRY && pDCB->sc_link == NULL) { 2042 2043 ptr = (struct scsi_inquiry_data *) xs->data; 2044 2045 if ((xs->error != XS_NOERROR) || 2046 ((ptr->device & SID_QUAL_BAD_LU) == SID_QUAL_BAD_LU)) { 2047 #ifdef TRM_DEBUG0 2048 sc_print_addr(xs->sc_link); 2049 printf("trm_FinishSRB NO Device\n"); 2050 #endif 2051 free(pDCB, M_DEVBUF, 0); 2052 sc->pDCB[target][lun] = NULL; 2053 pDCB = NULL; 2054 2055 } else 2056 pDCB->sc_link = xs->sc_link; 2057 } 2058 } 2059 2060 /* 2061 * Notify cmd done 2062 */ 2063 #ifdef TRM_DEBUG0 2064 if ((xs->error != 0) || (xs->status != 0) || 2065 ((xs->flags & SCSI_POLL) != 0)) { 2066 sc_print_addr(xs->sc_link); 2067 printf("trm_FinishSRB. xs->cmd.opcode = 0x%02x, xs->error = %d, xs->status = %d\n", 2068 xs->cmd.opcode, xs->error, xs->status); 2069 } 2070 #endif 2071 2072 if (ISSET(xs->flags, SCSI_POLL)) 2073 SET(xs->flags, ITSDONE); 2074 else 2075 scsi_done(xs); 2076 } 2077 2078 /* 2079 * ------------------------------------------------------------ 2080 * Function : trm_srb_reinit 2081 * Purpose : 2082 * Inputs : 2083 * ------------------------------------------------------------ 2084 */ 2085 void 2086 trm_srb_reinit(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2087 { 2088 bzero(&pSRB->SegmentX[0], sizeof(pSRB->SegmentX)); 2089 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2090 bzero(&pSRB->scsisense, sizeof(pSRB->scsisense)); 2091 2092 pSRB->SRBTotalXferLength = 0; 2093 pSRB->SRBSGCount = 0; 2094 pSRB->SRBSGIndex = 0; 2095 pSRB->SRBFlag = 0; 2096 2097 pSRB->SRBState = TRM_FREE; 2098 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2099 pSRB->TargetStatus = SCSI_OK; 2100 pSRB->ScsiPhase = PH_BUS_FREE; /* SCSI bus free Phase */ 2101 2102 pSRB->xs = NULL; 2103 pSRB->pSRBDCB = NULL; 2104 } 2105 2106 /* 2107 * ------------------------------------------------------------ 2108 * Function : trm_srb_free 2109 * Purpose : 2110 * Inputs : 2111 * ------------------------------------------------------------ 2112 */ 2113 void 2114 trm_srb_free(void *xsc, void *xpSRB) 2115 { 2116 struct trm_softc *sc = xsc; 2117 struct trm_scsi_req_q *pSRB = xpSRB; 2118 2119 trm_srb_reinit(sc, pSRB); 2120 2121 if (pSRB != &sc->SRB[0]) { 2122 mtx_enter(&sc->sc_srb_mtx); 2123 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2124 mtx_leave(&sc->sc_srb_mtx); 2125 } 2126 } 2127 2128 /* 2129 * ------------------------------------------------------------ 2130 * Function : trm_GoingSRB_Done 2131 * Purpose : 2132 * Inputs : 2133 * ------------------------------------------------------------ 2134 */ 2135 void 2136 trm_GoingSRB_Done(struct trm_softc *sc, struct trm_dcb *pDCB) 2137 { 2138 struct trm_scsi_req_q *pSRB, *pNextSRB; 2139 2140 /* ASSUME we are inside a splbio()/splx() pair */ 2141 2142 pSRB = TAILQ_FIRST(&sc->goingSRB); 2143 while (pSRB != NULL) { 2144 /* 2145 * Need to save pNextSRB because trm_FinishSRB() puts 2146 * pSRB in freeSRB queue, and thus its links no longer 2147 * point to members of the goingSRB queue. This is why 2148 * TAILQ_FOREACH() will not work for this traversal. 2149 */ 2150 pNextSRB = TAILQ_NEXT(pSRB, link); 2151 if (pDCB == NULL || pSRB->pSRBDCB == pDCB) { 2152 /* TODO XXXX: Is TIMED_OUT the best state to report? */ 2153 pSRB->SRBFlag |= TRM_SCSI_TIMED_OUT; 2154 trm_FinishSRB(sc, pSRB); 2155 } 2156 pSRB = pNextSRB; 2157 } 2158 } 2159 2160 /* 2161 * ------------------------------------------------------------ 2162 * Function : trm_ResetSCSIBus 2163 * Purpose : Reset the SCSI bus 2164 * Inputs : struct trm_softc * - 2165 * ------------------------------------------------------------ 2166 */ 2167 void 2168 trm_ResetSCSIBus(struct trm_softc *sc) 2169 { 2170 const bus_space_handle_t ioh = sc->sc_iohandle; 2171 const bus_space_tag_t iot = sc->sc_iotag; 2172 int intflag; 2173 2174 intflag = splbio(); 2175 2176 sc->sc_Flag |= RESET_DEV; 2177 2178 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTSCSI); 2179 while ((bus_space_read_2(iot, ioh, 2180 TRM_S1040_SCSI_INTSTATUS) & INT_SCSIRESET) == 0); 2181 2182 splx(intflag); 2183 } 2184 2185 /* 2186 * ------------------------------------------------------------ 2187 * Function : trm_ScsiRstDetect 2188 * Purpose : 2189 * Inputs : 2190 * ------------------------------------------------------------ 2191 */ 2192 void 2193 trm_ScsiRstDetect(struct trm_softc *sc) 2194 { 2195 const bus_space_handle_t ioh = sc->sc_iohandle; 2196 const bus_space_tag_t iot = sc->sc_iotag; 2197 int wlval; 2198 2199 #ifdef TRM_DEBUG0 2200 printf("%s: trm_ScsiRstDetect\n", sc->sc_device.dv_xname); 2201 #endif 2202 2203 wlval = 1000; 2204 /* 2205 * delay 1 sec 2206 */ 2207 while (--wlval != 0) 2208 DELAY(1000); 2209 2210 bus_space_write_1(iot, ioh, TRM_S1040_DMA_CONTROL, STOPDMAXFER); 2211 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_CLRFIFO); 2212 2213 if ((sc->sc_Flag & RESET_DEV) != 0) 2214 sc->sc_Flag |= RESET_DONE; 2215 else { 2216 sc->sc_Flag |= RESET_DETECT; 2217 trm_ResetAllDevParam(sc); 2218 trm_RecoverSRB(sc); 2219 sc->pActiveDCB = NULL; 2220 sc->sc_Flag = 0; 2221 trm_StartWaitingSRB(sc); 2222 } 2223 } 2224 2225 /* 2226 * ------------------------------------------------------------ 2227 * Function : trm_RequestSense 2228 * Purpose : 2229 * Inputs : 2230 * ------------------------------------------------------------ 2231 */ 2232 void 2233 trm_RequestSense(struct trm_softc *sc, struct trm_scsi_req_q *pSRB) 2234 { 2235 pSRB->SRBFlag |= TRM_AUTO_REQSENSE; 2236 2237 /* 2238 * Status of initiator/target 2239 */ 2240 pSRB->AdaptStatus = TRM_STATUS_GOOD; 2241 pSRB->TargetStatus = SCSI_OK; 2242 /* 2243 * Status of initiator/target 2244 */ 2245 2246 pSRB->SegmentX[0].address = pSRB->scsisensePhyAddr; 2247 pSRB->SegmentX[0].length = sizeof(struct scsi_sense_data); 2248 pSRB->SRBTotalXferLength = sizeof(struct scsi_sense_data); 2249 pSRB->SRBSGCount = 1; 2250 pSRB->SRBSGIndex = 0; 2251 2252 bzero(&pSRB->CmdBlock[0], sizeof(pSRB->CmdBlock)); 2253 2254 pSRB->CmdBlock[0] = REQUEST_SENSE; 2255 pSRB->CmdBlock[1] = (pSRB->xs->sc_link->lun) << 5; 2256 pSRB->CmdBlock[4] = sizeof(struct scsi_sense_data); 2257 2258 pSRB->ScsiCmdLen = 6; 2259 2260 if ((pSRB->xs != NULL) && ((pSRB->xs->flags & SCSI_POLL) == 0)) 2261 timeout_add_msec(&pSRB->xs->stimeout, pSRB->xs->timeout); 2262 2263 if (trm_StartSRB(sc, pSRB) != 0) 2264 trm_RewaitSRB(sc, pSRB); 2265 } 2266 2267 /* 2268 * ------------------------------------------------------------ 2269 * Function : trm_EnableMsgOut 2270 * Purpose : set up MsgBuf to send out a single byte message 2271 * Inputs : 2272 * ------------------------------------------------------------ 2273 */ 2274 void 2275 trm_EnableMsgOut(struct trm_softc *sc, u_int8_t msg) 2276 { 2277 sc->MsgBuf[0] = msg; 2278 sc->MsgCnt = 1; 2279 2280 bus_space_write_2(sc->sc_iotag, sc->sc_iohandle, TRM_S1040_SCSI_CONTROL, DO_SETATN); 2281 } 2282 2283 /* 2284 * ------------------------------------------------------------ 2285 * Function : trm_linkSRB 2286 * Purpose : 2287 * Inputs : 2288 * ------------------------------------------------------------ 2289 */ 2290 void 2291 trm_linkSRB(struct trm_softc *sc) 2292 { 2293 struct trm_scsi_req_q *pSRB; 2294 int i, intflag; 2295 2296 intflag = splbio(); 2297 2298 for (i = 0; i < TRM_MAX_SRB_CNT; i++) { 2299 pSRB = &sc->SRB[i]; 2300 2301 pSRB->PhysSRB = sc->sc_dmamap_control->dm_segs[0].ds_addr 2302 + i * sizeof(struct trm_scsi_req_q); 2303 2304 pSRB->SRBSGPhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2305 + i * sizeof(struct trm_scsi_req_q) 2306 + offsetof(struct trm_scsi_req_q, SegmentX); 2307 2308 pSRB->scsisensePhyAddr = sc->sc_dmamap_control->dm_segs[0].ds_addr 2309 + i * sizeof(struct trm_scsi_req_q) 2310 + offsetof(struct trm_scsi_req_q, scsisense); 2311 2312 /* 2313 * map all SRB space 2314 */ 2315 if (bus_dmamap_create(sc->sc_dmatag, TRM_MAX_PHYSG_BYTE, 2316 TRM_MAX_SG_LISTENTRY, TRM_MAX_PHYSG_BYTE, 0, 2317 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, 2318 &pSRB->dmamapxfer) != 0) { 2319 printf("%s: unable to create DMA transfer map\n", 2320 sc->sc_device.dv_xname); 2321 splx(intflag); 2322 return; 2323 } 2324 2325 if (i > 0) 2326 /* We use sc->SRB[0] directly, so *don't* link it */ 2327 TAILQ_INSERT_TAIL(&sc->freeSRB, pSRB, link); 2328 #ifdef TRM_DEBUG0 2329 printf("pSRB = %p ", pSRB); 2330 #endif 2331 } 2332 #ifdef TRM_DEBUG0 2333 printf("\n "); 2334 #endif 2335 splx(intflag); 2336 } 2337 2338 /* 2339 * ------------------------------------------------------------ 2340 * Function : trm_initACB 2341 * Purpose : initialize the internal structures for a given SCSI host 2342 * Inputs : 2343 * ------------------------------------------------------------ 2344 */ 2345 void 2346 trm_initACB(struct trm_softc *sc, int unit) 2347 { 2348 const bus_space_handle_t ioh = sc->sc_iohandle; 2349 const bus_space_tag_t iot = sc->sc_iotag; 2350 struct trm_adapter_nvram *pEEpromBuf; 2351 struct trm_dcb *pDCB; 2352 int target, lun; 2353 2354 pEEpromBuf = &trm_eepromBuf[unit]; 2355 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 2356 2357 if ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & WIDESCSI) != 0) 2358 sc->sc_config |= HCC_WIDE_CARD; 2359 2360 if ((pEEpromBuf->NvramChannelCfg & NAC_POWERON_SCSI_RESET) != 0) 2361 sc->sc_config |= HCC_SCSI_RESET; 2362 2363 TAILQ_INIT(&sc->freeSRB); 2364 TAILQ_INIT(&sc->waitingSRB); 2365 TAILQ_INIT(&sc->goingSRB); 2366 2367 mtx_init(&sc->sc_srb_mtx, IPL_BIO); 2368 scsi_iopool_init(&sc->sc_iopool, sc, trm_srb_alloc, trm_srb_free); 2369 2370 sc->pActiveDCB = NULL; 2371 sc->sc_AdapterUnit = unit; 2372 sc->sc_AdaptSCSIID = pEEpromBuf->NvramScsiId; 2373 sc->sc_TagMaxNum = 2 << pEEpromBuf->NvramMaxTag; 2374 sc->sc_Flag = 0; 2375 2376 /* 2377 * put all SRB's (except [0]) onto the freeSRB list 2378 */ 2379 trm_linkSRB(sc); 2380 2381 /* 2382 * allocate DCB array 2383 */ 2384 for (target = 0; target < TRM_MAX_TARGETS; target++) { 2385 if (target == sc->sc_AdaptSCSIID) 2386 continue; 2387 2388 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2389 pDCB = (struct trm_dcb *)malloc(sizeof(struct trm_dcb), 2390 M_DEVBUF, M_NOWAIT | M_ZERO); 2391 sc->pDCB[target][lun] = pDCB; 2392 2393 if (pDCB == NULL) 2394 continue; 2395 2396 pDCB->target = target; 2397 pDCB->lun = lun; 2398 pDCB->pActiveSRB = NULL; 2399 } 2400 } 2401 2402 trm_reset(sc); 2403 } 2404 2405 /* 2406 * ------------------------------------------------------------ 2407 * Function : trm_write_all 2408 * Description : write pEEpromBuf 128 bytes to seeprom 2409 * Input : iot, ioh - chip's base address 2410 * Output : none 2411 * ------------------------------------------------------------ 2412 */ 2413 void 2414 trm_write_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2415 bus_space_handle_t ioh) 2416 { 2417 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2418 u_int8_t bAddr; 2419 2420 /* 2421 * Enable SEEPROM 2422 */ 2423 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2424 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2425 /* 2426 * Write enable 2427 */ 2428 trm_write_cmd(iot, ioh, 0x04, 0xFF); 2429 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2430 trm_wait_30us(iot, ioh); 2431 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2432 trm_set_data(iot, ioh, bAddr, *bpEeprom); 2433 /* 2434 * Write disable 2435 */ 2436 trm_write_cmd(iot, ioh, 0x04, 0x00); 2437 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2438 trm_wait_30us(iot, ioh); 2439 /* 2440 * Disable SEEPROM 2441 */ 2442 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2443 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2444 } 2445 2446 /* 2447 * ------------------------------------------------------------ 2448 * Function : trm_set_data 2449 * Description : write one byte to seeprom 2450 * Input : iot, ioh - chip's base address 2451 * bAddr - address of SEEPROM 2452 * bData - data of SEEPROM 2453 * Output : none 2454 * ------------------------------------------------------------ 2455 */ 2456 void 2457 trm_set_data(bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr, 2458 u_int8_t bData) 2459 { 2460 u_int8_t bSendData; 2461 int i; 2462 2463 /* 2464 * Send write command & address 2465 */ 2466 trm_write_cmd(iot, ioh, 0x05, bAddr); 2467 /* 2468 * Write data 2469 */ 2470 for (i = 0; i < 8; i++, bData <<= 1) { 2471 bSendData = NVR_SELECT; 2472 if ((bData & 0x80) != 0) { /* Start from bit 7 */ 2473 bSendData |= NVR_BITOUT; 2474 } 2475 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2476 trm_wait_30us(iot, ioh); 2477 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2478 (bSendData | NVR_CLOCK)); 2479 trm_wait_30us(iot, ioh); 2480 } 2481 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2482 trm_wait_30us(iot, ioh); 2483 /* 2484 * Disable chip select 2485 */ 2486 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2487 trm_wait_30us(iot, ioh); 2488 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2489 trm_wait_30us(iot, ioh); 2490 /* 2491 * Wait for write ready 2492 */ 2493 for (;;) { 2494 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2495 (NVR_SELECT | NVR_CLOCK)); 2496 trm_wait_30us(iot, ioh); 2497 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2498 trm_wait_30us(iot, ioh); 2499 if (bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM) & NVR_BITIN) 2500 break; 2501 } 2502 /* 2503 * Disable chip select 2504 */ 2505 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2506 } 2507 2508 /* 2509 * ------------------------------------------------------------ 2510 * Function : trm_read_all 2511 * Description : read seeprom 128 bytes to pEEpromBuf 2512 * Input : pEEpromBuf, iot, ioh - chip's base address 2513 * Output : none 2514 * ------------------------------------------------------------ 2515 */ 2516 void 2517 trm_read_all(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2518 bus_space_handle_t ioh) 2519 { 2520 u_int8_t *bpEeprom = (u_int8_t *)pEEpromBuf; 2521 u_int8_t bAddr; 2522 2523 /* 2524 * Enable SEEPROM 2525 */ 2526 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2527 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) | EN_EEPROM)); 2528 2529 for (bAddr = 0; bAddr < 128; bAddr++, bpEeprom++) 2530 *bpEeprom = trm_get_data(iot, ioh, bAddr); 2531 2532 /* 2533 * Disable SEEPROM 2534 */ 2535 bus_space_write_1(iot, ioh, TRM_S1040_GEN_CONTROL, 2536 (bus_space_read_1(iot, ioh, TRM_S1040_GEN_CONTROL) & ~EN_EEPROM)); 2537 } 2538 2539 /* 2540 * ------------------------------------------------------------ 2541 * Function : trm_get_data 2542 * Description : read one byte from seeprom 2543 * Input : iot, ioh - chip's base address 2544 * bAddr - address of SEEPROM 2545 * Output : bData - data of SEEPROM 2546 * ------------------------------------------------------------ 2547 */ 2548 u_int8_t 2549 trm_get_data( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bAddr) 2550 { 2551 u_int8_t bReadData, bData; 2552 int i; 2553 2554 bData = 0; 2555 2556 /* 2557 * Send read command & address 2558 */ 2559 trm_write_cmd(iot, ioh, 0x06, bAddr); 2560 2561 for (i = 0; i < 8; i++) { 2562 /* 2563 * Read data 2564 */ 2565 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2566 (NVR_SELECT | NVR_CLOCK)); 2567 trm_wait_30us(iot, ioh); 2568 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2569 /* 2570 * Get data bit while falling edge 2571 */ 2572 bReadData = bus_space_read_1(iot, ioh, TRM_S1040_GEN_NVRAM); 2573 bData <<= 1; 2574 if ((bReadData & NVR_BITIN) != 0) 2575 bData |= 1; 2576 trm_wait_30us(iot, ioh); 2577 } 2578 /* 2579 * Disable chip select 2580 */ 2581 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 0); 2582 2583 return bData; 2584 } 2585 2586 /* 2587 * ------------------------------------------------------------ 2588 * Function : trm_wait_30us 2589 * Description : wait 30 us 2590 * Input : iot, ioh - chip's base address 2591 * Output : none 2592 * ------------------------------------------------------------ 2593 */ 2594 void 2595 trm_wait_30us(bus_space_tag_t iot, bus_space_handle_t ioh) 2596 { 2597 bus_space_write_1(iot, ioh, TRM_S1040_GEN_TIMER, 5); 2598 2599 while ((bus_space_read_1(iot, ioh, TRM_S1040_GEN_STATUS) & GTIMEOUT) 2600 == 0); 2601 } 2602 2603 /* 2604 * ------------------------------------------------------------ 2605 * Function : trm_write_cmd 2606 * Description : write SB and Op Code into seeprom 2607 * Input : iot, ioh - chip's base address 2608 * bCmd - SB + Op Code 2609 * bAddr - address of SEEPROM 2610 * Output : none 2611 * ------------------------------------------------------------ 2612 */ 2613 void 2614 trm_write_cmd( bus_space_tag_t iot, bus_space_handle_t ioh, u_int8_t bCmd, 2615 u_int8_t bAddr) 2616 { 2617 u_int8_t bSendData; 2618 int i; 2619 2620 for (i = 0; i < 3; i++, bCmd <<= 1) { 2621 /* 2622 * Program SB + OP code 2623 */ 2624 bSendData = NVR_SELECT; 2625 if (bCmd & 0x04) /* Start from bit 2 */ 2626 bSendData |= NVR_BITOUT; 2627 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2628 trm_wait_30us(iot, ioh); 2629 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2630 (bSendData | NVR_CLOCK)); 2631 trm_wait_30us(iot, ioh); 2632 } 2633 2634 for (i = 0; i < 7; i++, bAddr <<= 1) { 2635 /* 2636 * Program address 2637 */ 2638 bSendData = NVR_SELECT; 2639 if (bAddr & 0x40) { /* Start from bit 6 */ 2640 bSendData |= NVR_BITOUT; 2641 } 2642 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, bSendData); 2643 trm_wait_30us(iot, ioh); 2644 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, 2645 (bSendData | NVR_CLOCK)); 2646 trm_wait_30us(iot, ioh); 2647 } 2648 bus_space_write_1(iot, ioh, TRM_S1040_GEN_NVRAM, NVR_SELECT); 2649 trm_wait_30us(iot, ioh); 2650 } 2651 2652 /* 2653 * ------------------------------------------------------------ 2654 * Function : trm_check_eeprom 2655 * Description : read eeprom 128 bytes to pEEpromBuf and check 2656 * checksum. If it is wrong, updated with default value. 2657 * Input : eeprom, iot, ioh - chip's base address 2658 * Output : none 2659 * ------------------------------------------------------------ 2660 */ 2661 void 2662 trm_check_eeprom(struct trm_adapter_nvram *pEEpromBuf, bus_space_tag_t iot, 2663 bus_space_handle_t ioh) 2664 { 2665 u_int32_t *dpEeprom = (u_int32_t *)pEEpromBuf->NvramTarget; 2666 u_int32_t dAddr; 2667 u_int16_t *wpEeprom = (u_int16_t *)pEEpromBuf; 2668 u_int16_t wAddr, wCheckSum; 2669 2670 #ifdef TRM_DEBUG0 2671 printf("\ntrm_check_eeprom\n"); 2672 #endif 2673 trm_read_all(pEEpromBuf, iot, ioh); 2674 wCheckSum = 0; 2675 for (wAddr = 0; wAddr < 64; wAddr++, wpEeprom++) 2676 wCheckSum += *wpEeprom; 2677 2678 if (wCheckSum != 0x1234) { 2679 #ifdef TRM_DEBUG0 2680 printf("TRM_S1040 EEPROM Check Sum ERROR (load default)\n"); 2681 #endif 2682 /* 2683 * Checksum error, load default 2684 */ 2685 pEEpromBuf->NvramSubVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2686 pEEpromBuf->NvramSubVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2687 >> 8); 2688 pEEpromBuf->NvramSubSysID[0] = (u_int8_t) 2689 PCI_PRODUCT_TEKRAM2_DC3X5U; 2690 pEEpromBuf->NvramSubSysID[1] = (u_int8_t) 2691 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2692 pEEpromBuf->NvramSubClass = 0; 2693 pEEpromBuf->NvramVendorID[0] = (u_int8_t)PCI_VENDOR_TEKRAM2; 2694 pEEpromBuf->NvramVendorID[1] = (u_int8_t)(PCI_VENDOR_TEKRAM2 2695 >> 8); 2696 pEEpromBuf->NvramDeviceID[0] = (u_int8_t) 2697 PCI_PRODUCT_TEKRAM2_DC3X5U; 2698 pEEpromBuf->NvramDeviceID[1] = (u_int8_t) 2699 (PCI_PRODUCT_TEKRAM2_DC3X5U >> 8); 2700 pEEpromBuf->NvramReserved = 0; 2701 2702 for (dAddr = 0; dAddr < 16; dAddr++, dpEeprom++) 2703 /* 2704 * NvmTarCfg3,NvmTarCfg2,NvmTarPeriod,NvmTarCfg0 2705 */ 2706 *dpEeprom = 0x00000077; 2707 2708 /* 2709 * NvramMaxTag,NvramDelayTime,NvramChannelCfg,NvramScsiId 2710 */ 2711 *dpEeprom++ = 0x04000F07; 2712 2713 /* 2714 * NvramReserved1,NvramBootLun,NvramBootTarget,NvramReserved0 2715 */ 2716 *dpEeprom++ = 0x00000015; 2717 for (dAddr = 0; dAddr < 12; dAddr++, dpEeprom++) 2718 *dpEeprom = 0; 2719 2720 pEEpromBuf->NvramCheckSum = 0; 2721 for (wAddr = 0, wCheckSum =0; wAddr < 63; wAddr++, wpEeprom++) 2722 wCheckSum += *wpEeprom; 2723 2724 *wpEeprom = 0x1234 - wCheckSum; 2725 trm_write_all(pEEpromBuf, iot, ioh); 2726 } 2727 } 2728 2729 /* 2730 * ------------------------------------------------------------ 2731 * Function : trm_initAdapter 2732 * Purpose : initialize the SCSI chip ctrl registers 2733 * Inputs : psh - pointer to this host adapter's structure 2734 * ------------------------------------------------------------ 2735 */ 2736 void 2737 trm_initAdapter(struct trm_softc *sc) 2738 { 2739 const bus_space_handle_t ioh = sc->sc_iohandle; 2740 const bus_space_tag_t iot = sc->sc_iotag; 2741 u_int16_t wval; 2742 u_int8_t bval; 2743 2744 /* 2745 * program configuration 0 2746 */ 2747 if ((sc->sc_config & HCC_PARITY) != 0) { 2748 bval = PHASELATCH | INITIATOR | BLOCKRST | PARITYCHECK; 2749 } else { 2750 bval = PHASELATCH | INITIATOR | BLOCKRST; 2751 } 2752 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG0, bval); 2753 /* 2754 * program configuration 1 2755 */ 2756 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_CONFIG1, 0x13); 2757 /* 2758 * 250ms selection timeout 2759 */ 2760 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_TIMEOUT, TRM_SEL_TIMEOUT); 2761 /* 2762 * Mask all the interrupt 2763 */ 2764 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, 0); 2765 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 0); 2766 /* 2767 * Reset SCSI module 2768 */ 2769 bus_space_write_2(iot, ioh, TRM_S1040_SCSI_CONTROL, DO_RSTMODULE); 2770 /* 2771 * program Host ID 2772 */ 2773 bval = sc->sc_AdaptSCSIID; 2774 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_HOSTID, bval); 2775 /* 2776 * set asynchronous transfer 2777 */ 2778 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_OFFSET, 0); 2779 /* 2780 * Turn LED control off 2781 */ 2782 wval = bus_space_read_2(iot, ioh, TRM_S1040_GEN_CONTROL) & 0x7F; 2783 bus_space_write_2(iot, ioh, TRM_S1040_GEN_CONTROL, wval); 2784 /* 2785 * DMA config 2786 */ 2787 wval = bus_space_read_2(iot, ioh, TRM_S1040_DMA_CONFIG) | DMA_ENHANCE; 2788 bus_space_write_2(iot, ioh, TRM_S1040_DMA_CONFIG, wval); 2789 /* 2790 * Clear pending interrupt status 2791 */ 2792 bus_space_read_1(iot, ioh, TRM_S1040_SCSI_INTSTATUS); 2793 /* 2794 * Enable SCSI interrupts 2795 */ 2796 bus_space_write_1(iot, ioh, TRM_S1040_SCSI_INTEN, 2797 (EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 2798 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE)); 2799 bus_space_write_1(iot, ioh, TRM_S1040_DMA_INTEN, EN_SCSIINTR); 2800 } 2801 2802 /* 2803 * ------------------------------------------------------------ 2804 * Function : trm_init 2805 * Purpose : initialize the internal structures for a given SCSI host 2806 * Inputs : host - pointer to this host adapter's structure 2807 * Preconditions : when this function is called, the chip_type field of 2808 * the ACB structure MUST have been set. 2809 * ------------------------------------------------------------ 2810 */ 2811 int 2812 trm_init(struct trm_softc *sc, int unit) 2813 { 2814 const bus_space_handle_t ioh = sc->sc_iohandle; 2815 const bus_space_tag_t iot = sc->sc_iotag; 2816 bus_dma_segment_t seg; 2817 int error, rseg, all_srbs_size; 2818 2819 /* 2820 * EEPROM CHECKSUM 2821 */ 2822 trm_check_eeprom(&trm_eepromBuf[unit], iot, ioh); 2823 2824 /* 2825 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK 2826 */ 2827 /* 2828 * allocate the space for all SCSI control blocks (SRB) for DMA memory. 2829 */ 2830 all_srbs_size = TRM_MAX_SRB_CNT * sizeof(struct trm_scsi_req_q); 2831 2832 error = bus_dmamem_alloc(sc->sc_dmatag, all_srbs_size, NBPG, 0, &seg, 2833 1, &rseg, BUS_DMA_NOWAIT | BUS_DMA_ZERO); 2834 if (error != 0) { 2835 printf("%s: unable to allocate SCSI REQUEST BLOCKS, error = %d\n", 2836 sc->sc_device.dv_xname, error); 2837 /*errx(error, "%s: unable to allocate SCSI request blocks", 2838 sc->sc_device.dv_xname);*/ 2839 return -1; 2840 } 2841 2842 error = bus_dmamem_map(sc->sc_dmatag, &seg, rseg, all_srbs_size, 2843 (caddr_t *)&sc->SRB, BUS_DMA_NOWAIT|BUS_DMA_COHERENT); 2844 if (error != 0) { 2845 printf("%s: unable to map SCSI REQUEST BLOCKS, error = %d\n", 2846 sc->sc_device.dv_xname, error); 2847 /*errx(error, "unable to map SCSI request blocks");*/ 2848 return -1; 2849 } 2850 2851 error = bus_dmamap_create(sc->sc_dmatag, all_srbs_size, 1, 2852 all_srbs_size, 0, BUS_DMA_NOWAIT,&sc->sc_dmamap_control); 2853 if (error != 0) { 2854 printf("%s: unable to create SRB DMA maps, error = %d\n", 2855 sc->sc_device.dv_xname, error); 2856 /*errx(error, "unable to create SRB DMA maps");*/ 2857 return -1; 2858 } 2859 2860 error = bus_dmamap_load(sc->sc_dmatag, sc->sc_dmamap_control, 2861 sc->SRB, all_srbs_size, NULL, BUS_DMA_NOWAIT); 2862 if (error != 0) { 2863 printf("%s: unable to load SRB DMA maps, error = %d\n", 2864 sc->sc_device.dv_xname, error); 2865 /*errx(error, "unable to load SRB DMA maps");*/ 2866 return -1; 2867 } 2868 #ifdef TRM_DEBUG0 2869 printf("\n\n%s: all_srbs_size=%x\n", 2870 sc->sc_device.dv_xname, all_srbs_size); 2871 #endif 2872 trm_initACB(sc, unit); 2873 trm_initAdapter(sc); 2874 2875 return 0; 2876 } 2877 2878 /* ------------------------------------------------------------ 2879 * Function : trm_print_info 2880 * Purpose : Print the DCB negotiation information 2881 * Inputs : 2882 * ------------------------------------------------------------ 2883 */ 2884 void 2885 trm_print_info(struct trm_softc *sc, struct trm_dcb *pDCB) 2886 { 2887 int syncXfer, index; 2888 2889 index = pDCB->SyncPeriod & ~(WIDE_SYNC | ALT_SYNC); 2890 2891 printf("%s: target %d using ", sc->sc_device.dv_xname, pDCB->target); 2892 if ((pDCB->SyncPeriod & WIDE_SYNC) != 0) 2893 printf("16 bit "); 2894 else 2895 printf("8 bit "); 2896 2897 if (pDCB->SyncOffset == 0) 2898 printf("Asynchronous "); 2899 else { 2900 syncXfer = 100000 / (trm_clock_period[index] * 4); 2901 printf("%d.%01d MHz, Offset %d ", 2902 syncXfer / 100, syncXfer % 100, pDCB->SyncOffset); 2903 } 2904 printf("data transfers "); 2905 2906 if ((pDCB->DCBFlag & TRM_USE_TAG_QUEUING) != 0) 2907 printf("with Tag Queuing"); 2908 2909 printf("\n"); 2910 }
Cache object: b67e9584710e0fb88ea0f5535554dbe0
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