Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ic/trm.h
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1 /* $OpenBSD: trm.h,v 1.7 2020/07/22 13:16:04 krw Exp $ 2 * ------------------------------------------------------------ 3 * O.S : OpenBSD 4 * File Name : trm.h 5 * Device Driver for Tekram DC395U/UW/F,DC315/U 6 * PCI SCSI Bus Master Host Adapter 7 * (SCSI chip set used Tekram ASIC TRM-S1040) 8 * 9 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. 10 * (C)Copyright 2001-2002 Ashley R. Martens and Kenneth R Westerback 11 * ------------------------------------------------------------ 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * ------------------------------------------------------------ 34 */ 35 36 #ifndef _TRM_H 37 #define _TRM_H 38 39 /* 40 * ------------------------------------------------------------ 41 * Segment Entry 42 * ------------------------------------------------------------ 43 */ 44 struct SGentry 45 { 46 u_int32_t address; 47 u_int32_t length; 48 }; 49 50 /* 51 * ----------------------------------------------------------------------- 52 * feature of chip set MAX value 53 * ----------------------------------------------------------------------- 54 */ 55 56 #define TRM_MAX_ADAPTER_NUM 4 57 #define TRM_MAX_TARGETS 16 58 #define TRM_MAX_LUNS 8 59 #define TRM_MAX_SG_LISTENTRY 32 60 #define TRM_MAX_CMD_PER_LUN 32 61 #define TRM_MAX_SRB_CNT TRM_MAX_CMD_PER_LUN*4 62 #define TRM_MAX_PHYSG_BYTE ((TRM_MAX_SG_LISTENTRY - 1) << PGSHIFT) 63 #define TRM_MAX_SYNC_OFFSET 15 64 #define TRM_SEL_TIMEOUT 153 /* 250 ms selection timeout (@40MHz) */ 65 66 /* 67 *----------------------------------------------------------------------- 68 * SCSI Request Block 69 *----------------------------------------------------------------------- 70 */ 71 struct trm_scsi_req_q 72 { 73 TAILQ_ENTRY(trm_scsi_req_q) link; 74 bus_dmamap_t dmamapxfer; 75 u_int32_t PhysSRB; 76 u_int32_t SRBTotalXferLength; 77 u_int32_t SRBSGPhyAddr; /* a segment starting address */ 78 79 u_int16_t SRBState; /* State machine */ 80 #define TRM_FREE 0x0000 81 #define TRM_WAIT 0x0001 82 #define TRM_READY 0x0002 83 #define TRM_MSGOUT 0x0004 /*arbitration+msg_out 1st byte */ 84 #define TRM_EXTEND_MSGIN 0x0010 85 #define TRM_COMMAND 0x0020 86 #define TRM_START 0x0040 /*arbitration+msg_out+command_out */ 87 #define TRM_DISCONNECTED 0x0080 88 #define TRM_DATA_XFER 0x0100 89 #define TRM_XFERPAD 0x0200 90 #define TRM_STATUS 0x0400 91 #define TRM_COMPLETED 0x0800 92 #define TRM_ABORT_SENT 0x1000 93 #define TRM_UNEXPECT_RESEL 0x8000 94 95 u_int8_t AdaptStatus; 96 #define TRM_STATUS_GOOD 0x00 97 #define TRM_SELECTION_TIMED_OUT 0x11 98 #define TRM_OVER_UNDER_RUN 0x12 99 #define TRM_UNEXP_BUS_FREE 0x13 100 #define TRM_TARGET_PHASE_F 0x14 101 #define TRM_INVALID_CCB_OP 0x16 102 #define TRM_LINK_CCB_BAD 0x17 103 #define TRM_BAD_TARGET_DIR 0x18 104 #define TRM_DUPLICATE_CCB 0x19 105 #define TRM_BAD_CCB_OR_SG 0x1A 106 #define TRM_ABORT 0xFF 107 108 u_int8_t CmdBlock[16]; 109 110 u_int8_t ScsiCmdLen; 111 u_int8_t ScsiPhase; 112 113 u_int8_t SRBFlag; 114 #define TRM_AUTO_REQSENSE 0x01 115 #define TRM_SCSI_TIMED_OUT 0x02 116 #define TRM_PARITY_ERROR 0x04 117 #define TRM_ON_GOING_SRB 0x08 118 #define TRM_ON_WAITING_SRB 0x10 119 120 u_int8_t SRBSGCount; 121 u_int8_t SRBSGIndex; 122 u_int8_t TagNumber; 123 #define TRM_NO_TAG 0x00 124 125 u_int8_t TargetStatus; /* SCSI status codes + Tekram: */ 126 #define TRM_SCSI_UNEXP_BUS_FREE 0xFD /* Unexpect Bus Free */ 127 #define TRM_SCSI_BUS_RST_DETECTED 0xFE /* Scsi Bus Reset detected */ 128 #define TRM_SCSI_SELECT_TIMEOUT 0xFF /* Selection Time out */ 129 130 struct trm_dcb *pSRBDCB; 131 132 struct SGentry SegmentX[TRM_MAX_SG_LISTENTRY]; 133 134 struct scsi_xfer *xs; 135 136 struct scsi_sense_data scsisense; 137 u_int32_t scsisensePhyAddr; 138 }; 139 140 TAILQ_HEAD(SRB_HEAD, trm_scsi_req_q); 141 142 /* 143 *----------------------------------------------------------------------- 144 * Device Control Block 145 *----------------------------------------------------------------------- 146 */ 147 struct trm_dcb 148 { 149 u_int32_t TagMask; 150 151 u_int16_t DCBFlag; 152 #define TRM_WIDE_NEGO_ENABLE 0x0001 153 #define TRM_DOING_WIDE_NEGO 0x0002 154 #define TRM_WIDE_NEGO_DONE 0x0004 155 #define TRM_SYNC_NEGO_ENABLE 0x0008 156 #define TRM_DOING_SYNC_NEGO 0x0010 157 #define TRM_USE_TAG_QUEUING 0x0020 158 #define TRM_QUEUE_FULL 0x0040 159 #define TRM_WIDE_NEGO_16BIT 0x0080 160 #define TRM_QUIRKS_VALID 0x0100 161 #define TRM_BAD_DCB 0x0200 162 163 u_int8_t DevMode; /* trm_target_nvram.NvmTarCfg0 */ 164 165 u_int8_t MaxNegoPeriod; /* Maximum allow sync period */ 166 u_int8_t SyncPeriod; /* Current sync period */ 167 u_int8_t SyncOffset; /* Current sync offset */ 168 169 u_int8_t target; /* SCSI Target ID */ 170 u_int8_t lun; /* SCSI Logical Unit Number */ 171 172 u_int8_t IdentifyMsg; 173 174 struct scsi_link *sc_link; 175 struct trm_scsi_req_q *pActiveSRB; 176 }; 177 178 /* 179 *----------------------------------------------------------------------- 180 * Adapter Control Block 181 *----------------------------------------------------------------------- 182 */ 183 struct trm_softc 184 { 185 struct device sc_device; 186 187 bus_space_handle_t sc_iohandle; 188 bus_space_tag_t sc_iotag; 189 bus_dma_tag_t sc_dmatag; 190 bus_dmamap_t sc_dmamap_control; /* map the control structures */ 191 192 u_int16_t sc_AdapterUnit; /* nth Adapter this driver */ 193 194 u_int8_t sc_AdaptSCSIID; /* Adapter SCSI Target ID */ 195 u_int8_t sc_TagMaxNum; 196 197 u_int8_t sc_config; 198 #define HCC_WIDE_CARD 0x20 199 #define HCC_SCSI_RESET 0x10 200 #define HCC_PARITY 0x08 201 #define HCC_AUTOTERM 0x04 202 #define HCC_LOW8TERM 0x02 203 #define HCC_UP8TERM 0x01 204 205 u_int8_t sc_Flag; 206 #define RESET_DEV 0x01 207 #define RESET_DETECT 0x02 208 #define RESET_DONE 0x04 209 210 u_int8_t MsgCnt; 211 u_int8_t MsgBuf[6]; 212 213 struct SRB_HEAD freeSRB; 214 struct SRB_HEAD goingSRB; 215 struct SRB_HEAD waitingSRB; 216 217 struct mutex sc_srb_mtx; 218 struct scsi_iopool sc_iopool; 219 220 struct trm_dcb *pActiveDCB; 221 struct trm_dcb *pDCB[TRM_MAX_TARGETS][TRM_MAX_LUNS]; 222 223 struct trm_scsi_req_q *SRB; 224 }; 225 226 /* 227 * The SEEPROM structure for TRM_S1040 228 */ 229 struct trm_target_nvram 230 { 231 u_int8_t NvmTarCfg0; /* Target configuration byte 0 */ 232 #define TRM_WIDE 0x20 /* Wide negotiate */ 233 #define TRM_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */ 234 #define TRM_SEND_START 0x08 /* Send start command SPINUP */ 235 #define TRM_DISCONNECT 0x04 /* Enable SCSI disconnect */ 236 #define TRM_SYNC 0x02 /* Sync negotiation */ 237 #define TRM_PARITY 0x01 /* (it should be defined at NAC ) */ 238 239 u_int8_t NvmTarPeriod; /* Target period */ 240 u_int8_t NvmTarCfg2; /* Target configuration byte 2 */ 241 u_int8_t NvmTarCfg3; /* Target configuration byte 3 */ 242 }; 243 244 struct trm_adapter_nvram 245 { 246 u_int8_t NvramSubVendorID[2]; /*0,1 Sub Vendor ID */ 247 u_int8_t NvramSubSysID[2]; /*2,3 Sub System ID */ 248 u_int8_t NvramSubClass; /*4 Sub Class */ 249 u_int8_t NvramVendorID[2]; /*5,6 Vendor ID */ 250 u_int8_t NvramDeviceID[2]; /*7,8 Device ID */ 251 u_int8_t NvramReserved; /*9 Reserved */ 252 struct trm_target_nvram NvramTarget[TRM_MAX_TARGETS]; /* 10 */ 253 u_int8_t NvramScsiId; /*74 Host Adapter SCSI ID */ 254 u_int8_t NvramChannelCfg; /*75 Channel configuration */ 255 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 256 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 257 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 258 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 259 u_int8_t NvramDelayTime; /*76 Power on delay time */ 260 u_int8_t NvramMaxTag; /*77 Maximum tags */ 261 u_int8_t NvramReserved0; /*78 */ 262 u_int8_t NvramBootTarget; /*79 */ 263 u_int8_t NvramBootLun; /*80 */ 264 u_int8_t NvramReserved1; /*81 */ 265 u_int16_t Reserved[22]; /*82,..125 */ 266 u_int16_t NvramCheckSum; /*126,127 */ 267 }; 268 269 /* 270 * The PCI configuration register offsets for the TRM_S1040, and 271 * the associated bit definitions. 272 */ 273 274 #define TRM_S1040_ID 0x00 /* Vendor and Device ID */ 275 #define TRM_S1040_COMMAND 0x04 /* PCI command register */ 276 #define TRM_S1040_IOBASE 0x10 /* I/O Space base address */ 277 #define TRM_S1040_ROMBASE 0x30 /* Expansion ROM Base Address */ 278 #define TRM_S1040_INTLINE 0x3C /* Interrupt line */ 279 280 #define TRM_S1040_SCSI_STATUS 0x80 /* SCSI Status (R) */ 281 #define COMMANDPHASEDONE 0x2000 /* SCSI command phase done */ 282 #define SCSIXFERDONE 0x0800 /* SCSI SCSI transfer done */ 283 #define SCSIXFERCNT_2_ZERO 0x0100 /* SCSI SCSI transfer count to zero */ 284 #define SCSIINTERRUPT 0x0080 /* SCSI interrupt pending */ 285 #define COMMANDABORT 0x0040 /* SCSI command abort */ 286 #define SEQUENCERACTIVE 0x0020 /* SCSI sequencer active */ 287 #define PHASEMISMATCH 0x0010 /* SCSI phase mismatch */ 288 #define PARITYERROR 0x0008 /* SCSI parity error */ 289 #define PHASEMASK 0x0007 /* Phase MSG/CD/IO */ 290 #define PH_DATA_OUT 0x00 /* Data out phase */ 291 #define PH_DATA_IN 0x01 /* Data in phase */ 292 #define PH_COMMAND 0x02 /* Command phase */ 293 #define PH_STATUS 0x03 /* Status phase */ 294 #define PH_BUS_FREE 0x05 /* Invalid phase used as bus free */ 295 #define PH_MSG_OUT 0x06 /* Message out phase */ 296 #define PH_MSG_IN 0x07 /* Message in phase */ 297 #define TRM_S1040_SCSI_CONTROL 0x80 /* SCSI Control (W) */ 298 #define DO_CLRATN 0x0400 /* Clear ATN */ 299 #define DO_SETATN 0x0200 /* Set ATN */ 300 #define DO_CMDABORT 0x0100 /* Abort SCSI command */ 301 #define DO_RSTMODULE 0x0010 /* Reset SCSI chip */ 302 #define DO_RSTSCSI 0x0008 /* Reset SCSI bus */ 303 #define DO_CLRFIFO 0x0004 /* Clear SCSI transfer FIFO */ 304 #define DO_DATALATCH 0x0002 /* Enable SCSI bus data latch */ 305 #define DO_HWRESELECT 0x0001 /* Enable hardware reselection */ 306 #define TRM_S1040_SCSI_FIFOCNT 0x82 /* SCSI FIFO Counter 5bits(R) */ 307 #define TRM_S1040_SCSI_SIGNAL 0x83 /* SCSI low level signal (R/W) */ 308 #define TRM_S1040_SCSI_INTSTATUS 0x84 /* SCSI Interrupt Status (R) */ 309 #define INT_SCAM 0x80 /* SCAM selection interrupt */ 310 #define INT_SELECT 0x40 /* Selection interrupt */ 311 #define INT_SELTIMEOUT 0x20 /* Selection timeout interrupt */ 312 #define INT_DISCONNECT 0x10 /* Bus disconnected interrupt */ 313 #define INT_RESELECTED 0x08 /* Reselected interrupt */ 314 #define INT_SCSIRESET 0x04 /* SCSI reset detected interrupt */ 315 #define INT_BUSSERVICE 0x02 /* Bus service interrupt */ 316 #define INT_CMDDONE 0x01 /* SCSI command done interrupt */ 317 #define TRM_S1040_SCSI_OFFSET 0x84 /* SCSI Offset Count (W) */ 318 /* 319 * Bit Name Definition 320 * 07-05 0 RSVD Reversed. Always 0. 321 * 04 0 OFFSET4 Reversed for LVDS. Always 0. 322 * 03-00 0 OFFSET[03:00] Offset number from 0 to 15 323 */ 324 #define TRM_S1040_SCSI_SYNC 0x85 /* SCSI Synchronous Control (R/W) */ 325 #define LVDS_SYNC 0x20 /* Enable LVDS synchronous */ 326 #define WIDE_SYNC 0x10 /* Enable WIDE synchronous */ 327 #define ALT_SYNC 0x08 /* Enable Fast-20 alternate synchronous */ 328 /* 329 * SYNCM 7 6 5 4 3 2 1 0 330 * Name RSVD RSVD LVDS WIDE ALTPERD PERIOD2 PERIOD1 PERIOD0 331 * Default 0 0 0 0 0 0 0 0 332 * 333 * 334 * Bit Name Definition 335 * --- ---- ---------- 336 * 07-06 0 RSVD Reversed. Always read 0 337 * 05 0 LVDS Reversed. Always read 0 338 * 04 0 WIDE/WSCSI Enable wide (16-bits) SCSI transfer. 339 * 03 0 ALTPERD/ALTPD Alternate (Sync./Period) mode. 340 * 341 * @@ When this bit is set, 342 * the synchronous period bits 2:0 343 * in the Synchronous Mode register 344 * are used to transfer data 345 * at the Fast-20 rate. 346 * @@ When this bit is reset, 347 * the synchronous period bits 2:0 348 * in the Synchronous Mode Register 349 * are used to transfer data 350 * at the Fast-40 rate. 351 * 352 * 02-00 0 PERIOD[2:0]/SXPD[02:00] Synchronous SCSI Transfer Rate. 353 * These 3 bits specify 354 * the Synchronous SCSI Transfer Rate 355 * for Fast-20 and Fast-10. 356 * These bits are also reset 357 * by a SCSI Bus reset. 358 * 359 * For Fast-10 bit ALTPD = 0 and LVDS = 0 360 * and bit2,bit1,bit0 is defined as follows : 361 * 362 * 000 100ns, 10.0 Mbytes/s 363 * 001 150ns, 6.6 Mbytes/s 364 * 010 200ns, 5.0 Mbytes/s 365 * 011 250ns, 4.0 Mbytes/s 366 * 100 300ns, 3.3 Mbytes/s 367 * 101 350ns, 2.8 Mbytes/s 368 * 110 400ns, 2.5 Mbytes/s 369 * 111 450ns, 2.2 Mbytes/s 370 * 371 * For Fast-20 bit ALTPD = 1 and LVDS = 0 372 * and bit2,bit1,bit0 is defined as follows : 373 * 374 * 000 50ns, 20.0 Mbytes/s 375 * 001 75ns, 13.3 Mbytes/s 376 * 010 100ns, 10.0 Mbytes/s 377 * 011 125ns, 8.0 Mbytes/s 378 * 100 150ns, 6.6 Mbytes/s 379 * 101 175ns, 5.7 Mbytes/s 380 * 110 200ns, 5.0 Mbytes/s 381 * 111 250ns, 4.0 Mbytes/s 382 * 383 * For Fast-40 bit ALTPD = 0 and LVDS = 1 384 * and bit2,bit1,bit0 is defined as follows : 385 * 386 * 000 25ns, 40.0 Mbytes/s 387 * 001 50ns, 20.0 Mbytes/s 388 * 010 75ns, 13.3 Mbytes/s 389 * 011 100ns, 10.0 Mbytes/s 390 * 100 125ns, 8.0 Mbytes/s 391 * 101 150ns, 6.6 Mbytes/s 392 * 110 175ns, 5.7 Mbytes/s 393 * 111 200ns, 5.0 Mbytes/s 394 */ 395 #define TRM_S1040_SCSI_TARGETID 0x86 /* SCSI Target ID (R/W) */ 396 #define TRM_S1040_SCSI_IDMSG 0x87 /* SCSI Identify Message (R) */ 397 #define TRM_S1040_SCSI_HOSTID 0x87 /* SCSI Host ID (W) */ 398 #define TRM_S1040_SCSI_COUNTER 0x88 /* SCSI Transfer Counter 24bits(R/W) */ 399 #define TRM_S1040_SCSI_INTEN 0x8C /* SCSI Interrupt Enable (R/W) */ 400 #define EN_SCAM 0x80 /* Enable SCAM selection interrupt */ 401 #define EN_SELECT 0x40 /* Enable selection interrupt */ 402 #define EN_SELTIMEOUT 0x20 /* Enable selection timeout interrupt */ 403 #define EN_DISCONNECT 0x10 /* Enable bus disconnected interrupt */ 404 #define EN_RESELECTED 0x08 /* Enable reselected interrupt */ 405 #define EN_SCSIRESET 0x04 /* Enable SCSI reset detected interrupt*/ 406 #define EN_BUSSERVICE 0x02 /* Enable bus service interrupt */ 407 #define EN_CMDDONE 0x01 /* Enable SCSI command done interrupt */ 408 #define TRM_S1040_SCSI_CONFIG0 0x8D /* SCSI Configuration 0 (R/W) */ 409 #define PHASELATCH 0x40 /* Enable phase latch */ 410 #define INITIATOR 0x20 /* Enable initiator mode */ 411 #define PARITYCHECK 0x10 /* Enable parity check */ 412 #define BLOCKRST 0x01 /* Disable SCSI reset1 */ 413 #define TRM_S1040_SCSI_CONFIG1 0x8E /* SCSI Configuration 1 (R/W) */ 414 #define ACTIVE_NEGPLUS 0x10 /* Enhance active negation */ 415 #define FILTER_DISABLE 0x08 /* Disable SCSI data filter */ 416 #define ACTIVE_NEG 0x02 /* Enable active negation */ 417 #define TRM_S1040_SCSI_CONFIG2 0x8F /* SCSI Configuration 2 (R/W) */ 418 #define TRM_S1040_SCSI_COMMAND 0x90 /* SCSI Command (R/W) */ 419 #define SCMD_COMP 0x12 /* Command complete */ 420 #define SCMD_SEL_ATN 0x60 /* Selection with ATN */ 421 #define SCMD_SEL_ATN3 0x64 /* Selection with ATN3 */ 422 #define SCMD_SEL_ATNSTOP 0xB8 /* Selection with ATN and Stop */ 423 #define SCMD_FIFO_OUT 0xC0 /* SCSI FIFO transfer out */ 424 #define SCMD_DMA_OUT 0xC1 /* SCSI DMA transfer out */ 425 #define SCMD_FIFO_IN 0xC2 /* SCSI FIFO transfer in */ 426 #define SCMD_DMA_IN 0xC3 /* SCSI DMA transfer in */ 427 #define SCMD_MSGACCEPT 0xD8 /* Message accept */ 428 /* 429 * Code Command Description 430 * 431 * 02 Enable reselection with FIFO 432 * 40 Select without ATN with FIFO 433 * 60 Select with ATN with FIFO 434 * 64 Select with ATN3 with FIFO 435 * A0 Select with ATN and stop with FIFO 436 * C0 Transfer information out with FIFO 437 * C1 Transfer information out with DMA 438 * C2 Transfer information in with FIFO 439 * C3 Transfer information in with DMA 440 * 12 Initiator command complete with FIFO 441 * 50 Initiator transfer information out sequence without ATN with FIFO 442 * 70 Initiator transfer information out sequence with ATN with FIFO 443 * 74 Initiator transfer information out sequence with ATN3 with FIFO 444 * 52 Initiator transfer information in sequence without ATN with FIFO 445 * 72 Initiator transfer information in sequence with ATN with FIFO 446 * 76 Initiator transfer information in sequence with ATN3 with FIFO 447 * 90 Initiator transfer information out command complete with FIFO 448 * 92 Initiator transfer information in command complete with FIFO 449 * D2 Enable selection 450 * 08 Reselection 451 * 48 Disconnect command with FIFO 452 * 88 Terminate command with FIFO 453 * C8 Target command complete with FIFO 454 * 18 SCAM Arbitration/ Selection 455 * 5A Enable reselection 456 * 98 Select without ATN with FIFO 457 * B8 Select with ATN with FIFO 458 * D8 Message Accepted 459 * 58 NOP 460 */ 461 #define TRM_S1040_SCSI_TIMEOUT 0x91 /* SCSI Time Out Value (R/W) */ 462 #define TRM_S1040_SCSI_FIFO 0x98 /* SCSI FIFO (R/W) */ 463 #define TRM_S1040_SCSI_TCR0 0x9C /* SCSI Target Control 0 (R/W) */ 464 #define TCR0_WIDE_NEGO_DONE 0x8000 /* Wide nego done */ 465 #define TCR0_SYNC_NEGO_DONE 0x4000 /* Synchronous nego done */ 466 #define TCR0_ENABLE_LVDS 0x2000 /* Enable LVDS synchronous */ 467 #define TCR0_ENABLE_WIDE 0x1000 /* Enable WIDE synchronous */ 468 #define TCR0_ENABLE_ALT 0x0800 /* Enable alternate synchronous */ 469 #define TCR0_PERIOD_MASK 0x0700 /* Transfer rate */ 470 #define TCR0_DO_WIDE_NEGO 0x0080 /* Do wide NEGO */ 471 #define TCR0_DO_SYNC_NEGO 0x0040 /* Do sync NEGO */ 472 #define TCR0_DISCONNECT_EN 0x0020 /* Disconnection enable */ 473 #define TCR0_OFFSET_MASK 0x001F /* Offset number */ 474 #define TRM_S1040_SCSI_TCR1 0x9E /* SCSI Target Control 1 (R/W) */ 475 #define MAXTAG_MASK 0x7F00 /* Maximum tags (127) */ 476 #define NON_TAG_BUSY 0x0080 /* Non tag command active */ 477 #define ACTTAG_MASK 0x007F /* Active tags */ 478 479 #define TRM_S1040_DMA_COMMAND 0xA0 /* DMA Command (R/W) */ 480 #define XFERDATAIN 0x0103 /* Transfer data in */ 481 #define XFERDATAOUT 0x0102 /* Transfer data out */ 482 #define TRM_S1040_DMA_FIFOCNT 0xA1 /* DMA FIFO Counter (R) */ 483 #define TRM_S1040_DMA_CONTROL 0xA1 /* DMA Control (W) */ 484 #define STOPDMAXFER 0x08 /* Stop DMA transfer */ 485 #define ABORTXFER 0x04 /* Abort DMA transfer */ 486 #define CLRXFIFO 0x02 /* Clear DMA transfer FIFO */ 487 #define STARTDMAXFER 0x01 /* Start DMA transfer */ 488 #define TRM_S1040_DMA_STATUS 0xA3 /* DMA Interrupt Status (R/W) */ 489 #define XFERPENDING 0x80 /* Transfer pending */ 490 #define DMAXFERCOMP 0x02 /* Bus Master XFER Complete status */ 491 #define SCSICOMP 0x01 /* SCSI complete interrupt */ 492 #define TRM_S1040_DMA_INTEN 0xA4 /* DMA Interrupt Enable (R/W) */ 493 #define EN_SCSIINTR 0x01 /* Enable SCSI complete interrupt */ 494 #define TRM_S1040_DMA_CONFIG 0xA6 /* DMA Configuration (R/W) */ 495 #define DMA_ENHANCE 0x8000 /* Enable DMA enhance feature */ 496 #define TRM_S1040_DMA_XCNT 0xA8 /* DMA Transfer Counter (R/W) */ 497 #define TRM_S1040_DMA_CXCNT 0xAC /* DMA Current Transfer Counter (R) */ 498 #define TRM_S1040_DMA_XLOWADDR 0xB0 /* DMA Transfer Physical Low Address */ 499 #define TRM_S1040_DMA_XHIGHADDR 0xB4 /* DMA Transfer Physical High Address */ 500 501 #define TRM_S1040_GEN_CONTROL 0xD4 /* Global Control */ 502 #define EN_EEPROM 0x10 /* Enable EEPROM programming */ 503 #define AUTOTERM 0x04 /* Enable Auto SCSI terminator */ 504 #define LOW8TERM 0x02 /* Enable Lower 8 bit SCSI terminator */ 505 #define UP8TERM 0x01 /* Enable Upper 8 bit SCSI terminator */ 506 #define TRM_S1040_GEN_STATUS 0xD5 /* Global Status */ 507 #define GTIMEOUT 0x80 /* Global timer reach 0 */ 508 #define CON5068 0x10 /* External 50/68 pin connected */ 509 #define CON68 0x08 /* Internal 68 pin connected */ 510 #define CON50 0x04 /* Internal 50 pin connected */ 511 #define WIDESCSI 0x02 /* Wide SCSI card */ 512 #define TRM_S1040_GEN_NVRAM 0xD6 /* Serial NON-VOLATILE RAM port */ 513 #define NVR_BITOUT 0x08 /* Serial data out */ 514 #define NVR_BITIN 0x04 /* Serial data in */ 515 #define NVR_CLOCK 0x02 /* Serial clock */ 516 #define NVR_SELECT 0x01 /* Serial select */ 517 #define TRM_S1040_GEN_EDATA 0xD7 /* Parallel EEPROM data port */ 518 #define TRM_S1040_GEN_EADDRESS 0xD8 /* Parallel EEPROM address */ 519 #define TRM_S1040_GEN_TIMER 0xDB /* Global timer */ 520 521 int trm_Interrupt(void *); 522 int trm_init(struct trm_softc *, int); 523 void trm_scsi_cmd(struct scsi_xfer *); 524 525 526 #endif /* trm_h */
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