The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/tropicreg.h

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    1 /*      $NetBSD: tropicreg.h,v 1.4 2003/11/02 11:07:46 wiz Exp $        */
    2 
    3 /* 
    4  * Mach Operating System
    5  * Copyright (c) 1991 Carnegie Mellon University
    6  * Copyright (c) 1991 IBM Corporation 
    7  * All Rights Reserved.
    8  * 
    9  * Permission to use, copy, modify and distribute this software and its
   10  * documentation is hereby granted, provided that both the copyright
   11  * notice and this permission notice appear in all copies of the
   12  * software, derivative works or modified versions, and any portions
   13  * thereof, and that both notices appear in supporting documentation,
   14  * and that the name IBM not be used in advertising or publicity 
   15  * pertaining to distribution of the software without specific, written
   16  * prior permission.
   17  * 
   18  * CARNEGIE MELLON AND IBM ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS IS"
   19  * CONDITION.  CARNEGIE MELLON AND IBM DISCLAIM ANY LIABILITY OF ANY KIND FOR
   20  * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
   21  * 
   22  * Carnegie Mellon requests users of this software to return to
   23  * 
   24  *  Software Distribution Coordinator  or  Software.Distribution@CS.CMU.EDU
   25  *  School of Computer Science
   26  *  Carnegie Mellon University
   27  *  Pittsburgh PA 15213-3890
   28  * 
   29  * any improvements or extensions that they make and grant Carnegie Mellon
   30  * the rights to redistribute these changes.
   31  */
   32 
   33 /* $ACIS:if_lanreg.h 12.0$ */
   34 
   35 #define TR_SWITCH 0
   36 #define TR_RESET 1
   37 #define TR_RELEASE 2
   38 #define TR_CLEARINT 3
   39 
   40 /* macros to deal with accessing the MMIO region */
   41 #define MM_OUTB(sc, off, val)   \
   42         bus_space_write_1((sc)->sc_memt, (sc)->sc_mmioh, (off), (val))
   43 #define MM_OUTW(sc, off, val)   \
   44         bus_space_write_2((sc)->sc_memt, (sc)->sc_mmioh, (off), htons((val)))
   45 #define MM_INB(sc, off)         \
   46         bus_space_read_1((sc)->sc_memt, (sc)->sc_mmioh, (off))
   47 #define MM_INW(sc, off)         \
   48         ntohs(bus_space_read_2((sc)->sc_memt, (sc)->sc_mmioh, (off)))
   49 
   50 /* macros to deal with accesses to the shared ram */
   51 #define SR_INB(sc, off) \
   52         bus_space_read_1(sc->sc_memt, sc->sc_sramh, (off))
   53 #define SR_INW(sc, off) \
   54         htons(bus_space_read_2(sc->sc_memt, sc->sc_sramh, (off)))
   55 #define SR_OUTB(sc, off, val)   \
   56         bus_space_write_1((sc)->sc_memt, (sc)->sc_sramh, (off), (val))
   57 #define SR_OUTW(sc, off, val)   \
   58         bus_space_write_2((sc)->sc_memt, (sc)->sc_sramh, (off), htons((val)))
   59 
   60 /* macros to deal with accesses to the recv buffers */
   61 #define RB_INB(sc, rb, reg)     SR_INB(sc, (rb)+(reg))
   62 #define RB_INW(sc, rb, reg)     SR_INW(sc, (rb)+(reg))
   63 
   64 /* macros to deal with the ACA */
   65 #define ACA_RDB(sc, reg)        MM_INB(sc, ((sc->sc_aca+(reg))|ACA_RW))
   66 #define ACA_RDW(sc, reg)        MM_INW(sc, ((sc->sc_aca+(reg))|ACA_RW))
   67 #define ACA_OUTB(sc, reg, val)  MM_OUTB(sc, ((sc->sc_aca+(reg))|ACA_RW), (val))
   68 #define ACA_SETB(sc, reg, val)  MM_OUTB(sc, ((sc->sc_aca+(reg))|ACA_SET), (val))
   69 #define ACA_RSTB(sc, reg, val)  MM_OUTB(sc, ((sc->sc_aca+(reg))|ACA_RST), (val))
   70 
   71 /* macros to deal with the SSB */
   72 #define SSB_INB(sc, ssb, reg)   SR_INB(sc, (ssb)+(reg))
   73 
   74 /* macros to deal with the ARB */
   75 #define ARB_INB(sc, arb, reg)   SR_INB(sc, (arb)+(reg))
   76 #define ARB_INW(sc, arb, reg)   SR_INW(sc, (arb)+(reg))
   77 
   78 /* macros to deal with the SRB */
   79 #define SRB_INB(sc, srb, reg)   SR_INB(sc, (srb)+(reg))
   80 #define SRB_INW(sc, srb, reg)   SR_INW(sc, (srb)+(reg))
   81 #define SRB_OUTB(sc, srb, reg, val)     SR_OUTB(sc, (srb)+(reg), (val))
   82 #define SRB_OUTW(sc, srb, reg, val)     SR_OUTW(sc, (srb)+(reg), (val))
   83 
   84 /* macros to deal with the ASB */
   85 #define ASB_INB(sc, asb, reg)   SR_INB(sc, (asb)+(reg))
   86 #define ASB_INW(sc, asb, reg)   SR_INW(sc, (asb)+(reg))
   87 #define ASB_OUTB(sc, asb, reg, val)     SR_OUTB(sc, (asb)+(reg), (val))
   88 #define ASB_OUTW(sc, asb, reg, val)     SR_OUTW(sc, (asb)+(reg), (val))
   89 
   90 /* macros to deal with the TXCA */
   91 #define TXCA_INW(sc, reg)       SR_INW(sc, sc->sc_txca+(reg))
   92 #define TXCA_OUTW(sc, reg, val) SR_OUTW(sc, sc->sc_txca+(reg), (val))
   93 
   94 /* macros to deal with the txbuffers */
   95 #define TXB_INB(sc, buf, reg)   SR_INB(sc, (buf)+(reg))
   96 #define TXB_INW(sc, buf, reg)   SR_INW(sc, (buf)+(reg))
   97 #define TXB_OUTB(sc, buf, reg, val)     SR_OUTB(sc, (buf)+(reg), (val))
   98 #define TXB_OUTW(sc, buf, reg, val)     SR_OUTW(sc, (buf)+(reg), (val))
   99 
  100 /* ACA registers */
  101 #define ACA_RRR         0
  102 #define ACA_RRR_e       ACA_RRR
  103 #define ACA_RRR_o       (ACA_RRR+1)
  104 #define ACA_WRBR        2
  105 #define ACA_WRBR_e      ACA_WRBR
  106 #define ACA_WRBR_o      (ACA_WRBR+1)
  107 #define ACA_WWOR        4
  108 #define ACA_WWOR_e      ACA_WWOR
  109 #define ACA_WWOR_o      (ACA_WWOR+1)
  110 #define ACA_WWCR        6
  111 #define ACA_WWCR_e      ACA_WWCR
  112 #define ACA_WWCR_o      (ACA_WWCR+1)
  113 #define ACA_ISRP        8
  114 #define ACA_ISRP_e      ACA_ISRP
  115 #define ACA_ISRP_o      (ACA_ISRP+1)
  116 #define ACA_ISRA        10
  117 #define ACA_ISRA_e      ACA_ISRA
  118 #define ACA_ISRA_o      (ACA_ISRA+1)
  119 #define ACA_TCR         12
  120 #define ACA_TCR_e       ACA_TCR
  121 #define ACA_TCR_o       (ACA_TCR+1)
  122 #define ACA_TVR         14
  123 #define ACA_TVR_e       ACA_TVR
  124 #define ACA_TVR_o       (ACA_TVR+1)
  125 
  126 /* access flags; to be or-ed into offset */
  127 #define ACA_RW          0
  128 #define ACA_RST         0x20
  129 #define ACA_SET         0x40
  130 
  131 /* offsets valid for all command blocks */
  132 #define CMD_CMD         0
  133 #define CMD_RETCODE     2
  134 
  135 /*
  136  * Structure of SSB (System Status Block)
  137  */
  138 #define SSB_SIZE        20              /* size of SSB */
  139 #define SSB_CMD         0
  140 #define SSB_CMDCORR     1
  141 #define SSB_RETCODE     2
  142 #define SSB_STATIONID   4
  143 #define SSB_XMITERR     6
  144 
  145 /*
  146  * Structure of ARB (Adapter Request Block)
  147  */
  148 #define ARB_SIZE        28              /* size of ARB */
  149 #define ARB_CMD         0
  150 #define ARB_STATIONID   4               /* ID of receiving station */
  151 
  152 /* receive data command block */
  153 #define ARB_RXD_BUFADDR 6               /* RAM offset of 1st rec buf */
  154 #define ARB_RXD_LANHDRLEN       8       /* Length of LAN header */
  155 #define ARB_RXD_DLCHDRLEN       9       /* Length of DLC header */
  156 #define ARB_RXD_FRAMELEN        10      /* Length of entire frame */
  157 #define ARB_RXD_MSGTYPE         12      /* Category of message */
  158 
  159 /* transmit data command block */
  160 #define ARB_XMT_CMDCORR         1
  161 #define ARB_XMT_DHBADDR         6
  162 
  163 /* ring status change information block */
  164 #define ARB_RINGSTATUS          6
  165 
  166 /* DLC status change response block */
  167 #define ARB_DLCSTAT_STATUS      6       /* status info field */ 
  168 #define ARB_DLCSTAT_FRMRDATA    8       /* 5 bytes */
  169 #define ARB_DLCSTAT_ACCPRIO     13
  170 #define ARB_DLCSTAT_REMADDR     14      /* remote address */
  171 #define ARB_DLCSTAT_REMSAP      20      /* remote sap */
  172 
  173 /*
  174  * Structure of SRB (System Request Block)
  175  */
  176 #define SRB_SIZE        28              /* size of SRB */
  177 #define SRB_CMD 0
  178 #define SRB_RETCODE     2
  179 
  180 /* contents of SRB after adapter reset */
  181 #define         INIT_COMPL              0x80    /* in SRB_CMD */
  182 #define SRB_INIT_STATUS 1
  183 #define         RSP_DETECT              0x40
  184 #define         FAST_PATH_TRANSMIT      0x20
  185 #define         RING_MEASUREMENT        0x08
  186 #define         RPL                     0x02
  187 #define         RSP_16                  0x01
  188 #define SRB_INIT_STATUS2        2
  189 #define         PNP                     0x80
  190 #define         SET_DEF_RSP             0x40
  191 #define         AUTO_DEF_RSP_UPDATE     0x20
  192 #define SRB_INIT_BUC    6               /* bring up code */
  193 #define SRB_INIT_ENCADDR        8       /* offset of adapter's */
  194                                         /* permanent encoded address */
  195 #define SRB_INIT_LVLADDR        10      /* offset of adapter's */
  196                                         /* microcode level */
  197 #define SRB_INIT_ADAPADDR       12      /* offset of adapter addresses */
  198 #define SRB_INIT_PARMSADDR      14      /* offset of adapter parameters */
  199 #define SRB_INIT_MACADDR        16      /* offset of adapter MAC buffer */
  200 #define SRB_INIT_UTILADDR       18      /* offset of ring utilization measurement */
  201 
  202 /* config fast path ram command block */
  203 #define SRB_CFP_CMDSIZE         12      /* length of command block */
  204 #define SRB_CFP_RAMSIZE         8
  205 #define SRB_CFP_BUFSIZE         10
  206 
  207 /* config fast path transmit response block */
  208 #define SRB_CFPRESP_FPXMIT      8       /* offset to transmit control area */
  209 #define SRB_CFPRESP_SRBADDR     10      /* offset for the next SRB address */
  210 
  211 /* open command block */
  212 #define SRB_OPEN_CMDSIZE        60
  213 #define SRB_OPEN_OPTIONS        8       /* open options */
  214 #define SRB_OPEN_NODEADDR       10      /* adapter's ring address */
  215 #define SRB_OPEN_GROUPADDR      16      /* adapter's group address */
  216 #define SRB_OPEN_FUNCTADDR      20      /* adapter's functional address */
  217 #define SRB_OPEN_NUMRCVBUF      24      /* number of receive buffers */
  218 #define SRB_OPEN_RCVBUFLEN      26      /* length of receive buffers */
  219 #define SRB_OPEN_DHBLEN         28      /* length of DHBs */
  220 #define SRB_OPEN_NUMDHB         30      /* number of DHBs */
  221 #define SRB_OPEN_DLCMAXSAP      32      /* max. number of SAPs */
  222 #define SRB_OPEN_DLCMAXSTA      33      /* max. number of link stations */
  223 #define SRB_OPEN_DLCMAXGSAP     34      /* max. number of group SAPs */
  224 #define SRB_OPEN_DLCMAXGMEM     35      /* max. members per group SAP */
  225 #define SRB_OPEN_DLCT1TICK1     36      /* timer T1 intvl. group one */
  226 #define SRB_OPEN_DLCT2TICK1     37      /* timer T7 intvl. group one */
  227 #define SRB_OPEN_DLCTITICK1     38      /* timer Ti intvl. group one */
  228 #define SRB_OPEN_DLCT1TICK2     39      /* timer T1 intvl. group two */
  229 #define SRB_OPEN_DLCT2TICK2     40      /* timer T7 intvl. group two */
  230 #define SRB_OPEN_DLCTITICK2     41      /* timer Ti intvl. group two */
  231 #define SRB_OPEN_PODUCTID       42      /* product id (18 bytes) */
  232 
  233 /* open command response block */
  234 #define SRB_OPENRESP_ERRCODE    6
  235 #define SRB_OPENRESP_ASBADDR    8       /* offset of ASB */
  236 #define SRB_OPENRESP_SRBADDR    10      /* offset of SRB */
  237 #define SRB_OPENRESP_ARBADDR    12      /* offset of ARB */
  238 #define SRB_OPENRESP_SSBADDR    14      /* offset of SSB */
  239 
  240 /* open sap command and response block */
  241 #define SRB_OPNSAP_STATIONID    4       /* ID of SAP after open */
  242 #define SRB_OPNSAP_TIMERT1      6       /* response timer */
  243 #define SRB_OPNSAP_TIMERT2      7       /* acknowledge timer */
  244 #define SRB_OPNSAP_TIMERTI      8       /* inactivity timer */
  245 #define SRB_OPNSAP_MAXOUT       9       /* max. xmits without ack */
  246 #define SRB_OPNSAP_MAXIN        10      /* max. recvs without ack */
  247 #define SRB_OPNSAP_MAXOUTINCR   11      /* window increment value */
  248 #define SRB_OPNSAP_MAXRETRY     12      /* N2 value */
  249 #define SRB_OPNSAP_GSAPMAXMEMB  13      /* max. SAPs for a group SAP */
  250 #define SRB_OPNSAP_MAXIFIELD    14      /* max recv info field length */
  251 #define SRB_OPNSAP_SAPVALUE     16      /* SAP to be opened */
  252 #define SRB_OPNSAP_SAPOPTIONS   17      /* options to be set */
  253 #define SRB_OPNSAP_STATIONCNT   18      /* num of link stations to reserve */
  254 #define SRB_OPNSAP_SAPGSAPMEMB  19      /* number of GSAP members */
  255 #define SRB_OPNSAP_GSAP1        20      /* first gsap request */
  256 
  257 /* read log command and response block */
  258 #define SRB_RLOG_LOGDATA        14      /* 14 bytes of log data */
  259 #define SRB_LOG_LINEERRS        (SRB_RLOG_LOGDATA+0)    /* line errors */
  260 #define SRB_LOG_INTERRS         (SRB_RLOG_LOGDATA+1)    /* internal errors */
  261 #define SRB_LOG_BRSTERRS        (SRB_RLOG_LOGDATA+2)    /* burst errors */
  262 #define SRB_LOG_ACERRS          (SRB_RLOG_LOGDATA+3)    /* AC errors */
  263 #define SRB_LOG_ABRTERRS        (SRB_RLOG_LOGDATA+4)    /* abort errors */
  264 #define SRB_LOG_LOSTFRMS        (SRB_RLOG_LOGDATA+6)    /* lost frames */
  265 #define SRB_LOG_RCVCONG         (SRB_RLOG_LOGDATA+7)    /* receive congestion count */
  266 #define SRB_LOG_FCPYERRS        (SRB_RLOG_LOGDATA+8)    /* frame copied errors */
  267 #define SRB_LOG_FREQERRS        (SRB_RLOG_LOGDATA+9)    /* frequency erros  */
  268 #define SRB_LOG_TOKENERRS       (SRB_RLOG_LOGDATA+10)   /* token errors */
  269 
  270 /* set default ring speed command */
  271 #define SRB_SET_DEFRSP          6
  272 
  273 /*
  274  * Structure of ASB (Adapter Status Block)
  275  */
  276 #define ASB_SIZE        12              /* size of ASB */
  277 #define RECV_CMD        0
  278 #define RECV_RETCODE    2
  279 #define RECV_STATIONID  4
  280 
  281 #define RECV_RESP_RECBUFADDR    6
  282 
  283 /* host response to xmit-req-data command */
  284 #define XMIT_CMD        0
  285 #define XMIT_CMDCORR    1               /* command correlator */
  286 #define XMIT_RETCODE    2               /* return code */
  287 #define XMIT_STATIONID  4               /* id of sending station */
  288 #define XMIT_FRAMELEN   6               /* length of entire frame */
  289 #define XMIT_HDRLEN     8               /* length of LAN header */
  290 #define XMIT_REMSAP     9               /* remote SAP */
  291 #define XMIT_DATA       10              /* offset of first data byte */
  292 /* fast path specific data */
  293 #define XMIT_LASTBUF    12
  294 #define XMIT_FRAMEPTR   14
  295 #define XMIT_NEXTBUF    16
  296 #define XMIT_STATUS     18
  297 #define XMIT_STRIPFS    19
  298 #define XMIT_BUFLEN     20
  299 #define XMIT_FP_DATA    22              /* offset of first data byte */
  300 
  301 #if 0   /* XXXchb unused? */
  302 /*
  303  *      Adapter addresses
  304  */
  305 struct adapt_addr {
  306         unsigned char   node_addr[6];   /* Adapter node address */
  307         unsigned char   grp_addr[4];    /* Adapter group address */
  308         unsigned char   func_addr[4];   /* Adapter functional address */
  309 };
  310 
  311 /*
  312  *      Adapter parameters
  313  */
  314 struct param_addr {
  315         unsigned char   phys_addr[4];   /* Adapter physical address */
  316         unsigned char   up_node_addr[6];        /* Next active upstream node
  317                                          * addr */
  318         unsigned char   up_phys_addr[4];        /* Next active upstream phys
  319                                          * addr */
  320         unsigned char   poll_addr[6];   /* Last poll address */
  321         unsigned char   res0[2];/* Reserved */
  322         unsigned char   acc_priority[2];        /* Transmit access priority */
  323         unsigned char   src_class[2];   /* Source class authorization */
  324         unsigned char   att_code[2];    /* Last attention code */
  325         unsigned char   src_addr[6];    /* Last source address */
  326         unsigned char   bcon_type[2];   /* Last beacon type */
  327         unsigned char   major_vector[2];        /* Last major vector */
  328         unsigned char   ring_stat[2];   /* ring status */
  329         unsigned char   soft_error[2];  /* soft error timer value */
  330         unsigned char   fe_error[2];    /* front end error counter */
  331         unsigned char   next_state[2];  /* next state indicator */
  332         unsigned char   mon_error[2];   /* Monitor error code */
  333         unsigned char   bcon_xmit[2];   /* Beacon transmit type */
  334         unsigned char   bcon_receive[2];        /* Beacon receive type */
  335         unsigned char   frame_correl[2];        /* Frame correlator save */
  336         unsigned char   bcon_naun[6];   /* beacon station NAUN */
  337         unsigned char   res1[4];/* Reserved */
  338         unsigned char   bcon_phys[4];   /* Beacon station physical addr */
  339 };
  340 #endif
  341 
  342 #define TXCA_BUFFER_COUNT       0
  343 #define TXCA_FREE_QUEUE_HEAD    2
  344 #define TXCA_FREE_QUEUE_TAIL    4
  345 #define TXCA_ADAPTER_QUEUE_HEAD 6
  346 #define TXCA_BUFFER_SIZE        8
  347 #define TXCA_COMPLETION_QUEUE_TAIL      10
  348 
  349 /* Adapter receive buffer structure */
  350 #define RB_NEXTBUF      2       /* offset of next buf plus 2 in sram */
  351 #define RB_FS           5       /* FS/addr match (last buf only) */
  352 #define RB_BUFLEN       6       /* length of data in this buffer */
  353 #define RB_DATA         8       /* RCV_BUF_DLEN bytes frame data */
  354 
  355 /* Misc. structure sizes. */
  356 #define SAPCB_SIZE      64      /* size of SAP control block */
  357 #define LSCB_SIZE       144     /* size of DLC link station control block */
  358 
  359 /* memory in shared ram area that is reserved by the adapter */
  360 #define PRIVRAM_SIZE    1416    /* adapter private ram area */
  361 #define RESVDMEM_SIZE   (PRIVRAM_SIZE+ARB_SIZE+SSB_SIZE+SRB_SIZE+ASB_SIZE)
  362 
  363 /* Memory offsets of adapter control areas */
  364 
  365 #define TR_SRAM_DEFAULT 0xd8000
  366 
  367 /* Offset of MMIO region */
  368 #define TR_MMIO_OFFSET  0x80000 
  369 #define TR_MMIO_MINADDR 0xc0000
  370 #define TR_MMIO_MAXADDR 0xde000
  371 #define TR_MMIO_SIZE    8192
  372 
  373 #define TR_ACA_OFFSET   0x1e00  /* Offset of ACA in MMIO region */
  374 /*
  375  * XXX Create AIP structure 
  376  */
  377 #define TR_MAC_OFFSET   0x1f00  /* Offset of MAC address in MMIO region */
  378 #define TR_ID_OFFSET    0x1f30  /* Offset of ID in MMIO region */
  379 #define TR_TYP_OFFSET   0x1fa0  /* Offset of TYP in MMIO region */
  380 #define TR_RATES_OFFSET 0x1fa2  /* Offset of supported speeds in MMIO region */
  381 #define TR_RAM_OFFSET   0x1fa6  /* Offset of available shared RAM */
  382 #define TR_PAGE_OFFSET  0x1fa8  /* Offset of shared-RAM paging support */
  383 #define TR_DHB4_OFFSET  0x1faa  /* Offset of available DHB size at 4Mbit */
  384 #define TR_DHB16_OFFSET 0x1fac  /* Offset of available DHB size at 16Mbit */
  385 #define TR_MEDIAS_OFFSET 0x1fb6 /* Offset of supported media types in MMIO */
  386 #define TR_MEDIA_OFFSET 0x1fb8  /* Offset of selected media type in MMIO */
  387 #define TR_IRQ_OFFSET   0x1fba  /* Offset of IRQs supported in MMIO region */
  388 
  389 /* Bring-Up Test results */
  390 
  391 #define BUT_OK                  0x0000  /* Initialization completed OK */
  392 #define BUT_PROCESSOR_FAIL      0x0020  /* Failed processor initialization */
  393 #define BUT_ROM_FAIL            0x0022  /* Failed ROM test diagnostic */
  394 #define BUT_RAM_FAIL            0x0024  /* Failed RAM test diagnostic */
  395 #define BUT_INST_FAIL           0x0026  /* Failed instruction test diag. */
  396 #define BUT_INTER_FAIL          0x0028  /* Failed interrupt test diagnostic */
  397 #define BUT_MEM_FAIL            0x002a  /* Failed memory interface diag. */
  398 #define BUT_PROTOCOL_FAIL       0x002c  /* Failed protocol handler diag. */
  399 
  400 
  401 /* Direct PC-to-adapter commands */
  402 
  403 #define DIR_INTERRUPT           0x00    /* Cause adapter to interrupt the PC */
  404 #define DIR_MOD_OPEN_PARAMS     0x01    /* Modify open options */
  405 #define DIR_RESTORE_OPEN_PARMS  0x02    /* Restore open options */
  406 #define DIR_OPEN_ADAPTER        0x03    /* Open the adapter card */
  407 #define DIR_CLOSE               0x04    /* Close adapter card */
  408 #define DIR_SET_GRP_ADDR        0x06    /* Set adapter group address */
  409 #define DIR_SET_FUNC_ADDR       0x07    /* Set adapter functional addr */
  410 #define DIR_READ_LOG            0x08    /* Read and reset error counters */
  411 #define DIR_SET_BRIDGE_PARMS    0x09
  412 #define DIR_CONFIG_BRIDGE_RAM   0x0c
  413 #define DIR_CONFIG_FAST_PATH_RAM        0x12
  414 #define DIR_SINGLE_ROUTE_BROADCAST      0x1f
  415 #define DIR_SET_DEFAULT_RING_SPEED      0x21
  416 
  417 #define XMIT_DIR_FRAME          0x0a    /* Direct station transmit */
  418 #define XMIT_I_FRAME            0x0b
  419 #define XMIT_UI_FRM             0x0d    /* transmit unnumbered info frame */
  420 #define XMIT_XID_CMD            0x0e    /* transmit XID command */
  421 #define XMIT_XID_RESP_FINAL     0x0f
  422 #define XMIT_XID_RESP_NOT_FINAL 0x10
  423 #define XMIT_TEST_CMD           0x11    /* transmit TEST command */
  424 
  425 
  426 /* Adapter-Card-to-PC commands */
  427 
  428 #define REC_DATA                0x81    /* Data received from ring station */
  429 #define XMIT_DATA_REQ           0x82    /* Adapter needs data to xmit */
  430 #define DLC_STATUS              0x83    /* DLC status has changed */
  431 #define RING_STAT_CHANGE        0x84    /* Adapter has new ring-status info */
  432 #define REC_BRIDGE_DATA         0x85
  433 #define REXMIT_DATA_REQ         0x86
  434 
  435 /* Open options */
  436 
  437 #define OPEN_WRAP               0x8000  /* Wrap xmit data to receive data */
  438 #define OPEN_NO_HARD_ERR        0x4000  /* Ring hard error and xmit beacon */
  439                                         /* conditions do not cause interrupt */
  440 #define OPEN_NO_SOFT_ERR        0x2000  /* Ring soft errors do not cause */
  441                                         /* interrupt */
  442 #define OPEN_PASS_MAC           0x1000  /* Pass all adapter-class MAC frames */
  443                                         /* received but not supported by the */
  444                                         /* adapter */
  445 #define OPEN_PASS_ATTN_MAC      0x0800  /* Pass all attention-class MAC */
  446                                         /* frames != the previously received */
  447                                         /* attention MAC frame */
  448 #define OPEN_PASS_BCON_MAC      0x0100  /* Pass the first beacon MAC frame */
  449                                         /* and all subsequent beacon MAC */
  450                                         /* frames that have a change in */
  451                                         /* source address or beacon type */
  452 #define OPEN_CONT               0x0080  /* Adapter will participate in */
  453                                         /* monitor contention */
  454 
  455 #define NUM_RCV_BUF             4       /* Number of receive buffers in */
  456                                         /* shared RAM needed for adapter to */
  457                                         /* open */
  458 #define RCV_BUF_LEN             520     /* Length of each receive buffer */
  459 #define RCV_BUF_DLEN            RCV_BUF_LEN - 8 /* Length of data in rec buf */
  460 
  461 #define DHB_LENGTH              512     /* Length of each transmit buffer */
  462 #define FP_BUF_LEN              536     /* length of each FP transmit buffer */
  463 
  464 /*
  465  * Integrity cannot be guaranteed if number of dhbs > 2
  466  */
  467 #define NUM_DHB                 1       /* Number of transmit buffers */
  468 
  469 #define DLC_MAX_SAP             0       /* MAX number of SAPs */
  470 #define DLC_MAX_STA             0       /* MAX number of link stations */
  471 #define DLC_MAX_GSAP            0       /* MAX number of group SAPs */
  472 #define DLC_MAX_GMEM            0       /* MAX number of SAPs that can be */
  473                                         /* assigned to any given group */
  474 #define DLC_TICK                0       /* Zero selects default of 40ms */
  475 
  476 
  477 /* Open return codes */
  478 
  479 #define OPEN_OK                 0x00    /* Open completed successfully */
  480 #define OPEN_BAD_COMMAND        0x01    /* Invalid command code */
  481 #define OPEN_ALREADY            0x03    /* Adapter is ALREADY open */
  482 #define OPEN_MISSING_PARAMS     0x05    /* Required parameters missing */
  483 #define OPEN_UNRECOV_FAIL       0x07    /* Unrecoverable failure occurred */
  484 #define OPEN_INAD_REC_BUFS      0x30    /* Inadequate receive buffers */
  485 #define OPEN_BAD_NODE_ADDR      0x32    /* Invalid NODE address */
  486 #define OPEN_BAD_REC_BUF_LEN    0x33    /* Invalid receive buffer length */
  487 #define OPEN_BAD_XMIT_BUF_LEN   0x43    /* Invalid transmit buffer length */
  488 
  489 /* Bit definitions of ISRA High Byte, (Adapter Status)  */
  490 #define PARITY_ERROR    0x80    /* Parity error on the adapter's internal bus */
  491 #define TIMER_STAT      0x40    /* A Timer Control Reg. has an interrupt */
  492 #define ACCESS_STAT     0x20    /* Shared RAM or MMIO access violation */
  493 #define DEADMAN_TIMER   0x10    /* The deadman timer has expired */
  494 #define PROCESSOR_CK    0x08    /* Adapter Processor Check */
  495 #define H_INT_MASK      0x02    /* When on, no adapter hardware interrupts */
  496 #define S_INT_MASK      0x01    /* When on, no adapter software interrupts */
  497 
  498 /* Bit definitions of ISRA Low Byte, (Used by PC to interrupt adapter) */
  499 #define XMIT_REQ        0x40    /* Transmit frame in fast path transmit buf */
  500 #define CMD_IN_SRB      0x20    /* Inform adapter of command in SRB */
  501 #define RESP_IN_ASB     0x10    /* Inform adapter of response in ASB */
  502 #define SRB_FREE        0x08    /* Inform PC when SRB is FREE */
  503 #define ASB_FREE        0x04    /* Inform PC when ASB is FREE */
  504 #define ARB_FREE        0x02    /* Inform adapter ARB is FREE */
  505 #define SSB_FREE        0x01    /* Inform adapter SSB is FREE */
  506 
  507 /* Bit definitions of ISRP High Byte, (PC interrupts and interrupt control) */
  508 #define NMI_INT_CTL     0x80    /* 1 = all interrupts to PC interrupt level */
  509                                 /* 0 = error and timer interrupts to PC NMI */
  510 #define INT_ENABLE      0x40    /* Allow adapter to interrupt the PC */
  511 #define TCR_INT         0x10    /* Timer Control Reg. has interrupt for PC */
  512 #define ERR_INT         0x08    /* Adap machine check, deadman timer, overrun */
  513 #define ACCESS_INT      0x04    /* Shared RAM or MMIO access violation */
  514 #define SHARED_INT_BLK  0x02    /* Shared interrupt blocked */
  515 #define PRIM_ALT_ADDR   0x01    /* 0 = primary adapter address */
  516                                 /* 1 = alternate adapter address */
  517 
  518 /* Bit definitions of ISRP Low Byte, (PC interrupts) */
  519 #define ADAP_CHK_INT    0x40    /* The adapter has an unrecoverable error */
  520 #define SRB_RESP_INT    0x20    /* Adapter has placed a response in the SRB */
  521 #define ASB_FREE_INT    0x10    /* Adapter has read response in ARB */
  522 #define ARB_CMD_INT     0x08    /* ARB has command for PC to act on */
  523 #define SSB_RESP_INT    0x04    /* SSB has response to previous SRB command */
  524 #define XMIT_COMPLETE   0x02    /* Fast path transmit frame complete */
  525 
  526 
  527 /* Constants for Token-Ring physical header */
  528 #define DLC_HDR_LEN     0x3     /* Length of DLC header */
  529 #define SNAP_LENGTH     0x05    /* SNAP field length */              
  530                                 /* protocol id = 3 bytes */
  531                                 /* ethertype = 2 bytes */
  532 #define HDR_LNGTH_NOROUTE 14    /* length of header with no route info */
  533 #define SKIP_DSAP_SSAP    0x02  /* length of dsap and ssap in llc frame */
  534 #define TR_MAX_LINK_HDR 46      /* max length of link header with route info */
  535 
  536 /* SAP DLC SRB commands (page 6-50 Token Ring Tech. Ref.) */
  537 #define DLC_RESET               0x14
  538 #define DLC_OPEN_SAP            0x15    /* activate service access point */
  539 #define DLC_CLOSE_SAP           0x16    /* de-activate SAP */
  540 #define DLC_REALLOCATE          0x17
  541 #define DLC_OPEN_STATION        0x19
  542 #define DLC_CLOSE_STATION       0x1a
  543 #define DLC_CONNECT_STATION     0x1b
  544 #define DLC_MODIFY              0x1c
  545 #define DLC_FLOW_CONTROL        0x1d
  546 #define DLC_STATISTICS          0x1e
  547 
  548 
  549 /* ARB RING STATUS CHANGE */
  550 #define SIGNAL_LOSS     0x8000  /* signal loss */
  551 #define HARD_ERR        0x4000  /* beacon frames sent */
  552 #define SOFT_ERR        0x2000  /* soft error */
  553 #define LOBE_FAULT      0x0800  /* lobe wire fault */
  554 #define LOG_OFLOW       0x0080  /* adapter error log counter overflow */
  555 #define SINGLE_STATION  0x0040  /* single station on ring */

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