FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/uhareg.h
1 /* $NetBSD: uhareg.h,v 1.9 2003/05/03 18:11:24 wiz Exp $ */
2
3 /*-
4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
9 * Simulation Facility, NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 /*
41 * Ported for use with the UltraStor 14f by Gary Close (gclose@wvnvms.wvnet.edu)
42 * Slight fixes to timeouts to run with the 34F
43 * Thanks to Julian Elischer for advice and help with this port.
44 *
45 * Originally written by Julian Elischer (julian@tfs.com)
46 * for TRW Financial Systems for use under the MACH(2.5) operating system.
47 *
48 * TRW Financial Systems, in accordance with their agreement with Carnegie
49 * Mellon University, makes this software available to CMU to distribute
50 * or use in any manner that they see fit as long as this message is kept with
51 * the software. For this reason TFS also grants any other persons or
52 * organisations permission to use or modify this software.
53 *
54 * TFS supplies this software to be publicly redistributed
55 * on the understanding that TFS is not responsible for the correct
56 * functioning of this software in any circumstances.
57 *
58 * commenced: Sun Sep 27 18:14:01 PDT 1992
59 * slight mod to make work with 34F as well: Wed Jun 2 18:05:48 WST 1993
60 */
61
62 typedef u_long physaddr;
63 typedef u_long physlen;
64
65 /************************** board definitions *******************************/
66 /*
67 * I/O Port Interface
68 */
69 #define U14_LMASK 0x0000 /* local doorbell mask reg */
70 #define U14_LINT 0x0001 /* local doorbell int/stat reg */
71 #define U14_SMASK 0x0002 /* system doorbell mask reg */
72 #define U14_SINT 0x0003 /* system doorbell int/stat reg */
73 #define U14_ID 0x0004 /* product id reg (2 ports) */
74 #define U14_CONFIG 0x0006 /* config reg (2 ports) */
75 #define U14_OGMPTR 0x0008 /* outgoing mail ptr (4 ports) */
76 #define U14_ICMPTR 0x000c /* incoming mail ptr (4 ports) */
77
78 #define U24_CONFIG 0x0005 /* config reg (3 ports) */
79 #define U24_LMASK 0x000c /* local doorbell mask reg */
80 #define U24_LINT 0x000d /* local doorbell int/stat reg */
81 #define U24_SMASK 0x000e /* system doorbell mask reg */
82 #define U24_SINT 0x000f /* system doorbell int/stat reg */
83 #define U24_OGMCMD 0x0016 /* outgoing commands */
84 #define U24_OGMPTR 0x0017 /* outgoing mail ptr (4 ports) */
85 #define U24_ICMCMD 0x001b /* incoming commands */
86 #define U24_ICMPTR 0x001c /* incoming mail ptr (4 ports) */
87
88 /*
89 * UHA_LMASK bits (read only)
90 */
91 #define UHA_LDIE 0x80 /* local doorbell int enabled */
92 #define UHA_SRSTE 0x40 /* soft reset enabled */
93 #define UHA_ABORTEN 0x10 /* abort MSCP enabled */
94 #define UHA_OGMINTEN 0x01 /* outgoing mail interrupt enabled */
95
96 /*
97 * UHA_LINT bits (read only)
98 */
99 #define U14_LDIP 0x80 /* local doorbell int pending */
100 #define U24_LDIP 0x02 /* local doorbell int pending */
101
102 /*
103 * UHA_LINT bits (write only)
104 */
105 #define U14_OGMFULL 0x01 /* outgoing mailbox is full */
106 #define U14_ABORT 0x10 /* abort MSCP */
107
108 #define U24_OGMFULL 0x02 /* outgoing mailbox is full */
109
110 #define UHA_SBRST 0x40 /* scsi bus reset */
111 #define UHA_ADRST 0x80 /* adapter soft reset */
112 #define UHA_ASRST 0xc0 /* adapter and scsi reset */
113
114 /*
115 * UHA_SMASK bits (read/write)
116 */
117 #define UHA_ENSINT 0x80 /* enable system doorbell interrupt */
118 #define UHA_EN_ABORT_COMPLETE 0x10 /* enable abort MSCP complete int */
119 #define UHA_ENICM 0x01 /* enable ICM interrupt */
120
121 /*
122 * UHA_SINT bits (read)
123 */
124 #define U14_SDIP 0x80 /* system doorbell int pending */
125 #define U24_SDIP 0x02 /* system doorbell int pending */
126
127 #define UHA_ABORT_SUCC 0x10 /* abort MSCP successful */
128 #define UHA_ABORT_FAIL 0x18 /* abort MSCP failed */
129
130 /*
131 * UHA_SINT bits (write)
132 */
133 #define U14_ICM_ACK 0x01 /* acknowledge ICM and clear */
134 #define U24_ICM_ACK 0x02 /* acknowledge ICM and clear */
135
136 #define UHA_ABORT_ACK 0x18 /* acknowledge status and clear */
137
138 /*
139 * U14_CONFIG bits (read only)
140 */
141 #define U14_DMA_CH5 0x0000 /* DMA channel 5 */
142 #define U14_DMA_CH6 0x4000 /* 6 */
143 #define U14_DMA_CH7 0x8000 /* 7 */
144 #define U14_DMA_MASK 0xc000
145 #define U14_IRQ15 0x0000 /* IRQ 15 */
146 #define U14_IRQ14 0x1000 /* 14 */
147 #define U14_IRQ11 0x2000 /* 11 */
148 #define U14_IRQ10 0x3000 /* 10 */
149 #define U14_IRQ_MASK 0x3000
150 #define U14_HOSTID_MASK 0x0007
151
152 /*
153 * U24_CONFIG bits (read only)
154 */
155 #define U24_MAGIC1 0x08
156 #define U24_IRQ15 0x10
157 #define U24_IRQ14 0x20
158 #define U24_IRQ11 0x40
159 #define U24_IRQ10 0x80
160 #define U24_IRQ_MASK 0xf0
161
162 #define U24_MAGIC2 0x04
163
164 #define U24_HOSTID_MASK 0x07
165
166 /*
167 * EISA registers (offset from slot base)
168 */
169 #define EISA_VENDOR 0x0c80 /* vendor ID (2 ports) */
170 #define EISA_MODEL 0x0c82 /* model number (2 ports) */
171 #define EISA_CONTROL 0x0c84
172 #define EISA_RESET 0x04
173 #define EISA_ERROR 0x02
174 #define EISA_ENABLE 0x01
175
176 /*
177 * host_stat error codes
178 */
179 #define UHA_NO_ERR 0x00 /* No error supposedly */
180 #define UHA_SBUS_ABORT_ERR 0x84 /* scsi bus abort error */
181 #define UHA_SBUS_TIMEOUT 0x91 /* scsi bus selection timeout */
182 #define UHA_SBUS_OVER_UNDER 0x92 /* scsi bus over/underrun */
183 #define UHA_BAD_SCSI_CMD 0x96 /* illegal scsi command */
184 #define UHA_AUTO_SENSE_ERR 0x9b /* auto request sense err */
185 #define UHA_SBUS_RES_ERR 0xa3 /* scsi bus reset error */
186 #define UHA_BAD_SG_LIST 0xff /* invalid scatter gath list */
187
188 #define UHA_NSEG 33 /* number of DMA segments supported */
189
190 struct uha_dma_seg {
191 physaddr seg_addr;
192 physlen seg_len;
193 };
194
195 #pragma pack(1)
196 struct uha_mscp {
197 u_char opcode:3;
198 #define UHA_HAC 0x01 /* host adapter command */
199 #define UHA_TSP 0x02 /* target scsi pass through command */
200 #define UHA_SDR 0x04 /* scsi device reset */
201 u_char xdir:2; /* xfer direction */
202 #define UHA_SDET 0x00 /* determined by scsi command */
203 #define UHA_SDIN 0x01 /* scsi data in */
204 #define UHA_SDOUT 0x02 /* scsi data out */
205 #define UHA_NODATA 0x03 /* no data xfer */
206 u_char dcn:1; /* disable disconnect for this command */
207 u_char ca:1; /* cache control */
208 u_char sgth:1; /* scatter gather flag */
209 u_char target:3;
210 u_char chan:2; /* scsi channel (always 0 for 14f) */
211 u_char lun:3;
212 physaddr data_addr;
213 physlen data_length;
214 physaddr link_addr;
215 u_char link_id;
216 u_char sg_num; /* number of scat gath segs */
217 /*in s-g list if sg flag is */
218 /*set. starts at 1, 8bytes per */
219 u_char req_sense_length;
220 u_char scsi_cmd_length;
221 struct scsi_generic scsi_cmd;
222 u_char host_stat;
223 u_char target_stat;
224 physaddr sense_ptr; /* if 0 no auto sense */
225
226 struct uha_dma_seg uha_dma[UHA_NSEG];
227 struct scsipi_sense_data mscp_sense;
228 /*-----------------end of hardware supported fields----------------*/
229 TAILQ_ENTRY(uha_mscp) chain;
230 struct uha_mscp *nexthash;
231 u_long hashkey;
232 struct scsipi_xfer *xs; /* the scsipi_xfer for this cmd */
233 int flags;
234 #define MSCP_ALLOC 0x01
235 #define MSCP_ABORT 0x02
236 int timeout;
237
238 /*
239 * This DMA map maps the buffer involved in the transfer.
240 * It's contents are loaded into "uha_dma" above.
241 */
242 bus_dmamap_t dmamap_xfer;
243
244 };
245 #pragma pack()
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