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sys/dev/ic/wd33c93.c
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1 /* $NetBSD: wd33c93.c,v 1.9 2006/10/01 22:02:55 bjh21 Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 35 */ 36 37 /* 38 * Changes Copyright (c) 2001 Wayne Knowles 39 * Changes Copyright (c) 1996 Steve Woodford 40 * Original Copyright (c) 1994 Christian E. Hopps 41 * 42 * This code is derived from software contributed to Berkeley by 43 * Van Jacobson of Lawrence Berkeley Laboratory. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)scsi.c 7.5 (Berkeley) 5/4/91 74 */ 75 76 /* 77 * This version of the driver is pretty well generic, so should work with 78 * any flavour of WD33C93 chip. 79 */ 80 81 #include <sys/cdefs.h> 82 __KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.9 2006/10/01 22:02:55 bjh21 Exp $"); 83 84 #include "opt_ddb.h" 85 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/device.h> 89 #include <sys/kernel.h> /* For hz */ 90 #include <sys/disklabel.h> 91 #include <sys/buf.h> 92 93 #include <dev/scsipi/scsi_all.h> 94 #include <dev/scsipi/scsipi_all.h> 95 #include <dev/scsipi/scsiconf.h> 96 #include <dev/scsipi/scsi_message.h> 97 98 #include <uvm/uvm_extern.h> 99 100 #include <machine/bus.h> 101 102 #include <dev/ic/wd33c93reg.h> 103 #include <dev/ic/wd33c93var.h> 104 105 /* 106 * SCSI delays 107 * In u-seconds, primarily for state changes on the SPC. 108 */ 109 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */ 110 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */ 111 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */ 112 113 #define STATUS_UNKNOWN 0xff /* uninitialized status */ 114 115 /* 116 * Convenience macro for waiting for a particular wd33c93 event 117 */ 118 #define SBIC_WAIT(regs, until, timeo) wd33c93_wait(regs, until, timeo, __LINE__) 119 120 void wd33c93_init (struct wd33c93_softc *); 121 void wd33c93_reset (struct wd33c93_softc *); 122 int wd33c93_go (struct wd33c93_softc *, struct wd33c93_acb *); 123 int wd33c93_dmaok (struct wd33c93_softc *, struct scsipi_xfer *); 124 int wd33c93_wait (struct wd33c93_softc *, u_char, int , int); 125 u_char wd33c93_selectbus (struct wd33c93_softc *, struct wd33c93_acb *); 126 int wd33c93_xfout (struct wd33c93_softc *, int, void *); 127 int wd33c93_xfin (struct wd33c93_softc *, int, void *); 128 int wd33c93_poll (struct wd33c93_softc *, struct wd33c93_acb *); 129 int wd33c93_nextstate (struct wd33c93_softc *, struct wd33c93_acb *, 130 u_char, u_char); 131 int wd33c93_abort (struct wd33c93_softc *, struct wd33c93_acb *, 132 const char *); 133 void wd33c93_xferdone (struct wd33c93_softc *); 134 void wd33c93_error (struct wd33c93_softc *, struct wd33c93_acb *); 135 void wd33c93_scsidone (struct wd33c93_softc *, struct wd33c93_acb *, int); 136 void wd33c93_sched (struct wd33c93_softc *); 137 void wd33c93_dequeue (struct wd33c93_softc *, struct wd33c93_acb *); 138 void wd33c93_dma_stop (struct wd33c93_softc *); 139 void wd33c93_dma_setup (struct wd33c93_softc *, int); 140 int wd33c93_msgin_phase (struct wd33c93_softc *, int); 141 void wd33c93_msgin (struct wd33c93_softc *, u_char *, int); 142 void wd33c93_reselect (struct wd33c93_softc *, int, int, int, int); 143 void wd33c93_sched_msgout (struct wd33c93_softc *, u_short); 144 void wd33c93_msgout (struct wd33c93_softc *); 145 void wd33c93_timeout (void *arg); 146 void wd33c93_watchdog (void *arg); 147 int wd33c93_div2stp (struct wd33c93_softc *, int); 148 int wd33c93_stp2div (struct wd33c93_softc *, int); 149 void wd33c93_setsync (struct wd33c93_softc *, struct wd33c93_tinfo *); 150 void wd33c93_update_xfer_mode (struct wd33c93_softc *, int); 151 152 static struct pool wd33c93_pool; /* Adapter Control Blocks */ 153 static int wd33c93_pool_initialized = 0; 154 155 /* 156 * Timeouts 157 */ 158 int wd33c93_cmd_wait = SBIC_CMD_WAIT; 159 int wd33c93_data_wait = SBIC_DATA_WAIT; 160 int wd33c93_init_wait = SBIC_INIT_WAIT; 161 162 int wd33c93_nodma = 0; /* Use polled IO transfers */ 163 int wd33c93_nodisc = 0; /* Allow command queues */ 164 int wd33c93_notags = 0; /* No Tags */ 165 166 /* 167 * Some useful stuff for debugging purposes 168 */ 169 #ifdef DEBUG 170 171 #define QPRINTF(a) SBIC_DEBUG(MISC, a) 172 173 int wd33c93_debug = 0; /* Debug flags */ 174 175 void wd33c93_print_csr (u_char); 176 void wd33c93_hexdump (u_char *, int); 177 178 #else 179 #define QPRINTF(a) /* */ 180 #endif 181 182 static const char *wd33c93_chip_names[] = SBIC_CHIP_LIST; 183 184 /* 185 * Attach instance of driver and probe for sub devices 186 */ 187 void 188 wd33c93_attach(struct wd33c93_softc *dev) 189 { 190 struct scsipi_adapter *adapt = &dev->sc_adapter; 191 struct scsipi_channel *chan = &dev->sc_channel; 192 193 adapt->adapt_dev = &dev->sc_dev; 194 adapt->adapt_nchannels = 1; 195 adapt->adapt_openings = 256; 196 adapt->adapt_max_periph = 256; /* Max tags per device */ 197 adapt->adapt_ioctl = NULL; 198 /* adapt_request initialized by MD interface */ 199 /* adapt_minphys initialized by MD interface */ 200 201 memset(chan, 0, sizeof(*chan)); 202 chan->chan_adapter = &dev->sc_adapter; 203 chan->chan_bustype = &scsi_bustype; 204 chan->chan_channel = 0; 205 chan->chan_ntargets = SBIC_NTARG; 206 chan->chan_nluns = SBIC_NLUN; 207 chan->chan_id = dev->sc_id; 208 209 callout_init(&dev->sc_watchdog); 210 211 dev->sc_maxoffset = SBIC_SYN_MAX_OFFSET; /* Max Sync Offset */ 212 213 /* 214 * Add reference to adapter so that we drop the reference after 215 * config_found() to make sure the adatper is disabled. 216 */ 217 if (scsipi_adapter_addref(&dev->sc_adapter) != 0) { 218 printf("%s: unable to enable controller\n", 219 dev->sc_dev.dv_xname); 220 return; 221 } 222 223 dev->sc_cfflags = device_cfdata(&dev->sc_dev)->cf_flags; 224 wd33c93_init(dev); 225 226 printf(": %s revision %d, %d.%d MHz, SCSI ID %d\n", 227 wd33c93_chip_names[dev->sc_chip], dev->sc_rev, 228 dev->sc_clkfreq / 10, dev->sc_clkfreq % 10, 229 dev->sc_channel.chan_id); 230 231 dev->sc_child = config_found(&dev->sc_dev, &dev->sc_channel, 232 scsiprint); 233 scsipi_adapter_delref(&dev->sc_adapter); 234 } 235 236 /* 237 * Initialize driver-private structures 238 */ 239 void 240 wd33c93_init(struct wd33c93_softc *dev) 241 { 242 u_int i; 243 244 if (!wd33c93_pool_initialized) { 245 /* All instances share the same pool */ 246 pool_init(&wd33c93_pool, sizeof(struct wd33c93_acb), 0, 0, 0, 247 "wd33c93_acb", NULL); 248 ++wd33c93_pool_initialized; 249 } 250 251 if (dev->sc_state == 0) { 252 TAILQ_INIT(&dev->ready_list); 253 254 dev->sc_nexus = NULL; 255 dev->sc_disc = 0; 256 memset(dev->sc_tinfo, 0, sizeof(dev->sc_tinfo)); 257 258 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 259 } else 260 panic("wd33c93: reinitializing driver!"); 261 262 dev->sc_flags = 0; 263 dev->sc_state = SBIC_IDLE; 264 wd33c93_reset(dev); 265 266 for (i = 0; i < 8; i++) { 267 struct wd33c93_tinfo *ti = &dev->sc_tinfo[i]; 268 /* 269 * sc_flags = 0xTTRRSS 270 * 271 * TT = Bitmask to disable Tagged Queues 272 * RR = Bitmask to disable disconnect/reselect 273 * SS = Bitmask to diable Sync negotiation 274 */ 275 ti->flags = T_NEED_RESET; 276 if (dev->sc_cfflags & (1<<(i+8))) 277 ti->flags |= T_NOSYNC; 278 if (dev->sc_cfflags & (1<<i) || wd33c93_nodisc) 279 ti->flags |= T_NODISC; 280 ti->period = dev->sc_syncperiods[0]; 281 ti->offset = 0; 282 } 283 } 284 285 void 286 wd33c93_reset(struct wd33c93_softc *dev) 287 { 288 u_int my_id, s, div, i; 289 u_char csr, reg; 290 291 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 292 WAIT_CIP(dev); 293 294 s = splbio(); 295 296 if (dev->sc_reset != NULL) 297 (*dev->sc_reset)(dev); 298 299 my_id = dev->sc_channel.chan_id & SBIC_ID_MASK; 300 /* 301 * Choose a suitable clock divisor and work out the resulting 302 * sync transfer periods in 4ns units. 303 */ 304 if (dev->sc_clkfreq < 110) { 305 my_id |= SBIC_ID_FS_8_10; 306 div = 2; 307 } else if (dev->sc_clkfreq < 160) { 308 my_id |= SBIC_ID_FS_12_15; 309 div = 3; 310 } else if (dev->sc_clkfreq < 210) { 311 my_id |= SBIC_ID_FS_16_20; 312 div = 4; 313 } else 314 panic("wd33c93: invalid clock speed %d", dev->sc_clkfreq); 315 for (i = 0; i < 7; i++) 316 dev->sc_syncperiods[i] = 317 (i + 2) * div * 1250 / dev->sc_clkfreq; 318 SBIC_DEBUG(SYNC, ("available sync periods: %d %d %d %d %d %d %d\n", 319 dev->sc_syncperiods[0], dev->sc_syncperiods[1], 320 dev->sc_syncperiods[2], dev->sc_syncperiods[3], 321 dev->sc_syncperiods[4], dev->sc_syncperiods[5], 322 dev->sc_syncperiods[6])); 323 324 /* Enable advanced features */ 325 #if 1 326 my_id |= SBIC_ID_EAF; /* XXX - MD Layer */ 327 #endif 328 329 SET_SBIC_myid(dev, my_id); 330 331 /* Reset the chip */ 332 SET_SBIC_cmd(dev, SBIC_CMD_RESET); 333 DELAY(25); 334 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 335 336 /* Set up various chip parameters */ 337 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 338 339 GET_SBIC_csr(dev, csr); /* clears interrupt also */ 340 GET_SBIC_cdb1(dev, dev->sc_rev); 341 342 switch (csr) { 343 case SBIC_CSR_RESET: 344 dev->sc_chip = SBIC_CHIP_WD33C93; 345 break; 346 case SBIC_CSR_RESET_AM: 347 SET_SBIC_queue_tag(dev, 0x55); 348 GET_SBIC_queue_tag(dev, reg); 349 dev->sc_chip = (reg == 0x55) ? 350 SBIC_CHIP_WD33C93B : SBIC_CHIP_WD33C93A; 351 SET_SBIC_queue_tag(dev, 0x0); 352 break; 353 default: 354 dev->sc_chip = SBIC_CHIP_UNKNOWN; 355 } 356 357 /* 358 * don't allow Selection (SBIC_RID_ES) 359 * until we can handle target mode!! 360 */ 361 SET_SBIC_rselid(dev, SBIC_RID_ER); 362 363 /* Asynchronous for now */ 364 SET_SBIC_syn(dev, 0); 365 366 dev->sc_flags = 0; 367 dev->sc_state = SBIC_IDLE; 368 369 splx(s); 370 } 371 372 void 373 wd33c93_error(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 374 { 375 struct scsipi_xfer *xs = acb->xs; 376 377 KASSERT(xs); 378 379 if (xs->xs_control & XS_CTL_SILENT) 380 return; 381 382 scsipi_printaddr(xs->xs_periph); 383 printf("SCSI Error\n"); 384 } 385 386 /* 387 * Setup sync mode for given target 388 */ 389 void 390 wd33c93_setsync(struct wd33c93_softc *dev, struct wd33c93_tinfo *ti) 391 { 392 u_char offset, period; 393 394 if (ti->flags & T_SYNCMODE) { 395 offset = ti->offset; 396 period = wd33c93_stp2div(dev, ti->period); 397 } else { 398 offset = 0; 399 period = 0; 400 } 401 402 SBIC_DEBUG(SYNC, ("wd33c93_setsync: sync reg = 0x%02x\n", 403 SBIC_SYN(offset, period))); 404 SET_SBIC_syn(dev, SBIC_SYN(offset, period)); 405 } 406 407 /* 408 * Check if current operation can be done using DMA 409 * 410 * returns 1 if DMA OK, 0 for polled I/O transfer 411 */ 412 int 413 wd33c93_dmaok(struct wd33c93_softc *dev, struct scsipi_xfer *xs) 414 { 415 if (wd33c93_nodma || (xs->xs_control & XS_CTL_POLL) || xs->datalen == 0) 416 return (0); 417 return(1); 418 } 419 420 /* 421 * Setup for DMA transfer 422 */ 423 void 424 wd33c93_dma_setup(struct wd33c93_softc *dev, int datain) 425 { 426 struct wd33c93_acb *acb = dev->sc_nexus; 427 int s; 428 429 dev->sc_daddr = acb->daddr; 430 dev->sc_dleft = acb->dleft; 431 432 s = splbio(); 433 /* Indicate that we're in DMA mode */ 434 if (dev->sc_dleft) { 435 dev->sc_dmasetup(dev, &dev->sc_daddr, &dev->sc_dleft, 436 datain, &dev->sc_dleft); 437 } 438 splx(s); 439 return; 440 } 441 442 443 /* 444 * Save DMA pointers. Take into account partial transfer. Shut down DMA. 445 */ 446 void 447 wd33c93_dma_stop(struct wd33c93_softc *dev) 448 { 449 size_t count; 450 int asr; 451 452 /* Wait until WD chip is idle */ 453 do { 454 GET_SBIC_asr(dev, asr); /* XXX */ 455 if (asr & SBIC_ASR_DBR) { 456 printf("wd33c93_dma_stop: asr %02x canceled!\n", asr); 457 break; 458 } 459 } while (asr & (SBIC_ASR_BSY|SBIC_ASR_CIP)); 460 461 /* Only need to save pointers if DMA was active */ 462 if (dev->sc_flags & SBICF_INDMA) { 463 int s = splbio(); 464 465 /* Shut down DMA and flush FIFO's */ 466 dev->sc_dmastop(dev); 467 468 /* Fetch the residual count */ 469 SBIC_TC_GET(dev, count); 470 471 /* Work out how many bytes were actually transferred */ 472 count = dev->sc_tcnt - count; 473 474 if (dev->sc_dleft < count) 475 printf("xfer too large: dleft=%zu resid=%zu\n", 476 dev->sc_dleft, count); 477 478 /* Fixup partial xfers */ 479 dev->sc_daddr += count; 480 dev->sc_dleft -= count; 481 dev->sc_tcnt = 0; 482 dev->sc_flags &= ~SBICF_INDMA; 483 splx(s); 484 SBIC_DEBUG(DMA, ("dma_stop\n")); 485 } 486 /* 487 * Ensure the WD chip is back in polled I/O mode, with nothing to 488 * transfer. 489 */ 490 SBIC_TC_PUT(dev, 0); 491 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 492 } 493 494 495 /* 496 * Handle new request from scsipi layer 497 */ 498 void 499 wd33c93_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg) 500 { 501 struct wd33c93_softc *dev = (void *)chan->chan_adapter->adapt_dev; 502 struct scsipi_xfer *xs; 503 struct scsipi_periph *periph; 504 struct wd33c93_acb *acb; 505 int flags, s; 506 507 switch (req) { 508 case ADAPTER_REQ_RUN_XFER: 509 xs = arg; 510 periph = xs->xs_periph; 511 flags = xs->xs_control; 512 513 if (flags & XS_CTL_DATA_UIO) 514 panic("wd33c93: scsi data uio requested"); 515 516 if (dev->sc_nexus && (flags & XS_CTL_POLL)) 517 panic("wd33c93_scsicmd: busy"); 518 519 s = splbio(); 520 acb = (struct wd33c93_acb *)pool_get(&wd33c93_pool, PR_NOWAIT); 521 splx(s); 522 523 if (acb == NULL) { 524 scsipi_printaddr(periph); 525 printf("cannot allocate acb\n"); 526 xs->error = XS_RESOURCE_SHORTAGE; 527 scsipi_done(xs); 528 return; 529 } 530 531 acb->flags = ACB_ACTIVE; 532 acb->xs = xs; 533 acb->clen = xs->cmdlen; 534 acb->daddr = xs->data; 535 acb->dleft = xs->datalen; 536 acb->timeout = xs->timeout; 537 memcpy(&acb->cmd, xs->cmd, xs->cmdlen); 538 539 if (flags & XS_CTL_POLL) { 540 /* 541 * Complete currently active command(s) before 542 * issuing an immediate command 543 */ 544 while (dev->sc_nexus) 545 wd33c93_poll(dev, dev->sc_nexus); 546 } 547 548 s = splbio(); 549 TAILQ_INSERT_TAIL(&dev->ready_list, acb, chain); 550 acb->flags |= ACB_READY; 551 552 /* If nothing is active, try to start it now. */ 553 if (dev->sc_state == SBIC_IDLE) 554 wd33c93_sched(dev); 555 splx(s); 556 557 if ((flags & XS_CTL_POLL) == 0) 558 return; 559 560 if (wd33c93_poll(dev, acb)) { 561 wd33c93_timeout(acb); 562 if (wd33c93_poll(dev, acb)) /* 2nd retry for ABORT */ 563 wd33c93_timeout(acb); 564 } 565 return; 566 567 case ADAPTER_REQ_GROW_RESOURCES: 568 /* XXX Not supported. */ 569 return; 570 571 case ADAPTER_REQ_SET_XFER_MODE: 572 { 573 struct wd33c93_tinfo *ti; 574 struct scsipi_xfer_mode *xm = arg; 575 576 ti = &dev->sc_tinfo[xm->xm_target]; 577 ti->flags &= ~T_WANTSYNC; 578 579 if ((dev->sc_cfflags & (1<<(xm->xm_target+16))) == 0 && 580 (xm->xm_mode & PERIPH_CAP_TQING) && !wd33c93_notags) 581 ti->flags |= T_TAG; 582 else 583 ti->flags &= ~T_TAG; 584 585 SBIC_DEBUG(SYNC, ("wd33c93_scsi_request: " 586 "target %d: scsipi requested %s\n", xm->xm_target, 587 (xm->xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 588 589 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 590 (ti->flags & T_NOSYNC) == 0) 591 ti->flags |= T_WANTSYNC; 592 /* 593 * If we're not going to negotiate, send the notification 594 * now, since it won't happen later. 595 */ 596 if (!(ti->flags & T_WANTSYNC) == !(ti->flags & T_SYNCMODE)) 597 wd33c93_update_xfer_mode(dev, xm->xm_target); 598 else 599 ti->flags |= T_NEGOTIATE; 600 return; 601 } 602 603 } 604 } 605 606 /* 607 * attempt to start the next available command 608 */ 609 void 610 wd33c93_sched(struct wd33c93_softc *dev) 611 { 612 struct scsipi_periph *periph = NULL; /* Gag the compiler */ 613 struct wd33c93_acb *acb; 614 struct wd33c93_tinfo *ti; 615 struct wd33c93_linfo *li; 616 int lun, tag, flags; 617 618 if (dev->sc_state != SBIC_IDLE) 619 return; 620 621 KASSERT(dev->sc_nexus == NULL); 622 623 /* Loop through the ready list looking for work to do... */ 624 TAILQ_FOREACH(acb, &dev->ready_list, chain) { 625 periph = acb->xs->xs_periph; 626 lun = periph->periph_lun; 627 ti = &dev->sc_tinfo[periph->periph_target]; 628 li = TINFO_LUN(ti, lun); 629 630 KASSERT(acb->flags & ACB_READY); 631 632 /* Select type of tag for this command */ 633 if ((ti->flags & T_NODISC) != 0) 634 tag = 0; 635 else if ((ti->flags & T_TAG) == 0) 636 tag = 0; 637 else if ((acb->flags & ACB_SENSE) != 0) 638 tag = 0; 639 else if (acb->xs->xs_control & XS_CTL_POLL) 640 tag = 0; /* No tags for polled commands */ 641 else 642 tag = acb->xs->xs_tag_type; 643 644 if (li == NULL) { 645 /* Initialize LUN info and add to list. */ 646 li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT); 647 if (li == NULL) 648 continue; 649 memset(li, 0, sizeof(*li)); 650 li->lun = lun; 651 if (lun < SBIC_NLUN) 652 ti->lun[lun] = li; 653 } 654 li->last_used = time_second; 655 656 /* 657 * We've found a potential command, but is the target/lun busy? 658 */ 659 660 if (tag == 0 && li->untagged == NULL) 661 li->untagged = acb; /* Issue untagged */ 662 663 if (li->untagged != NULL) { 664 tag = 0; 665 if ((li->state != L_STATE_BUSY) && li->used == 0) { 666 /* Issue this untagged command now */ 667 acb = li->untagged; 668 periph = acb->xs->xs_periph; 669 } else /* Not ready yet */ 670 continue; 671 } 672 673 acb->tag_type = tag; 674 if (tag != 0) { 675 if (li->queued[acb->xs->xs_tag_id]) 676 printf("queueing to active tag\n"); 677 li->queued[acb->xs->xs_tag_id] = acb; 678 acb->tag_id = acb->xs->xs_tag_id; 679 li->used++; 680 break; 681 } 682 if (li->untagged != NULL && (li->state != L_STATE_BUSY)) { 683 li->state = L_STATE_BUSY; 684 break; 685 } 686 if (li->untagged == NULL && tag != 0) { 687 break; 688 } else 689 printf("%d:%d busy\n", periph->periph_target, 690 periph->periph_lun); 691 } 692 693 if (acb == NULL) { 694 SBIC_DEBUG(ACBS, ("wd33c93sched: no work\n")); 695 return; /* did not find an available command */ 696 } 697 698 SBIC_DEBUG(ACBS, ("wd33c93_sched(%d,%d)\n", periph->periph_target, 699 periph->periph_lun)); 700 701 TAILQ_REMOVE(&dev->ready_list, acb, chain); 702 acb->flags &= ~ACB_READY; 703 704 flags = acb->xs->xs_control; 705 if (flags & XS_CTL_RESET) 706 wd33c93_reset(dev); 707 708 /* XXX - Implicitly call scsidone on select timeout */ 709 if (wd33c93_go(dev, acb) != 0 || acb->xs->error == XS_SELTIMEOUT) { 710 acb->dleft = dev->sc_dleft; 711 wd33c93_scsidone(dev, acb, dev->sc_status); 712 return; 713 } 714 715 return; 716 } 717 718 void 719 wd33c93_scsidone(struct wd33c93_softc *dev, struct wd33c93_acb *acb, int status) 720 { 721 struct scsipi_xfer *xs = acb->xs; 722 struct wd33c93_tinfo *ti; 723 struct wd33c93_linfo *li; 724 int s; 725 726 #ifdef DIAGNOSTIC 727 KASSERT(dev->target == xs->xs_periph->periph_target); 728 KASSERT(dev->lun == xs->xs_periph->periph_lun); 729 if (acb == NULL || xs == NULL) { 730 panic("wd33c93_scsidone -- (%d,%d) no scsipi_xfer", 731 dev->target, dev->lun); 732 } 733 KASSERT(acb->flags != ACB_FREE); 734 #endif 735 736 SBIC_DEBUG(ACBS, ("scsidone: (%d,%d)->(%d,%d)%02x\n", 737 xs->xs_periph->periph_target, xs->xs_periph->periph_lun, 738 dev->target, dev->lun, status)); 739 callout_stop(&xs->xs_callout); 740 741 xs->status = status & SCSI_STATUS_MASK; 742 xs->resid = acb->dleft; 743 744 if (xs->error == XS_NOERROR) { 745 switch (xs->status) { 746 case SCSI_CHECK: 747 case SCSI_TERMINATED: 748 /* XXX Need to read sense - return busy for now */ 749 /*FALLTHROUGH*/ 750 case SCSI_QUEUE_FULL: 751 case SCSI_BUSY: 752 xs->error = XS_BUSY; 753 break; 754 } 755 } 756 757 ti = &dev->sc_tinfo[dev->target]; 758 li = TINFO_LUN(ti, dev->lun); 759 ti->cmds++; 760 if (xs->error == XS_SELTIMEOUT) { 761 /* Selection timeout -- discard this LUN if empty */ 762 if (li->untagged == NULL && li->used == 0) { 763 if (dev->lun < SBIC_NLUN) 764 ti->lun[dev->lun] = NULL; 765 free(li, M_DEVBUF); 766 } 767 } 768 769 wd33c93_dequeue(dev, acb); 770 if (dev->sc_nexus == acb) { 771 dev->sc_state = SBIC_IDLE; 772 dev->sc_nexus = NULL; 773 dev->sc_flags = 0; 774 775 if (!TAILQ_EMPTY(&dev->ready_list)) 776 wd33c93_sched(dev); 777 } 778 779 /* place control block back on free list. */ 780 s = splbio(); 781 acb->flags = ACB_FREE; 782 pool_put(&wd33c93_pool, (void *)acb); 783 splx(s); 784 785 scsipi_done(xs); 786 } 787 788 void 789 wd33c93_dequeue(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 790 { 791 struct wd33c93_tinfo *ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 792 struct wd33c93_linfo *li; 793 int lun = acb->xs->xs_periph->periph_lun; 794 795 li = TINFO_LUN(ti, lun); 796 #ifdef DIAGNOSTIC 797 if (li == NULL || li->lun != lun) 798 panic("wd33c93_dequeue: lun %d for ecb %p does not exist", 799 lun, acb); 800 #endif 801 if (li->untagged == acb) { 802 li->state = L_STATE_IDLE; 803 li->untagged = NULL; 804 } 805 if (acb->tag_type && li->queued[acb->tag_id] != NULL) { 806 #ifdef DIAGNOSTIC 807 if (li->queued[acb->tag_id] != NULL && 808 (li->queued[acb->tag_id] != acb)) 809 panic("wd33c93_dequeue: slot %d for lun %d has %p " 810 "instead of acb %p\n", acb->tag_id, 811 lun, li->queued[acb->tag_id], acb); 812 #endif 813 li->queued[acb->tag_id] = NULL; 814 li->used--; 815 } 816 } 817 818 819 int 820 wd33c93_wait(struct wd33c93_softc *dev, u_char until, int timeo, int line) 821 { 822 u_char val; 823 824 if (timeo == 0) 825 timeo = 1000000; /* some large value.. */ 826 GET_SBIC_asr(dev, val); 827 while ((val & until) == 0) { 828 if (timeo-- == 0) { 829 int csr; 830 GET_SBIC_csr(dev, csr); 831 printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n", 832 line, val, csr); 833 #if defined(DDB) && defined(DEBUG) 834 Debugger(); 835 #endif 836 return(val); /* Maybe I should abort */ 837 break; 838 } 839 DELAY(1); 840 GET_SBIC_asr(dev, val); 841 } 842 return(val); 843 } 844 845 int 846 wd33c93_abort(struct wd33c93_softc *dev, struct wd33c93_acb *acb, 847 const char *where) 848 { 849 u_char csr, asr; 850 851 GET_SBIC_asr(dev, asr); 852 GET_SBIC_csr(dev, csr); 853 854 scsipi_printaddr(acb->xs->xs_periph); 855 printf ("ABORT in %s: csr=0x%02x, asr=0x%02x\n", where, csr, asr); 856 857 acb->timeout = SBIC_ABORT_TIMEOUT; 858 acb->flags |= ACB_ABORT; 859 860 /* 861 * Clean up chip itself 862 */ 863 if (dev->sc_nexus == acb) { 864 /* Reschedule timeout. */ 865 callout_reset(&acb->xs->xs_callout, mstohz(acb->timeout), 866 wd33c93_timeout, acb); 867 868 while (asr & SBIC_ASR_DBR) { 869 /* 870 * wd33c93 is jammed w/data. need to clear it 871 * But we don't know what direction it needs to go 872 */ 873 GET_SBIC_data(dev, asr); 874 printf("abort %s: clearing data buffer 0x%02x\n", 875 where, asr); 876 GET_SBIC_asr(dev, asr); 877 if (asr & SBIC_ASR_DBR) /* Not the read direction */ 878 SET_SBIC_data(dev, asr); 879 GET_SBIC_asr(dev, asr); 880 } 881 882 scsipi_printaddr(acb->xs->xs_periph); 883 printf("sending ABORT command\n"); 884 885 WAIT_CIP(dev); 886 SET_SBIC_cmd(dev, SBIC_CMD_ABORT); 887 WAIT_CIP(dev); 888 889 GET_SBIC_asr(dev, asr); 890 891 scsipi_printaddr(acb->xs->xs_periph); 892 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) { 893 /* 894 * ok, get more drastic.. 895 */ 896 printf("Resetting bus\n"); 897 wd33c93_reset(dev); 898 } else { 899 printf("sending DISCONNECT to target\n"); 900 SET_SBIC_cmd(dev, SBIC_CMD_DISC); 901 WAIT_CIP(dev); 902 903 do { 904 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 905 GET_SBIC_asr(dev, asr); 906 GET_SBIC_csr(dev, csr); 907 SBIC_DEBUG(MISC, ("csr: 0x%02x, asr: 0x%02x\n", 908 csr, asr)); 909 } while ((csr != SBIC_CSR_DISC) && 910 (csr != SBIC_CSR_DISC_1) && 911 (csr != SBIC_CSR_CMD_INVALID)); 912 } 913 dev->sc_state = SBIC_ERROR; 914 dev->sc_flags = 0; 915 } 916 return SBIC_STATE_ERROR; 917 } 918 919 920 /* 921 * select the bus, return when selected or error. 922 * 923 * Returns the current CSR following selection and optionally MSG out phase. 924 * i.e. the returned CSR *should* indicate CMD phase... 925 * If the return value is 0, some error happened. 926 */ 927 u_char 928 wd33c93_selectbus(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 929 { 930 struct scsipi_xfer *xs = acb->xs; 931 struct wd33c93_tinfo *ti; 932 u_char target, lun, asr, csr, id; 933 934 KASSERT(dev->sc_state == SBIC_IDLE); 935 936 target = xs->xs_periph->periph_target; 937 lun = xs->xs_periph->periph_lun; 938 ti = &dev->sc_tinfo[target]; 939 940 dev->sc_state = SBIC_SELECTING; 941 dev->target = target; 942 dev->lun = lun; 943 944 SBIC_DEBUG(PHASE, ("wd33c93_selectbus %d: ", target)); 945 946 if ((xs->xs_control & XS_CTL_POLL) == 0) 947 callout_reset(&xs->xs_callout, mstohz(acb->timeout), 948 wd33c93_timeout, acb); 949 950 /* 951 * issue select 952 */ 953 SBIC_TC_PUT(dev, 0); 954 SET_SBIC_selid(dev, target); 955 SET_SBIC_timeo(dev, SBIC_TIMEOUT(250, dev->sc_clkfreq)); 956 957 GET_SBIC_asr(dev, asr); 958 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) { 959 /* This means we got ourselves reselected upon */ 960 SBIC_DEBUG(PHASE, ("WD busy (reselect?) ASR=%02x\n", asr)); 961 return 0; 962 } 963 964 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN); 965 WAIT_CIP(dev); 966 967 /* 968 * wait for select (merged from separate function may need 969 * cleanup) 970 */ 971 do { 972 asr = SBIC_WAIT(dev, SBIC_ASR_INT | SBIC_ASR_LCI, 0); 973 if (asr & SBIC_ASR_LCI) { 974 QPRINTF(("late LCI: asr %02x\n", asr)); 975 return 0; 976 } 977 978 /* Clear interrupt */ 979 GET_SBIC_csr (dev, csr); 980 981 /* Reselected from under our feet? */ 982 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) { 983 SBIC_DEBUG(PHASE, ("got reselected, asr %02x\n", asr)); 984 /* 985 * We need to handle this now so we don't lock up later 986 */ 987 wd33c93_nextstate(dev, acb, csr, asr); 988 return 0; 989 } 990 991 /* Whoops! */ 992 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) { 993 panic("wd33c93_selectbus: target issued select!"); 994 return 0; 995 } 996 997 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) && 998 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) && 999 csr != SBIC_CSR_SEL_TIMEO); 1000 1001 /* Anyone at home? */ 1002 if (csr == SBIC_CSR_SEL_TIMEO) { 1003 xs->error = XS_SELTIMEOUT; 1004 SBIC_DEBUG(PHASE, ("-- Selection Timeout\n")); 1005 return 0; 1006 } 1007 1008 SBIC_DEBUG(PHASE, ("Selection Complete\n")); 1009 1010 /* Assume we're now selected */ 1011 GET_SBIC_selid(dev, id); 1012 if (id != target) { 1013 /* Something went wrong - wrong target was select */ 1014 printf("wd33c93_selectbus: wrong target selected;" 1015 " WANTED %d GOT %d", target, id); 1016 return 0; /* XXX: Need to call nexstate to handle? */ 1017 } 1018 1019 dev->sc_flags |= SBICF_SELECTED; 1020 dev->sc_state = SBIC_CONNECTED; 1021 1022 /* setup correct sync mode for this target */ 1023 wd33c93_setsync(dev, ti); 1024 1025 if (ti->flags & T_NODISC && dev->sc_disc == 0) 1026 SET_SBIC_rselid (dev, 0); /* Not expecting a reselect */ 1027 else 1028 SET_SBIC_rselid (dev, SBIC_RID_ER); 1029 1030 /* 1031 * We only really need to do anything when the target goes to MSG out 1032 * If the device ignored ATN, it's probably old and brain-dead, 1033 * but we'll try to support it anyhow. 1034 * If it doesn't support message out, it definately doesn't 1035 * support synchronous transfers, so no point in even asking... 1036 */ 1037 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) { 1038 if (ti->flags & T_NEGOTIATE) { 1039 /* Inititae a SDTR message */ 1040 SBIC_DEBUG(SYNC, ("Sending SDTR to target %d\n", id)); 1041 if (ti->flags & T_WANTSYNC) { 1042 ti->period = dev->sc_syncperiods[0]; 1043 ti->offset = dev->sc_maxoffset; 1044 } else { 1045 ti->period = 0; 1046 ti->offset = 0; 1047 } 1048 /* Send Sync negotiation message */ 1049 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 0); /* No Disc */ 1050 dev->sc_omsg[1] = MSG_EXTENDED; 1051 dev->sc_omsg[2] = MSG_EXT_SDTR_LEN; 1052 dev->sc_omsg[3] = MSG_EXT_SDTR; 1053 if (ti->flags & T_WANTSYNC) { 1054 dev->sc_omsg[4] = dev->sc_syncperiods[0]; 1055 dev->sc_omsg[5] = dev->sc_maxoffset; 1056 } else { 1057 dev->sc_omsg[4] = 0; 1058 dev->sc_omsg[5] = 0; 1059 } 1060 wd33c93_xfout(dev, 6, dev->sc_omsg); 1061 dev->sc_msgout |= SEND_SDTR; /* may be rejected */ 1062 dev->sc_flags |= SBICF_SYNCNEGO; 1063 } else { 1064 if (dev->sc_nexus->tag_type != 0) { 1065 /* Use TAGS */ 1066 SBIC_DEBUG(TAGS, ("<select %d:%d TAG=%x>\n", 1067 dev->target, dev->lun, 1068 dev->sc_nexus->tag_id)); 1069 dev->sc_omsg[0] = MSG_IDENTIFY(lun, 1); 1070 dev->sc_omsg[1] = dev->sc_nexus->tag_type; 1071 dev->sc_omsg[2] = dev->sc_nexus->tag_id; 1072 wd33c93_xfout(dev, 3, dev->sc_omsg); 1073 dev->sc_msgout |= SEND_TAG; 1074 } else { 1075 int no_disc; 1076 1077 /* Setup LUN nexus and disconnect privilege */ 1078 no_disc = xs->xs_control & XS_CTL_POLL || 1079 ti->flags & T_NODISC; 1080 SEND_BYTE(dev, MSG_IDENTIFY(lun, !no_disc)); 1081 } 1082 } 1083 /* 1084 * There's one interrupt still to come: 1085 * the change to CMD phase... 1086 */ 1087 SBIC_WAIT(dev, SBIC_ASR_INT , 0); 1088 GET_SBIC_csr(dev, csr); 1089 } 1090 1091 return csr; 1092 } 1093 1094 /* 1095 * Information Transfer *to* a SCSI Target. 1096 * 1097 * Note: Don't expect there to be an interrupt immediately after all 1098 * the data is transferred out. The WD spec sheet says that the Transfer- 1099 * Info command for non-MSG_IN phases only completes when the target 1100 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state. 1101 * 1102 * This can have a nasty effect on commands which take a relatively long 1103 * time to complete, for example a START/STOP unit command may remain in 1104 * CMD phase until the disk has spun up. Only then will the target change 1105 * to STATUS phase. This is really only a problem for immediate commands 1106 * since we don't allow disconnection for them (yet). 1107 */ 1108 int 1109 wd33c93_xfout(struct wd33c93_softc *dev, int len, void *bp) 1110 { 1111 int wait = wd33c93_data_wait; 1112 u_char asr, *buf = bp; 1113 1114 QPRINTF(("wd33c93_xfout {%d} %02x %02x %02x %02x %02x " 1115 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2], 1116 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9])); 1117 1118 /* 1119 * sigh.. WD-PROTO strikes again.. sending the command in one go 1120 * causes the chip to lock up if talking to certain (misbehaving?) 1121 * targets. Anyway, this procedure should work for all targets, but 1122 * it's slightly slower due to the overhead 1123 */ 1124 1125 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1126 SBIC_TC_PUT (dev, (unsigned)len); 1127 1128 WAIT_CIP (dev); 1129 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1130 1131 /* 1132 * Loop for each byte transferred 1133 */ 1134 do { 1135 GET_SBIC_asr (dev, asr); 1136 1137 if (asr & SBIC_ASR_DBR) { 1138 if (len) { 1139 SET_SBIC_data (dev, *buf); 1140 buf++; 1141 len--; 1142 } else { 1143 SET_SBIC_data (dev, 0); 1144 } 1145 wait = wd33c93_data_wait; 1146 } 1147 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1148 1149 QPRINTF(("wd33c93_xfout done: %d bytes remaining (wait:%d)\n", len, wait)); 1150 1151 /* 1152 * Normally, an interrupt will be pending when this routing returns. 1153 */ 1154 return(len); 1155 } 1156 1157 /* 1158 * Information Transfer *from* a Scsi Target 1159 * returns # bytes left to read 1160 */ 1161 int 1162 wd33c93_xfin(struct wd33c93_softc *dev, int len, void *bp) 1163 { 1164 int wait = wd33c93_data_wait; 1165 u_char *buf = bp; 1166 u_char asr; 1167 #ifdef DEBUG 1168 u_char *obp = bp; 1169 #endif 1170 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1171 SBIC_TC_PUT (dev, (unsigned)len); 1172 1173 WAIT_CIP (dev); 1174 SET_SBIC_cmd (dev, SBIC_CMD_XFER_INFO); 1175 1176 /* 1177 * Loop for each byte transferred 1178 */ 1179 do { 1180 GET_SBIC_asr (dev, asr); 1181 1182 if (asr & SBIC_ASR_DBR) { 1183 if (len) { 1184 GET_SBIC_data (dev, *buf); 1185 buf++; 1186 len--; 1187 } else { 1188 u_char foo; 1189 GET_SBIC_data (dev, foo); 1190 } 1191 wait = wd33c93_data_wait; 1192 } 1193 1194 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0); 1195 1196 QPRINTF(("wd33c93_xfin {%d} %02x %02x %02x %02x %02x %02x " 1197 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2], 1198 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9])); 1199 1200 SBIC_TC_PUT (dev, 0); 1201 1202 /* 1203 * this leaves with one csr to be read 1204 */ 1205 return len; 1206 } 1207 1208 1209 /* 1210 * Finish SCSI xfer command: After the completion interrupt from 1211 * a read/write operation, sequence through the final phases in 1212 * programmed i/o. 1213 */ 1214 void 1215 wd33c93_xferdone(struct wd33c93_softc *dev) 1216 { 1217 u_char phase, csr; 1218 int s; 1219 1220 QPRINTF(("{")); 1221 s = splbio(); 1222 1223 /* 1224 * have the wd33c93 complete on its own 1225 */ 1226 SBIC_TC_PUT(dev, 0); 1227 SET_SBIC_cmd_phase(dev, 0x46); 1228 SET_SBIC_cmd(dev, SBIC_CMD_SEL_ATN_XFER); 1229 1230 do { 1231 SBIC_WAIT (dev, SBIC_ASR_INT, 0); 1232 GET_SBIC_csr (dev, csr); 1233 QPRINTF(("%02x:", csr)); 1234 } while ((csr != SBIC_CSR_DISC) && 1235 (csr != SBIC_CSR_DISC_1) && 1236 (csr != SBIC_CSR_S_XFERRED)); 1237 1238 dev->sc_flags &= ~SBICF_SELECTED; 1239 dev->sc_state = SBIC_DISCONNECT; 1240 1241 GET_SBIC_cmd_phase (dev, phase); 1242 QPRINTF(("}%02x", phase)); 1243 1244 if (phase == 0x60) 1245 GET_SBIC_tlun(dev, dev->sc_status); 1246 else 1247 wd33c93_error(dev, dev->sc_nexus); 1248 1249 QPRINTF(("=STS:%02x=\n", dev->sc_status)); 1250 splx(s); 1251 } 1252 1253 1254 int 1255 wd33c93_go(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1256 { 1257 struct scsipi_xfer *xs = acb->xs; 1258 int i, dmaok; 1259 u_char csr, asr; 1260 1261 SBIC_DEBUG(ACBS, ("wd33c93_go(%d:%d)\n", dev->target, dev->lun)); 1262 1263 dev->sc_nexus = acb; 1264 1265 dev->target = xs->xs_periph->periph_target; 1266 dev->lun = xs->xs_periph->periph_lun; 1267 1268 dev->sc_status = STATUS_UNKNOWN; 1269 dev->sc_daddr = acb->daddr; 1270 dev->sc_dleft = acb->dleft; 1271 1272 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 1273 dev->sc_flags = 0; 1274 1275 dmaok = wd33c93_dmaok(dev, xs); 1276 1277 if (dmaok == 0) 1278 dev->sc_flags |= SBICF_NODMA; 1279 1280 SBIC_DEBUG(DMA, ("wd33c93_go dmago:%d(tcnt=%zx) dmaok=%dx\n", 1281 dev->target, dev->sc_tcnt, dmaok)); 1282 1283 /* select the SCSI bus (it's an error if bus isn't free) */ 1284 if ((csr = wd33c93_selectbus(dev, acb)) == 0) 1285 return(0); /* Not done: needs to be rescheduled */ 1286 1287 /* 1288 * Lets cycle a while then let the interrupt handler take over. 1289 */ 1290 GET_SBIC_asr(dev, asr); 1291 do { 1292 QPRINTF(("go[0x%x] ", csr)); 1293 1294 /* Handle the new phase */ 1295 i = wd33c93_nextstate(dev, acb, csr, asr); 1296 WAIT_CIP(dev); /* XXX */ 1297 if (dev->sc_state == SBIC_CONNECTED) { 1298 1299 GET_SBIC_asr(dev, asr); 1300 1301 if (asr & SBIC_ASR_LCI) 1302 printf("wd33c93_go: LCI asr:%02x csr:%02x\n", asr, csr); 1303 1304 if (asr & SBIC_ASR_INT) 1305 GET_SBIC_csr(dev, csr); 1306 } 1307 1308 } while (dev->sc_state == SBIC_CONNECTED && 1309 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1310 1311 QPRINTF(("> done i=%d stat=%02x\n", i, dev->sc_status)); 1312 1313 if (i == SBIC_STATE_DONE) { 1314 if (dev->sc_status == STATUS_UNKNOWN) { 1315 printf("wd33c93_go: done & stat == UNKNOWN\n"); 1316 return 1; /* Did we really finish that fast? */ 1317 } 1318 } 1319 return 0; 1320 } 1321 1322 1323 int 1324 wd33c93_intr(struct wd33c93_softc *dev) 1325 { 1326 u_char asr, csr; 1327 int i; 1328 1329 /* 1330 * pending interrupt? 1331 */ 1332 GET_SBIC_asr (dev, asr); 1333 if ((asr & SBIC_ASR_INT) == 0) 1334 return(0); 1335 1336 GET_SBIC_csr(dev, csr); 1337 1338 do { 1339 SBIC_DEBUG(INTS, ("intr[csr=0x%x]", csr)); 1340 1341 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1342 WAIT_CIP(dev); /* XXX */ 1343 if (dev->sc_state == SBIC_CONNECTED) { 1344 GET_SBIC_asr(dev, asr); 1345 1346 if (asr & SBIC_ASR_LCI) 1347 printf("wd33c93_intr: LCI asr:%02x csr:%02x\n", 1348 asr, csr); 1349 1350 if (asr & SBIC_ASR_INT) 1351 GET_SBIC_csr(dev, csr); 1352 } 1353 } while (dev->sc_state == SBIC_CONNECTED && 1354 asr & (SBIC_ASR_INT|SBIC_ASR_LCI)); 1355 1356 SBIC_DEBUG(INTS, ("intr done. state=%d, asr=0x%02x\n", i, asr)); 1357 1358 return(1); 1359 } 1360 1361 /* 1362 * Complete current command using polled I/O. Used when interrupt driven 1363 * I/O is not allowed (ie. during boot and shutdown) 1364 * 1365 * Polled I/O is very processor intensive 1366 */ 1367 int 1368 wd33c93_poll(struct wd33c93_softc *dev, struct wd33c93_acb *acb) 1369 { 1370 u_char asr, csr=0; 1371 int i, count; 1372 struct scsipi_xfer *xs = acb->xs; 1373 1374 SBIC_WAIT(dev, SBIC_ASR_INT, wd33c93_cmd_wait); 1375 for (count=acb->timeout; count;) { 1376 GET_SBIC_asr (dev, asr); 1377 if (asr & SBIC_ASR_LCI) 1378 printf("wd33c93_poll: LCI; asr:%02x csr:%02x\n", 1379 asr, csr); 1380 if (asr & SBIC_ASR_INT) { 1381 GET_SBIC_csr(dev, csr); 1382 dev->sc_flags |= SBICF_NODMA; 1383 i = wd33c93_nextstate(dev, dev->sc_nexus, csr, asr); 1384 WAIT_CIP(dev); /* XXX */ 1385 } else { 1386 DELAY(1000); 1387 count--; 1388 } 1389 1390 if ((xs->xs_status & XS_STS_DONE) != 0) 1391 return (0); 1392 1393 if (dev->sc_state == SBIC_IDLE) { 1394 SBIC_DEBUG(ACBS, ("[poll: rescheduling] ")); 1395 wd33c93_sched(dev); 1396 } 1397 } 1398 return (1); 1399 } 1400 1401 static inline int 1402 __verify_msg_format(u_char *p, int len) 1403 { 1404 1405 if (len == 1 && MSG_IS1BYTE(p[0])) 1406 return 1; 1407 if (len == 2 && MSG_IS2BYTE(p[0])) 1408 return 1; 1409 if (len >= 3 && MSG_ISEXTENDED(p[0]) && 1410 len == p[1] + 2) 1411 return 1; 1412 return 0; 1413 } 1414 1415 /* 1416 * Handle message_in phase 1417 */ 1418 int 1419 wd33c93_msgin_phase(struct wd33c93_softc *dev, int reselect) 1420 { 1421 int len; 1422 u_char asr, csr, *msg; 1423 1424 GET_SBIC_asr(dev, asr); 1425 1426 SBIC_DEBUG(MSGS, ("wd33c93msgin asr=%02x\n", asr)); 1427 1428 GET_SBIC_selid (dev, csr); 1429 SET_SBIC_selid (dev, csr | SBIC_SID_FROM_SCSI); 1430 1431 SBIC_TC_PUT(dev, 0); 1432 1433 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1434 1435 msg = dev->sc_imsg; 1436 len = 0; 1437 1438 do { 1439 /* Fetch the next byte of the message */ 1440 RECV_BYTE(dev, *msg++); 1441 len++; 1442 1443 /* 1444 * get the command completion interrupt, or we 1445 * can't send a new command (LCI) 1446 */ 1447 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1448 GET_SBIC_csr(dev, csr); 1449 1450 if (__verify_msg_format(dev->sc_imsg, len)) 1451 break; /* Complete message recieved */ 1452 1453 /* 1454 * Clear ACK, and wait for the interrupt 1455 * for the next byte or phase change 1456 */ 1457 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1458 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1459 1460 GET_SBIC_csr(dev, csr); 1461 } while (len < SBIC_MAX_MSGLEN); 1462 1463 if (__verify_msg_format(dev->sc_imsg, len)) 1464 wd33c93_msgin(dev, dev->sc_imsg, len); 1465 1466 /* 1467 * Clear ACK, and wait for the interrupt 1468 * for the phase change 1469 */ 1470 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1471 SBIC_WAIT(dev, SBIC_ASR_INT, 0); 1472 1473 /* Should still have one CSR to read */ 1474 return SBIC_STATE_RUNNING; 1475 } 1476 1477 1478 void wd33c93_msgin(struct wd33c93_softc *dev, u_char *msgaddr, int msglen) 1479 { 1480 struct wd33c93_acb *acb = dev->sc_nexus; 1481 struct wd33c93_tinfo *ti = &dev->sc_tinfo[dev->target]; 1482 struct wd33c93_linfo *li; 1483 u_char asr; 1484 1485 switch (dev->sc_state) { 1486 case SBIC_CONNECTED: 1487 switch (msgaddr[0]) { 1488 case MSG_MESSAGE_REJECT: 1489 SBIC_DEBUG(MSGS, ("msgin: MSG_REJECT, " 1490 "last msgout=%x\n", dev->sc_msgout)); 1491 switch (dev->sc_msgout) { 1492 case SEND_TAG: 1493 printf("%s: tagged queuing rejected: " 1494 "target %d\n", 1495 dev->sc_dev.dv_xname, dev->target); 1496 ti->flags &= ~T_TAG; 1497 li = TINFO_LUN(ti, dev->lun); 1498 if (acb->tag_type && 1499 li->queued[acb->tag_id] != NULL) { 1500 li->queued[acb->tag_id] = NULL; 1501 li->used--; 1502 } 1503 acb->tag_type = acb->tag_id = 0; 1504 li->untagged = acb; 1505 li->state = L_STATE_BUSY; 1506 break; 1507 1508 case SEND_SDTR: 1509 printf("%s: sync transfer rejected: target %d\n", 1510 dev->sc_dev.dv_xname, dev->target); 1511 1512 dev->sc_flags &= ~SBICF_SYNCNEGO; 1513 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE); 1514 wd33c93_update_xfer_mode(dev, 1515 acb->xs->xs_periph->periph_target); 1516 wd33c93_setsync(dev, ti); 1517 1518 case SEND_INIT_DET_ERR: 1519 goto abort; 1520 1521 default: 1522 SBIC_DEBUG(MSGS, ("Unexpected MSG_REJECT\n")); 1523 break; 1524 } 1525 dev->sc_msgout = 0; 1526 break; 1527 1528 case MSG_HEAD_OF_Q_TAG: 1529 case MSG_ORDERED_Q_TAG: 1530 case MSG_SIMPLE_Q_TAG: 1531 printf("-- Out of phase TAG;" 1532 "Nexus=%d:%d Tag=%02x/%02x\n", 1533 dev->target, dev->lun, msgaddr[0], msgaddr[1]); 1534 break; 1535 1536 case MSG_DISCONNECT: 1537 SBIC_DEBUG(MSGS, ("msgin: DISCONNECT")); 1538 /* 1539 * Mark the fact that all bytes have moved. The 1540 * target may not bother to do a SAVE POINTERS 1541 * at this stage. This flag will set the residual 1542 * count to zero on MSG COMPLETE. 1543 */ 1544 if (dev->sc_dleft == 0) 1545 acb->flags |= ACB_COMPLETE; 1546 1547 if (acb->xs->xs_control & XS_CTL_POLL) 1548 /* Don't allow disconnect in immediate mode */ 1549 goto reject; 1550 else { /* Allow disconnect */ 1551 dev->sc_flags &= ~SBICF_SELECTED; 1552 dev->sc_state = SBIC_DISCONNECT; 1553 } 1554 if ((acb->xs->xs_periph->periph_quirks & 1555 PQUIRK_AUTOSAVE) == 0) 1556 break; 1557 /*FALLTHROUGH*/ 1558 1559 case MSG_SAVEDATAPOINTER: 1560 SBIC_DEBUG(MSGS, ("msgin: SAVEDATAPTR")); 1561 acb->daddr = dev->sc_daddr; 1562 acb->dleft = dev->sc_dleft; 1563 break; 1564 1565 case MSG_RESTOREPOINTERS: 1566 SBIC_DEBUG(MSGS, ("msgin: RESTOREPTR")); 1567 dev->sc_daddr = acb->daddr; 1568 dev->sc_dleft = acb->dleft; 1569 break; 1570 1571 case MSG_CMDCOMPLETE: 1572 /* 1573 * !! KLUDGE ALERT !! quite a few drives don't seem to 1574 * really like the current way of sending the 1575 * sync-handshake together with the ident-message, and 1576 * they react by sending command-complete and 1577 * disconnecting right after returning the valid sync 1578 * handshake. So, all I can do is reselect the drive, 1579 * and hope it won't disconnect again. I don't think 1580 * this is valid behavior, but I can't help fixing a 1581 * problem that apparently exists. 1582 * 1583 * Note: we should not get here on `normal' command 1584 * completion, as that condition is handled by the 1585 * high-level sel&xfer resume command used to walk 1586 * thru status/cc-phase. 1587 */ 1588 SBIC_DEBUG(MSGS, ("msgin: CMD_COMPLETE")); 1589 SBIC_DEBUG(SYNC, ("GOT MSG %d! target %d" 1590 " acting weird.." 1591 " waiting for disconnect...\n", 1592 msgaddr[0], dev->target)); 1593 1594 /* Check to see if wd33c93 is handling this */ 1595 GET_SBIC_asr(dev, asr); 1596 if (asr & SBIC_ASR_BSY) 1597 break; 1598 1599 /* XXX: Assume it works and set status to 00 */ 1600 dev->sc_status = 0; 1601 dev->sc_state = SBIC_CMDCOMPLETE; 1602 break; 1603 1604 case MSG_EXTENDED: 1605 switch(msgaddr[2]) { 1606 case MSG_EXT_SDTR: /* Sync negotiation */ 1607 SBIC_DEBUG(MSGS, ("msgin: EXT_SDTR; " 1608 "period %d, offset %d", 1609 msgaddr[3], msgaddr[4])); 1610 if (msgaddr[1] != 3) 1611 goto reject; 1612 1613 ti->period = 1614 MAX(msgaddr[3], dev->sc_syncperiods[0]); 1615 ti->offset = MIN(msgaddr[4], dev->sc_maxoffset); 1616 if (!(ti->flags & T_WANTSYNC)) 1617 ti->period = ti->offset = 0; 1618 1619 ti->flags &= ~T_NEGOTIATE; 1620 1621 if (ti->offset == 0) 1622 ti->flags &= ~T_SYNCMODE; /* Async */ 1623 else 1624 ti->flags |= T_SYNCMODE; /* Sync */ 1625 1626 if ((dev->sc_flags&SBICF_SYNCNEGO) == 0) 1627 /* target initiated negotiation */ 1628 wd33c93_sched_msgout(dev, SEND_SDTR); 1629 dev->sc_flags &= ~SBICF_SYNCNEGO; 1630 1631 SBIC_DEBUG(SYNC, ("msgin(%d): SDTR(o=%d,p=%d)", 1632 dev->target, ti->offset, 1633 ti->period)); 1634 wd33c93_update_xfer_mode(dev, 1635 acb->xs->xs_periph->periph_target); 1636 wd33c93_setsync(dev, ti); 1637 break; 1638 1639 case MSG_EXT_WDTR: 1640 SBIC_DEBUG(MSGS, ("msgin: EXT_WDTR rejected")); 1641 goto reject; 1642 1643 default: 1644 scsipi_printaddr(acb->xs->xs_periph); 1645 printf("unrecognized MESSAGE EXTENDED;" 1646 " sending REJECT\n"); 1647 goto reject; 1648 } 1649 break; 1650 1651 default: 1652 scsipi_printaddr(acb->xs->xs_periph); 1653 printf("unrecognized MESSAGE; sending REJECT\n"); 1654 1655 reject: 1656 /* We don't support whatever this message is... */ 1657 wd33c93_sched_msgout(dev, SEND_REJECT); 1658 break; 1659 } 1660 break; 1661 1662 case SBIC_IDENTIFIED: 1663 /* 1664 * IDENTIFY message was received and queue tag is expected now 1665 */ 1666 if ((msgaddr[0]!=MSG_SIMPLE_Q_TAG) || (dev->sc_msgify==0)) { 1667 printf("%s: TAG reselect without IDENTIFY;" 1668 " MSG %x; sending DEVICE RESET\n", 1669 dev->sc_dev.dv_xname, msgaddr[0]); 1670 goto reset; 1671 } 1672 SBIC_DEBUG(TAGS, ("TAG %x/%x\n", msgaddr[0], msgaddr[1])); 1673 if (dev->sc_nexus) 1674 printf("*TAG Recv with active nexus!!\n"); 1675 wd33c93_reselect(dev, dev->target, dev->lun, 1676 msgaddr[0], msgaddr[1]); 1677 break; 1678 1679 case SBIC_RESELECTED: 1680 /* 1681 * IDENTIFY message with target 1682 */ 1683 if (MSG_ISIDENTIFY(msgaddr[0])) { 1684 SBIC_DEBUG(PHASE, ("IFFY[%x] ", msgaddr[0])); 1685 dev->sc_msgify = msgaddr[0]; 1686 } else { 1687 printf("%s: reselect without IDENTIFY;" 1688 " MSG %x;" 1689 " sending DEVICE RESET\n", 1690 dev->sc_dev.dv_xname, msgaddr[0]); 1691 goto reset; 1692 } 1693 break; 1694 1695 default: 1696 printf("Unexpected MESSAGE IN. State=%d - Sending RESET\n", 1697 dev->sc_state); 1698 reset: 1699 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 1700 break; 1701 abort: 1702 wd33c93_sched_msgout(dev, SEND_ABORT); 1703 break; 1704 } 1705 } 1706 1707 void 1708 wd33c93_sched_msgout(struct wd33c93_softc *dev, u_short msg) 1709 { 1710 u_char asr; 1711 1712 SBIC_DEBUG(SYNC,("sched_msgout: %04x\n", msg)); 1713 dev->sc_msgpriq |= msg; 1714 1715 /* Schedule MSGOUT Phase to send message */ 1716 1717 WAIT_CIP(dev); 1718 SET_SBIC_cmd(dev, SBIC_CMD_SET_ATN); 1719 WAIT_CIP(dev); 1720 GET_SBIC_asr(dev, asr); 1721 if (asr & SBIC_ASR_LCI) { 1722 printf("MSGOUT Failed!\n"); 1723 } 1724 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1725 WAIT_CIP(dev); 1726 } 1727 1728 /* 1729 * Send the highest priority, scheduled message 1730 */ 1731 void 1732 wd33c93_msgout(struct wd33c93_softc *dev) 1733 { 1734 struct wd33c93_tinfo *ti; 1735 struct wd33c93_acb *acb = dev->sc_nexus; 1736 1737 if (acb == NULL) 1738 panic("MSGOUT with no nexus"); 1739 1740 if (dev->sc_omsglen == 0) { 1741 /* Pick up highest priority message */ 1742 dev->sc_msgout = dev->sc_msgpriq & -dev->sc_msgpriq; 1743 dev->sc_msgoutq |= dev->sc_msgout; 1744 dev->sc_msgpriq &= ~dev->sc_msgout; 1745 dev->sc_omsglen = 1; /* "Default" message len */ 1746 switch (dev->sc_msgout) { 1747 case SEND_SDTR: 1748 ti = &dev->sc_tinfo[acb->xs->xs_periph->periph_target]; 1749 dev->sc_omsg[0] = MSG_EXTENDED; 1750 dev->sc_omsg[1] = MSG_EXT_SDTR_LEN; 1751 dev->sc_omsg[2] = MSG_EXT_SDTR; 1752 if (ti->flags & T_WANTSYNC) { 1753 dev->sc_omsg[3] = ti->period; 1754 dev->sc_omsg[4] = ti->offset; 1755 } else { 1756 dev->sc_omsg[3] = 0; 1757 dev->sc_omsg[4] = 0; 1758 } 1759 dev->sc_omsglen = 5; 1760 if ((dev->sc_flags & SBICF_SYNCNEGO) == 0) { 1761 if (ti->flags & T_WANTSYNC) 1762 ti->flags |= T_SYNCMODE; 1763 else 1764 ti->flags &= ~T_SYNCMODE; 1765 wd33c93_setsync(dev, ti); 1766 } 1767 break; 1768 case SEND_IDENTIFY: 1769 if (dev->sc_state != SBIC_CONNECTED) { 1770 printf("%s at line %d: no nexus\n", 1771 dev->sc_dev.dv_xname, __LINE__); 1772 } 1773 dev->sc_omsg[0] = 1774 MSG_IDENTIFY(acb->xs->xs_periph->periph_lun, 0); 1775 break; 1776 case SEND_TAG: 1777 if (dev->sc_state != SBIC_CONNECTED) { 1778 printf("%s at line %d: no nexus\n", 1779 dev->sc_dev.dv_xname, __LINE__); 1780 } 1781 dev->sc_omsg[0] = acb->tag_type; 1782 dev->sc_omsg[1] = acb->tag_id; 1783 dev->sc_omsglen = 2; 1784 break; 1785 case SEND_DEV_RESET: 1786 dev->sc_omsg[0] = MSG_BUS_DEV_RESET; 1787 ti = &dev->sc_tinfo[dev->target]; 1788 ti->flags &= ~T_SYNCMODE; 1789 wd33c93_update_xfer_mode(dev, dev->target); 1790 if ((ti->flags & T_NOSYNC) == 0) 1791 /* We can re-start sync negotiation */ 1792 ti->flags |= T_NEGOTIATE; 1793 break; 1794 case SEND_PARITY_ERROR: 1795 dev->sc_omsg[0] = MSG_PARITY_ERROR; 1796 break; 1797 case SEND_ABORT: 1798 dev->sc_flags |= SBICF_ABORTING; 1799 dev->sc_omsg[0] = MSG_ABORT; 1800 break; 1801 case SEND_INIT_DET_ERR: 1802 dev->sc_omsg[0] = MSG_INITIATOR_DET_ERR; 1803 break; 1804 case SEND_REJECT: 1805 dev->sc_omsg[0] = MSG_MESSAGE_REJECT; 1806 break; 1807 default: 1808 /* Wasn't expecting MSGOUT Phase */ 1809 dev->sc_omsg[0] = MSG_NOOP; 1810 break; 1811 } 1812 } 1813 1814 wd33c93_xfout(dev, dev->sc_omsglen, dev->sc_omsg); 1815 } 1816 1817 1818 /* 1819 * wd33c93_nextstate() 1820 * return: 1821 * SBIC_STATE_DONE == done 1822 * SBIC_STATE_RUNNING == working 1823 * SBIC_STATE_DISCONNECT == disconnected 1824 * SBIC_STATE_ERROR == error 1825 */ 1826 int 1827 wd33c93_nextstate(struct wd33c93_softc *dev, struct wd33c93_acb *acb, u_char csr, u_char asr) 1828 { 1829 SBIC_DEBUG(PHASE, ("next[a=%02x,c=%02x]: ",asr,csr)); 1830 1831 switch (csr) { 1832 1833 case SBIC_CSR_XFERRED | CMD_PHASE: 1834 case SBIC_CSR_MIS | CMD_PHASE: 1835 case SBIC_CSR_MIS_1 | CMD_PHASE: 1836 case SBIC_CSR_MIS_2 | CMD_PHASE: 1837 1838 if (wd33c93_xfout(dev, acb->clen, &acb->cmd)) 1839 goto abort; 1840 break; 1841 1842 case SBIC_CSR_XFERRED | STATUS_PHASE: 1843 case SBIC_CSR_MIS | STATUS_PHASE: 1844 case SBIC_CSR_MIS_1 | STATUS_PHASE: 1845 case SBIC_CSR_MIS_2 | STATUS_PHASE: 1846 1847 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 1848 1849 /* 1850 * this should be the normal i/o completion case. 1851 * get the status & cmd complete msg then let the 1852 * device driver look at what happened. 1853 */ 1854 wd33c93_xferdone(dev); 1855 1856 wd33c93_dma_stop(dev); 1857 1858 /* Fixup byte count to be passed to higher layer */ 1859 acb->dleft = (acb->flags & ACB_COMPLETE) ? 0 : 1860 dev->sc_dleft; 1861 1862 /* 1863 * Indicate to the upper layers that the command is done 1864 */ 1865 wd33c93_scsidone(dev, acb, dev->sc_status); 1866 1867 return SBIC_STATE_DONE; 1868 1869 1870 case SBIC_CSR_XFERRED | DATA_IN_PHASE: 1871 case SBIC_CSR_MIS | DATA_IN_PHASE: 1872 case SBIC_CSR_MIS_1 | DATA_IN_PHASE: 1873 case SBIC_CSR_MIS_2 | DATA_IN_PHASE: 1874 case SBIC_CSR_XFERRED | DATA_OUT_PHASE: 1875 case SBIC_CSR_MIS | DATA_OUT_PHASE: 1876 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE: 1877 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE: 1878 /* 1879 * Verify that we expected to transfer data... 1880 */ 1881 if (acb->dleft <= 0) { 1882 printf("next: DATA phase with xfer count == %zd, asr:0x%02x csr:0x%02x\n", 1883 acb->dleft, asr, csr); 1884 goto abort; 1885 } 1886 1887 /* 1888 * Should we transfer using PIO or DMA ? 1889 */ 1890 if (acb->xs->xs_control & XS_CTL_POLL || 1891 dev->sc_flags & SBICF_NODMA) { 1892 /* Perfrom transfer using PIO */ 1893 int resid; 1894 1895 SBIC_DEBUG(DMA, ("PIO xfer: %d(%p:%zx)\n", dev->target, 1896 dev->sc_daddr, dev->sc_dleft)); 1897 1898 if (SBIC_PHASE(csr) == DATA_IN_PHASE) 1899 /* data in */ 1900 resid = wd33c93_xfin(dev, dev->sc_dleft, 1901 dev->sc_daddr); 1902 else /* data out */ 1903 resid = wd33c93_xfout(dev, dev->sc_dleft, 1904 dev->sc_daddr); 1905 1906 dev->sc_daddr += (acb->dleft - resid); 1907 dev->sc_dleft = resid; 1908 } else { 1909 int datain = SBIC_PHASE(csr) == DATA_IN_PHASE; 1910 1911 /* Perform transfer using DMA */ 1912 wd33c93_dma_setup(dev, datain); 1913 1914 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI | 1915 dev->sc_dmamode); 1916 1917 SBIC_DEBUG(DMA, ("DMA xfer: %d(%p:%zx)\n", dev->target, 1918 dev->sc_daddr, dev->sc_dleft)); 1919 1920 /* Setup byte count for transfer */ 1921 SBIC_TC_PUT(dev, (unsigned)dev->sc_dleft); 1922 1923 /* Start the transfer */ 1924 SET_SBIC_cmd(dev, SBIC_CMD_XFER_INFO); 1925 1926 /* Start the DMA chip going */ 1927 dev->sc_tcnt = dev->sc_dmago(dev); 1928 1929 /* Indicate that we're in DMA mode */ 1930 dev->sc_flags |= SBICF_INDMA; 1931 } 1932 break; 1933 1934 case SBIC_CSR_XFERRED | MESG_IN_PHASE: 1935 case SBIC_CSR_MIS | MESG_IN_PHASE: 1936 case SBIC_CSR_MIS_1 | MESG_IN_PHASE: 1937 case SBIC_CSR_MIS_2 | MESG_IN_PHASE: 1938 1939 wd33c93_dma_stop(dev); 1940 1941 /* Handle a single message in... */ 1942 return wd33c93_msgin_phase(dev, 0); 1943 1944 case SBIC_CSR_MSGIN_W_ACK: 1945 1946 /* 1947 * We should never see this since it's handled in 1948 * 'wd33c93_msgin_phase()' but just for the sake of paranoia... 1949 */ 1950 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 1951 1952 printf("Acking unknown msgin CSR:%02x",csr); 1953 break; 1954 1955 case SBIC_CSR_XFERRED | MESG_OUT_PHASE: 1956 case SBIC_CSR_MIS | MESG_OUT_PHASE: 1957 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE: 1958 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE: 1959 1960 /* 1961 * Message out phase. ATN signal has been asserted 1962 */ 1963 wd33c93_dma_stop(dev); 1964 wd33c93_msgout(dev); 1965 return SBIC_STATE_RUNNING; 1966 1967 case SBIC_CSR_DISC: 1968 case SBIC_CSR_DISC_1: 1969 SBIC_DEBUG(RSEL, ("wd33c93next target %d disconnected\n", 1970 dev->target)); 1971 wd33c93_dma_stop(dev); 1972 1973 dev->sc_nexus = NULL; 1974 dev->sc_state = SBIC_IDLE; 1975 dev->sc_flags = 0; 1976 1977 ++dev->sc_tinfo[dev->target].dconns; 1978 ++dev->sc_disc; 1979 1980 if (acb->xs->xs_control & XS_CTL_POLL || wd33c93_nodisc) 1981 return SBIC_STATE_DISCONNECT; 1982 1983 /* Try to schedule another target */ 1984 wd33c93_sched(dev); 1985 1986 return SBIC_STATE_DISCONNECT; 1987 1988 case SBIC_CSR_RSLT_NI: 1989 case SBIC_CSR_RSLT_IFY: 1990 { 1991 /* 1992 * A reselection. 1993 * Note that since we don't enable Advanced Features (assuming 1994 * the WD chip is at least the 'A' revision), we're only ever 1995 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the 1996 * hell of it, we'll handle it anyway, for all the extra code 1997 * it needs... 1998 */ 1999 u_char newtarget, newlun; 2000 2001 if (dev->sc_flags & SBICF_INDMA) { 2002 printf("**** RESELECT WHILE DMA ACTIVE!!! ***\n"); 2003 wd33c93_dma_stop(dev); 2004 } 2005 2006 dev->sc_state = SBIC_RESELECTED; 2007 GET_SBIC_rselid(dev, newtarget); 2008 2009 /* check SBIC_RID_SIV? */ 2010 newtarget &= SBIC_RID_MASK; 2011 2012 if (csr == SBIC_CSR_RSLT_IFY) { 2013 /* Read Identify msg to avoid lockup */ 2014 GET_SBIC_data(dev, newlun); 2015 WAIT_CIP(dev); 2016 newlun &= SBIC_TLUN_MASK; 2017 dev->sc_msgify = MSG_IDENTIFY(newlun, 0); 2018 } else { 2019 /* 2020 * Need to read Identify message the hard way, assuming 2021 * the target even sends us one... 2022 */ 2023 for (newlun = 255; newlun; --newlun) { 2024 GET_SBIC_asr(dev, asr); 2025 if (asr & SBIC_ASR_INT) 2026 break; 2027 DELAY(10); 2028 } 2029 2030 /* If we didn't get an interrupt, somethink's up */ 2031 if ((asr & SBIC_ASR_INT) == 0) { 2032 printf("%s: Reselect without identify? asr %x\n", 2033 dev->sc_dev.dv_xname, asr); 2034 newlun = 0; /* XXXX */ 2035 } else { 2036 /* 2037 * We got an interrupt, verify that it's a 2038 * change to message in phase, and if so 2039 * read the message. 2040 */ 2041 GET_SBIC_csr(dev,csr); 2042 2043 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) || 2044 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) || 2045 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) { 2046 /* 2047 * Yup, gone to message in. 2048 * Fetch the target LUN 2049 */ 2050 dev->sc_msgify = 0; 2051 wd33c93_msgin_phase(dev, 1); 2052 newlun = dev->sc_msgify & SBIC_TLUN_MASK; 2053 } else { 2054 /* 2055 * Whoops! Target didn't go to msg_in 2056 * phase!! 2057 */ 2058 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr); 2059 newlun = 0; /* XXXSCW */ 2060 } 2061 } 2062 } 2063 2064 /* Ok, we have the identity of the reselecting target. */ 2065 SBIC_DEBUG(RSEL, ("wd33c93next: reselect from targ %d lun %d", 2066 newtarget, newlun)); 2067 wd33c93_reselect(dev, newtarget, newlun, 0, 0); 2068 dev->sc_disc--; 2069 2070 if (csr == SBIC_CSR_RSLT_IFY) 2071 SET_SBIC_cmd(dev, SBIC_CMD_CLR_ACK); 2072 break; 2073 } 2074 2075 default: 2076 abort: 2077 /* Something unexpected happend -- deal with it. */ 2078 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr); 2079 2080 #ifdef DDB 2081 Debugger(); 2082 #endif 2083 2084 SET_SBIC_control(dev, SBIC_CTL_EDI | SBIC_CTL_IDI); 2085 if (acb->xs) 2086 wd33c93_error(dev, acb); 2087 wd33c93_abort(dev, acb, "next"); 2088 2089 if (dev->sc_flags & SBICF_INDMA) { 2090 wd33c93_dma_stop(dev); 2091 wd33c93_scsidone(dev, acb, STATUS_UNKNOWN); 2092 } 2093 return SBIC_STATE_ERROR; 2094 } 2095 return SBIC_STATE_RUNNING; 2096 } 2097 2098 2099 void 2100 wd33c93_reselect(struct wd33c93_softc *dev, int target, int lun, int tag_type, int tag_id) 2101 { 2102 2103 struct wd33c93_tinfo *ti; 2104 struct wd33c93_linfo *li; 2105 struct wd33c93_acb *acb; 2106 2107 if (dev->sc_nexus) { 2108 /* 2109 * Whoops! We've been reselected with a 2110 * command in progress! 2111 * The best we can do is to put the current 2112 * command back on the ready list and hope 2113 * for the best. 2114 */ 2115 SBIC_DEBUG(RSEL, ("%s: reselect with active command\n", 2116 dev->sc_dev.dv_xname)); 2117 ti = &dev->sc_tinfo[dev->target]; 2118 li = TINFO_LUN(ti, dev->lun); 2119 li->state = L_STATE_IDLE; 2120 2121 wd33c93_dequeue(dev, dev->sc_nexus); 2122 TAILQ_INSERT_HEAD(&dev->ready_list, dev->sc_nexus, chain); 2123 dev->sc_nexus->flags |= ACB_READY; 2124 2125 dev->sc_nexus = NULL; 2126 } 2127 2128 /* Setup state for new nexus */ 2129 acb = NULL; 2130 dev->sc_flags = SBICF_SELECTED; 2131 dev->sc_msgpriq = dev->sc_msgout = dev->sc_msgoutq = 0; 2132 2133 ti = &dev->sc_tinfo[target]; 2134 li = TINFO_LUN(ti, lun); 2135 2136 if (li != NULL) { 2137 if (li->untagged != NULL && li->state) 2138 acb = li->untagged; 2139 else if (tag_type != MSG_SIMPLE_Q_TAG) { 2140 /* Wait for tag to come by during MESG_IN Phase */ 2141 dev->target = target; /* setup I_T_L nexus */ 2142 dev->lun = lun; 2143 dev->sc_state = SBIC_IDENTIFIED; 2144 return; 2145 } else if (tag_type) 2146 acb = li->queued[tag_id]; 2147 } 2148 2149 if (acb == NULL) { 2150 printf("%s: reselect from target %d lun %d tag %x:%x " 2151 "with no nexus; sending ABORT\n", 2152 dev->sc_dev.dv_xname, target, lun, tag_type, tag_id); 2153 goto abort; 2154 } 2155 2156 dev->target = target; 2157 dev->lun = lun; 2158 dev->sc_nexus = acb; 2159 dev->sc_state = SBIC_CONNECTED; 2160 2161 if (!wd33c93_dmaok(dev, acb->xs)) 2162 dev->sc_flags |= SBICF_NODMA; 2163 2164 /* Do an implicit RESTORE POINTERS. */ 2165 dev->sc_daddr = acb->daddr; 2166 dev->sc_dleft = acb->dleft; 2167 2168 /* Set sync modes for new target */ 2169 wd33c93_setsync(dev, ti); 2170 2171 if (acb->flags & ACB_RESET) 2172 wd33c93_sched_msgout(dev, SEND_DEV_RESET); 2173 else if (acb->flags & ACB_ABORT) 2174 wd33c93_sched_msgout(dev, SEND_ABORT); 2175 return; 2176 2177 abort: 2178 wd33c93_sched_msgout(dev, SEND_ABORT); 2179 return; 2180 2181 } 2182 2183 void 2184 wd33c93_update_xfer_mode(struct wd33c93_softc *sc, int target) 2185 { 2186 struct wd33c93_tinfo *ti = &sc->sc_tinfo[target]; 2187 struct scsipi_xfer_mode xm; 2188 2189 xm.xm_target = target; 2190 xm.xm_mode = 0; 2191 xm.xm_period = 0; 2192 xm.xm_offset = 0; 2193 2194 if (ti->flags & T_SYNCMODE) { 2195 xm.xm_mode |= PERIPH_CAP_SYNC; 2196 xm.xm_period = ti->period; 2197 xm.xm_offset = ti->offset; 2198 } 2199 2200 if ((ti->flags & (T_NODISC|T_TAG)) == T_TAG) 2201 xm.xm_mode |= PERIPH_CAP_TQING; 2202 2203 SBIC_DEBUG(SYNC, ("wd33c93_update_xfer_mode: reporting target %d %s\n", 2204 xm.xm_target, 2205 (xm.xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async")); 2206 2207 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 2208 } 2209 2210 2211 /* 2212 * Calculate SCSI Tranfser Period Factor (4ns units each) from the 2213 * WD33c93 divisor value 2214 * 2215 * cycle = DIV / (2 * CLK) 2216 * DIV = FS + 2 2217 * best we can do is 200ns at 20 MHz, 2 cycles 2218 */ 2219 int 2220 wd33c93_div2stp(struct wd33c93_softc *dev, int div) 2221 { 2222 2223 if (div < 2) 2224 div = 8; /* map to Cycles */ 2225 return dev->sc_syncperiods[div - 2]; 2226 } 2227 2228 /* 2229 * Convert SCSI Transfer Period Factor (in 4ns units) to the divisor 2230 * value used by the WD33c93 controller. 2231 */ 2232 int 2233 wd33c93_stp2div(struct wd33c93_softc *dev, int stp) 2234 { 2235 unsigned i; 2236 2237 for (i = 0; i < 7; i++) 2238 if (dev->sc_syncperiods[i] >= stp) 2239 return (i == 6 ? 0 : i + 2); 2240 return 0; /* XXX we can't slow down far enough */ 2241 } 2242 2243 void 2244 wd33c93_timeout(void *arg) 2245 { 2246 struct wd33c93_acb *acb = arg; 2247 struct scsipi_xfer *xs = acb->xs; 2248 struct scsipi_periph *periph = xs->xs_periph; 2249 struct wd33c93_softc *dev = 2250 (void *)periph->periph_channel->chan_adapter->adapt_dev; 2251 int s, asr; 2252 2253 s = splbio(); 2254 2255 GET_SBIC_asr(dev, asr); 2256 2257 scsipi_printaddr(periph); 2258 printf("%s: timed out; asr=0x%02x [acb %p (flags 0x%x, dleft %zx)], " 2259 "<state %d, nexus %p, resid %lx, msg(q %x,o %x)>", 2260 dev->sc_dev.dv_xname, asr, acb, acb->flags, acb->dleft, 2261 dev->sc_state, dev->sc_nexus, (long)dev->sc_dleft, 2262 dev->sc_msgpriq, dev->sc_msgout); 2263 2264 if (asr & SBIC_ASR_INT) { 2265 /* We need to service a missed IRQ */ 2266 wd33c93_intr(dev); 2267 } else { 2268 (void) wd33c93_abort(dev, dev->sc_nexus, "timeout"); 2269 } 2270 splx(s); 2271 } 2272 2273 2274 void 2275 wd33c93_watchdog(void *arg) 2276 { 2277 struct wd33c93_softc *dev = arg; 2278 struct wd33c93_tinfo *ti; 2279 struct wd33c93_linfo *li; 2280 int t, s, l; 2281 /* scrub LUN's that have not been used in the last 10min. */ 2282 time_t old = time_second - (10 * 60); 2283 2284 for (t = 0; t < SBIC_NTARG; t++) { 2285 ti = &dev->sc_tinfo[t]; 2286 for (l = 0; l < SBIC_NLUN; l++) { 2287 s = splbio(); 2288 li = TINFO_LUN(ti, l); 2289 if (li && li->last_used < old && 2290 li->untagged == NULL && li->used == 0) { 2291 ti->lun[li->lun] = NULL; 2292 free(li, M_DEVBUF); 2293 } 2294 splx(s); 2295 } 2296 } 2297 callout_reset(&dev->sc_watchdog, 60 * hz, wd33c93_watchdog, dev); 2298 } 2299 2300 2301 #ifdef DEBUG 2302 void 2303 wd33c93_hexdump(u_char *buf, int len) 2304 { 2305 printf("{%d}:", len); 2306 while (len--) 2307 printf(" %02x", *buf++); 2308 printf("\n"); 2309 } 2310 2311 2312 void 2313 wd33c93_print_csr(u_char csr) 2314 { 2315 switch (SCSI_PHASE(csr)) { 2316 case CMD_PHASE: 2317 printf("CMD_PHASE\n"); 2318 break; 2319 2320 case STATUS_PHASE: 2321 printf("STATUS_PHASE\n"); 2322 break; 2323 2324 case DATA_IN_PHASE: 2325 printf("DATAIN_PHASE\n"); 2326 break; 2327 2328 case DATA_OUT_PHASE: 2329 printf("DATAOUT_PHASE\n"); 2330 break; 2331 2332 case MESG_IN_PHASE: 2333 printf("MESG_IN_PHASE\n"); 2334 break; 2335 2336 case MESG_OUT_PHASE: 2337 printf("MESG_OUT_PHASE\n"); 2338 break; 2339 2340 default: 2341 switch (csr) { 2342 case SBIC_CSR_DISC_1: 2343 printf("DISC_1\n"); 2344 break; 2345 2346 case SBIC_CSR_RSLT_NI: 2347 printf("RESELECT_NO_IFY\n"); 2348 break; 2349 2350 case SBIC_CSR_RSLT_IFY: 2351 printf("RESELECT_IFY\n"); 2352 break; 2353 2354 case SBIC_CSR_SLT: 2355 printf("SELECT\n"); 2356 break; 2357 2358 case SBIC_CSR_SLT_ATN: 2359 printf("SELECT, ATN\n"); 2360 break; 2361 2362 case SBIC_CSR_UNK_GROUP: 2363 printf("UNK_GROUP\n"); 2364 break; 2365 2366 default: 2367 printf("UNKNOWN csr=%02x\n", csr); 2368 } 2369 } 2370 } 2371 #endif
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