Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/wd33c93reg.h
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1 /* $FreeBSD$ */ 2 /* $NecBSD: wd33c93reg.h,v 1.21.24.1 2001/06/13 05:52:05 honda Exp $ */ 3 /* $NetBSD$ */ 4 /* 5 * [NetBSD for NEC PC-98 series] 6 * Copyright (c) 1996, 1997, 1998 7 * NetBSD/pc98 porting staff. All rights reserved. 8 * Copyright (c) 1996, 1997, 1998 9 * Naofumi Honda. All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 25 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 26 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 27 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 30 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 31 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 32 * POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _WD33C93REG_H_ 36 #define _WD33C93REG_H_ 37 38 /* wd33c93 register */ 39 #define wd3s_oid 0x00 40 #define IDR_FS_16_20 0x80 41 #define IDR_FS_12_15 0x40 42 #define IDR_FS_8_10 0x00 43 #define IDR_RAF 0x20 44 #define IDR_EHP 0x10 45 #define IDR_EAF 0x08 46 #define IDR_IDM 0x07 47 48 #define wd3s_ctrl 0x01 49 #define CR_DMA 0x80 50 #define CR_DMAD 0x40 51 #define CR_HLT_HOST_PARITY 0x10 52 #define CR_DIS_INT 0x08 53 #define CR_IDIS_INT 0x04 54 #define CR_HLT_ATN 0x02 55 #define CR_HLT_BUS_PARITY 0x01 56 #define CR_DEFAULT (CR_DIS_INT | CR_IDIS_INT) 57 #define CR_DEFAULT_HP (CR_DEFAULT | CR_HLT_BUS_PARITY) 58 59 #define wd3s_tout 0x02 60 #define wd3s_cdb 0x03 61 #define wd3s_lun 0x0f 62 #define wd3s_cph 0x10 63 #define wd3s_synch 0x11 64 #define wd3s_cnt 0x12 65 #define wd3s_did 0x15 66 #define DIDR_SCC 0x80 67 #define DIDR_DPD 0x40 68 69 #define wd3s_sid 0x16 70 #define SIDR_RESEL 0x80 71 #define SIDR_SEL 0x40 72 #define SIDR_VALID 0x08 73 #define SIDR_IDM 0x07 74 75 #define wd3s_stat 0x17 76 77 #define BSR_CM 0xf0 78 #define BSR_CMDCPL 0x10 79 #define BSR_CMDABT 0x20 80 #define BSR_CMDERR 0x40 81 #define BSR_CMDREQ 0x80 82 83 #define BSR_SM 0x0f 84 #define BSR_PM 0x07 85 #define BSR_PHVALID 0x08 86 #define BSR_IOR 0x01 87 #define BSR_DATAOUT 0x00 88 #define BSR_DATAIN 0x01 89 #define BSR_CMDOUT 0x02 90 #define BSR_STATIN 0x03 91 #define BSR_UNSPINFO0 0x04 92 #define BSR_UNSPINFO1 0x05 93 #define BSR_MSGOUT 0x06 94 #define BSR_MSGIN 0x07 95 96 #define BSR_RESET 0x00 97 #define BSR_AFM_RESET 0x01 98 #define BSR_SELECTED 0x11 99 #define BSR_SATFIN 0x16 100 #define BSR_ACKREQ 0x20 101 #define BSR_SATSDP 0x21 102 #define BSR_RESEL 0x80 103 #define BSR_AFM_RESEL 0x81 104 #define BSR_DISC 0x85 105 106 #define wd3s_cmd 0x18 107 #define wd3s_data 0x19 108 #define wd3s_qtag 0x1a 109 110 #define wd3s_mbank 0x30 111 #define MBR_RST 0x02 112 #define MBR_IEN 0x04 113 114 #define wd3s_mwin 0x31 115 #define wd3s_auxc 0x33 116 #define AUXCR_HIDM 0x07 117 #define AUXCR_INTM 0x38 118 #define AUXCR_RRST 0x80 119 120 /* status port */ 121 #define STR_INT 0x80 122 #define STR_LCI 0x40 123 #define STR_BSY 0x20 124 #define STR_CIP 0x10 125 #define STR_PE 0x02 126 #define STR_DBR 0x01 127 #define STR_BUSY 0xf0 128 129 /* cmd port */ 130 #define CMDP_DMES 0x01 131 #define CMDP_DMER 0x02 132 #define CMDP_TCMS 0x04 133 #define CMDP_TCMR 0x08 134 #define CMDP_TCIR 0x10 135 136 /* wd33c93 chip cmds */ 137 #define WD3S_SBT 0x80 138 #define WD3S_RESET 0x00 139 #define WD3S_ABORT 0x01 140 #define WD3S_ASSERT_ATN 0x02 141 #define WD3S_NEGATE_ACK 0x03 142 #define WD3S_DISCONNECT 0x04 143 #define WD3S_RESELECT 0x05 144 #define WD3S_SELECT_ATN 0x06 145 #define WD3S_SELECT_NO_ATN 0x07 146 #define WD3S_SELECT_ATN_TFR 0x08 147 #define WD3S_SELECT_NO_ATN_TFR 0x09 148 #define WD3S_RESELECT_RCV_DATA 0x0a 149 #define WD3S_RESELECT_SEND_DATA 0x0b 150 #define WD3S_WAIT_SELECT_RCV 0x0c 151 #define WD3S_CMD_COMPSEQ 0x0d 152 #define WD3S_SEND_DISC_MSG 0x0e 153 #define WD3S_SET_IDI 0x0f 154 #define WD3S_RCV_CMD 0x10 155 #define WD3S_RCV_DATA 0x11 156 #define WD3S_RCV_MSG_OUT 0x12 157 #define WD3S_RCV_UNSP_INFO_OUT 0x13 158 #define WD3S_SEND_STATUS 0x14 159 #define WD3S_SEND_DATA 0x15 160 #define WD3S_SEND_MSG_IN 0x16 161 #define WD3S_SEND_UNSP_INFO_IN 0x17 162 #define WD3S_TRANSLATE_ADDRESS 0x18 163 #define WD3S_TFR_INFO 0x20 164 165 #endif /* !_WD33C93REG_H_ */
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