The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/wd33c93reg.h

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    1 /*      $NetBSD: wd33c93reg.h,v 1.1 2006/08/26 22:06:37 bjh21 Exp $     */
    2 
    3 /*
    4  * Copyright (c) 1990 The Regents of the University of California.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to Berkeley by
    8  * Van Jacobson of Lawrence Berkeley Laboratory.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. Neither the name of the University nor the names of its contributors
   19  *    may be used to endorse or promote products derived from this software
   20  *    without specific prior written permission.
   21  *
   22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   32  * SUCH DAMAGE.
   33  *
   34  *  @(#)scsireg.h   7.3 (Berkeley) 2/5/91
   35  */
   36 
   37 /*
   38  * Copyright (c) 2001 Wayne Knowles
   39  *
   40  * This code is derived from software contributed to Berkeley by
   41  * Van Jacobson of Lawrence Berkeley Laboratory.
   42  *
   43  * Redistribution and use in source and binary forms, with or without
   44  * modification, are permitted provided that the following conditions
   45  * are met:
   46  * 1. Redistributions of source code must retain the above copyright
   47  *    notice, this list of conditions and the following disclaimer.
   48  * 2. Redistributions in binary form must reproduce the above copyright
   49  *    notice, this list of conditions and the following disclaimer in the
   50  *    documentation and/or other materials provided with the distribution.
   51  * 3. All advertising materials mentioning features or use of this software
   52  *    must display the following acknowledgement:
   53  *  This product includes software developed by the University of
   54  *  California, Berkeley and its contributors.
   55  * 4. Neither the name of the University nor the names of its contributors
   56  *    may be used to endorse or promote products derived from this software
   57  *    without specific prior written permission.
   58  *
   59  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   60  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   61  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   62  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   63  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   64  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   65  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   66  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   67  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   68  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   69  * SUCH DAMAGE.
   70  *
   71  *  @(#)scsireg.h   7.3 (Berkeley) 2/5/91
   72  */
   73 
   74 /*
   75  * WD33C93 SCSI interface hardware description.
   76  *
   77  * Using parts of the Mach scsi driver for the 33C93
   78  */
   79 
   80 #define SBIC_myid       0
   81 #define SBIC_cdbsize    0
   82 #define SBIC_control    1
   83 #define SBIC_timeo      2
   84 #define SBIC_cdb1       3
   85 #define SBIC_tsecs      3
   86 #define SBIC_cdb2       4
   87 #define SBIC_theads     4
   88 #define SBIC_cdb3       5
   89 #define SBIC_tcyl_hi    5
   90 #define SBIC_cdb4       6
   91 #define SBIC_tcyl_lo    6
   92 #define SBIC_cdb5       7
   93 #define SBIC_addr_hi    7
   94 #define SBIC_cdb6       8
   95 #define SBIC_addr_2     8
   96 #define SBIC_cdb7       9
   97 #define SBIC_addr_3     9
   98 #define SBIC_cdb8       10
   99 #define SBIC_addr_lo    10
  100 #define SBIC_cdb9       11
  101 #define SBIC_secno      11
  102 #define SBIC_cdb10      12
  103 #define SBIC_headno     12
  104 #define SBIC_cdb11      13
  105 #define SBIC_cylno_hi   13
  106 #define SBIC_cdb12      14
  107 #define SBIC_cylno_lo   14
  108 #define SBIC_tlun       15
  109 #define SBIC_cmd_phase  16
  110 #define SBIC_syn        17
  111 #define SBIC_count_hi   18
  112 #define SBIC_count_med  19
  113 #define SBIC_count_lo   20
  114 #define SBIC_selid      21
  115 #define SBIC_rselid     22
  116 #define SBIC_csr        23
  117 #define SBIC_cmd        24
  118 #define SBIC_data       25
  119 #define SBIC_queue_tag  26
  120 #define SBIC_aux_status 27
  121 
  122 /* wd33c93_asr is addressed directly */
  123 
  124 /*
  125  *  Register defines
  126  */
  127 
  128 /*
  129  * Auxiliary Status Register
  130  */
  131 
  132 #define SBIC_ASR_INT            0x80    /* Interrupt pending */
  133 #define SBIC_ASR_LCI            0x40    /* Last command ignored */
  134 #define SBIC_ASR_BSY            0x20    /* Busy, only cmd/data/asr readable */
  135 #define SBIC_ASR_CIP            0x10    /* Busy, cmd unavail also */
  136 #define SBIC_ASR_xxx            0x0c
  137 #define SBIC_ASR_PE             0x02    /* Parity error (even) */
  138 #define SBIC_ASR_DBR            0x01    /* Data Buffer Ready */
  139 
  140 /*
  141  * My ID register, and/or CDB Size
  142  */
  143 
  144 #define SBIC_ID_FS_8_10         0x00    /* Input clock is  8-10 MHz */
  145                                         /* 11 MHz is invalid */
  146 #define SBIC_ID_FS_12_15        0x40    /* Input clock is 12-15 MHz */
  147 #define SBIC_ID_FS_16_20        0x80    /* Input clock is 16-20 MHz */
  148 #define SBIC_ID_RAF             0x20    /* */
  149 #define SBIC_ID_EHP             0x10    /* Enable host parity */
  150 #define SBIC_ID_EAF             0x08    /* Enable Advanced Features */
  151 #define SBIC_ID_MASK            0x07
  152 #define SBIC_ID_CBDSIZE_MASK    0x0f    /* if unk SCSI cmd group */
  153 
  154 /*
  155  * Control register
  156  */
  157 
  158 #define SBIC_CTL_DMA            0x80    /* Single byte dma */
  159 #define SBIC_CTL_DBA_DMA        0x40    /* direct buffer acces (bus master)*/
  160 #define SBIC_CTL_BURST_DMA      0x20    /* continuous mode (8237) */
  161 #define SBIC_CTL_NO_DMA         0x00    /* Programmed I/O */
  162 #define SBIC_CTL_HHP            0x10    /* Halt on host parity error */
  163 #define SBIC_CTL_EDI            0x08    /* Ending disconnect interrupt */
  164 #define SBIC_CTL_IDI            0x04    /* Intermediate disconnect interrupt*/
  165 #define SBIC_CTL_HA             0x02    /* Halt on ATN */
  166 #define SBIC_CTL_HSP            0x01    /* Halt on SCSI parity error */
  167 
  168 /*
  169  * Timeout period register
  170  * [val in msecs, input clk in 0.1 MHz]
  171  */
  172 
  173 #define SBIC_TIMEOUT(val,clk)   ((((val) * (clk)) / 800) + 1)
  174 
  175 /*
  176  * CDBn registers, note that
  177  *  cdb11 is used for status byte in target mode (send-status-and-cc)
  178  *  cdb12 sez if linked command complete, and w/flag if so
  179  */
  180 
  181 /*
  182  * Target LUN register
  183  * [holds target status when select-and-xfer]
  184  */
  185 
  186 #define SBIC_TLUN_VALID         0x80    /* did we receive an Identify msg */
  187 #define SBIC_TLUN_DOK           0x40    /* Disconnect OK */
  188 #define SBIC_TLUN_xxx           0x38
  189 #define SBIC_TLUN_MASK          0x07
  190 
  191 /*
  192  * Command Phase register
  193  */
  194 
  195 #define SBIC_CPH_MASK           0x7f    /* values/restarts are cmd specific */
  196 #define SBIC_CPH(p)             ((p) & SBIC_CPH_MASK)
  197 
  198 /*
  199  * FIFO register
  200  */
  201 
  202 #define SBIC_FIFO_DEEP          12
  203 
  204 /*
  205  * maximum possible size in TC registers. Since this is 24 bit, it's easy
  206  */
  207 #define SBIC_TC_MAX             ((1 << 24) - 1)
  208 
  209 /*
  210  * Synchronous xfer register
  211  */
  212 
  213 #define SBIC_SYN_OFF_MASK       0x0f
  214 #define SBIC_SYN_MAX_OFFSET     SBIC_FIFO_DEEP
  215 #define SBIC_SYN_PER_MASK       0x70
  216 #define SBIC_SYN_MIN_PERIOD     2       /* upto 8, encoded as 0 */
  217 
  218 #define SBIC_SYN(o,p) \
  219     (((o) & SBIC_SYN_OFF_MASK) | (((p) << 4) & SBIC_SYN_PER_MASK))
  220 
  221 /*
  222  * Transfer count register
  223  * optimal access macros depend on addressing
  224  */
  225 
  226 /*
  227  * Destination ID (selid) register
  228  */
  229 
  230 #define SBIC_SID_SCC            0x80    /* Select command chaining (tgt) */
  231 #define SBIC_SID_DPD            0x40    /* Data phase direction (inittor) */
  232 #define SBIC_SID_FROM_SCSI      0x40
  233 #define SBIC_SID_TO_SCSI        0x00
  234 #define SBIC_SID_xxx            0x38
  235 #define SBIC_SID_IDMASK         0x07
  236 
  237 /*
  238  * Source ID (rselid) register
  239  */
  240 
  241 #define SBIC_RID_ER             0x80    /* Enable reselection */
  242 #define SBIC_RID_ES             0x40    /* Enable selection */
  243 #define SBIC_RID_DSP            0x20    /* Disable select parity */
  244 #define SBIC_RID_SIV            0x08    /* Source ID valid */
  245 #define SBIC_RID_MASK           0x07
  246 
  247 /*
  248  * Status register
  249  */
  250 
  251 #define SBIC_CSR_CAUSE          0xf0
  252 #define SBIC_CSR_RESET          0x00    /* chip was reset */
  253 #define SBIC_CSR_CMD_DONE       0x10    /* cmd completed */
  254 #define SBIC_CSR_CMD_STOPPED    0x20    /* interrupted or abrted*/
  255 #define SBIC_CSR_CMD_ERR        0x40    /* end with error */
  256 #define SBIC_CSR_BUS_SERVICE    0x80    /* REQ pending on the bus */
  257 
  258 
  259 #define SBIC_CSR_QUALIFIER      0x0f
  260 /* Reset State Interrupts */
  261 #define SBIC_CSR_RESET          0x00    /* reset w/advanced features*/
  262 #define SBIC_CSR_RESET_AM       0x01    /* reset w/advanced features*/
  263 /* Successful Completion Interrupts */
  264 #define SBIC_CSR_TARGET         0x10    /* reselect complete */
  265 #define SBIC_CSR_INITIATOR      0x11    /* select complete */
  266 #define SBIC_CSR_WO_ATN         0x13    /* tgt mode completion */
  267 #define SBIC_CSR_W_ATN          0x14    /* ditto */
  268 #define SBIC_CSR_XLATED         0x15    /* translate address cmd */
  269 #define SBIC_CSR_S_XFERRED      0x16    /* initiator mode completion*/
  270 #define SBIC_CSR_XFERRED        0x18    /* phase in low bits */
  271 /* Paused or Aborted Interrupts */
  272 #define SBIC_CSR_MSGIN_W_ACK    0x20    /* (I) msgin, ACK asserted*/
  273 #define SBIC_CSR_SDP            0x21    /* (I) SDP msg received */
  274 #define SBIC_CSR_SEL_ABRT       0x22    /* sel/resel aborted */
  275 #define SBIC_CSR_XFR_PAUSED     0x23    /* (T) no ATN */
  276 #define SBIC_CSR_XFR_PAUSED_ATN 0x24    /* (T) ATN is asserted */
  277 #define SBIC_CSR_RSLT_AM        0x27    /* (I) lost selection (AM) */
  278 #define SBIC_CSR_MIS            0x28    /* (I) xfer aborted, ph mis */
  279 /* Terminated Interrupts */
  280 #define SBIC_CSR_CMD_INVALID    0x40
  281 #define SBIC_CSR_DISC           0x41    /* (I) tgt disconnected */
  282 #define SBIC_CSR_SEL_TIMEO      0x42
  283 #define SBIC_CSR_PE             0x43    /* parity error */
  284 #define SBIC_CSR_PE_ATN         0x44    /* ditto, ATN is asserted */
  285 #define SBIC_CSR_XLATE_TOOBIG   0x45
  286 #define SBIC_CSR_RSLT_NOAM      0x46    /* (I) lost sel, no AM mode */
  287 #define SBIC_CSR_BAD_STATUS     0x47    /* status byte was nok */
  288 #define SBIC_CSR_MIS_1          0x48    /* ph mis, see low bits */
  289 /* Service Required Interrupts */
  290 #define SBIC_CSR_RSLT_NI        0x80    /* reselected, no ify msg */
  291 #define SBIC_CSR_RSLT_IFY       0x81    /* ditto, AM mode, got ify */
  292 #define SBIC_CSR_SLT            0x82    /* selected, no ATN */
  293 #define SBIC_CSR_SLT_ATN        0x83    /* selected with ATN */
  294 #define SBIC_CSR_ATN            0x84    /* (T) ATN asserted */
  295 #define SBIC_CSR_DISC_1         0x85    /* (I) bus is free */
  296 #define SBIC_CSR_UNK_GROUP      0x87    /* strange CDB1 */
  297 #define SBIC_CSR_MIS_2          0x88    /* (I) ph mis, see low bits */
  298 
  299 #define SBIC_PHASE(csr)         SCSI_PHASE(csr)
  300 
  301 /*
  302  * Command register (command codes)
  303  */
  304 
  305 #define SBIC_CMD_SBT            0x80    /* Single byte xfer qualifier */
  306 #define SBIC_CMD_MASK           0x7f
  307 
  308                     /* Miscellaneous */
  309 #define SBIC_CMD_RESET          0x00    /* (DTI) lev I */
  310 #define SBIC_CMD_ABORT          0x01    /* (DTI) lev I */
  311 #define SBIC_CMD_DISC           0x04    /* ( TI) lev I */
  312 #define SBIC_CMD_SSCC           0x0d    /* ( TI) lev I */
  313 #define SBIC_CMD_SET_IDI        0x0f    /* (DTI) lev I */
  314 #define SBIC_CMD_XLATE          0x18    /* (DT ) lev II */
  315 
  316                     /* Initiator state */
  317 #define SBIC_CMD_SET_ATN        0x02    /* (  I) lev I */
  318 #define SBIC_CMD_CLR_ACK        0x03    /* (  I) lev I */
  319 #define SBIC_CMD_XFER_PAD       0x19    /* (  I) lev II */
  320 #define SBIC_CMD_XFER_INFO      0x20    /* (  I) lev II */
  321 
  322                     /* Target state */
  323 #define SBIC_CMD_SND_DISC       0x0e    /* ( T ) lev II */
  324 #define SBIC_CMD_RCV_CMD        0x10    /* ( T ) lev II */
  325 #define SBIC_CMD_RCV_DATA       0x11    /* ( T ) lev II */
  326 #define SBIC_CMD_RCV_MSG_OUT    0x12    /* ( T ) lev II */
  327 #define SBIC_CMD_RCV            0x13    /* ( T ) lev II */
  328 #define SBIC_CMD_SND_STATUS     0x14    /* ( T ) lev II */
  329 #define SBIC_CMD_SND_DATA       0x15    /* ( T ) lev II */
  330 #define SBIC_CMD_SND_MSG_IN     0x16    /* ( T ) lev II */
  331 #define SBIC_CMD_SND            0x17    /* ( T ) lev II */
  332 
  333                     /* Disconnected state */
  334 #define SBIC_CMD_RESELECT       0x05    /* (D  ) lev II */
  335 #define SBIC_CMD_SEL_ATN        0x06    /* (D  ) lev II */
  336 #define SBIC_CMD_SEL            0x07    /* (D  ) lev II */
  337 #define SBIC_CMD_SEL_ATN_XFER   0x08    /* (D I) lev II */
  338 #define SBIC_CMD_SEL_XFER       0x09    /* (D I) lev II */
  339 #define SBIC_CMD_RESELECT_RECV  0x0a    /* (DT ) lev II */
  340 #define SBIC_CMD_RESELECT_SEND  0x0b    /* (DT ) lev II */
  341 #define SBIC_CMD_WAIT_SEL_RECV  0x0c    /* (DT ) lev II */
  342 
  343 
  344 #define PHASE_MASK              0x07    /* mask for psns/pctl phase */
  345 #define DATA_OUT_PHASE          0x00
  346 #define DATA_IN_PHASE           0x01
  347 #define CMD_PHASE               0x02
  348 #define STATUS_PHASE            0x03
  349 #define BUS_FREE_PHASE          0x04
  350 #define ARB_SEL_PHASE           0x05    /* Fuji chip combines bus arb with sel. */
  351 #define MESG_OUT_PHASE          0x06
  352 #define MESG_IN_PHASE           0x07
  353 
  354 #define SCSI_PHASE(reg)         ((reg) & PHASE_MASK)
  355 
  356 #define SCSI_STATUS_MASK        0x3e    /* Mask unused bits in status byte */
  357 
  358 /* approximate, but we won't do SBT on selects */
  359 #define wd33c93_isa_select(cmd)    (((cmd) > 0x5) && ((cmd) < 0xa))
  360 
  361 #define PAD(n)  char n;
  362 #define SBIC_MACHINE_DMA_MODE   SBIC_CTL_DMA
  363 
  364 typedef struct {
  365         volatile unsigned char  wd33c93_asr;    /* r : Aux Status Register */
  366 #define wd33c93_address         wd33c93_asr     /* w : desired register no */
  367         volatile unsigned char  wd33c93_value; /* rw: register value */
  368 } wd33c93_padded_ind_regmap_t;
  369 typedef volatile wd33c93_padded_ind_regmap_t *wd33c93_regmap_p;
  370 
  371 #define SBIC_ASR                0       /* offset to ASC register */
  372 #define SBIC_ADDR               0       /* offset to address reg */
  373 #define SBIC_VAL                1       /* offset to data register */
  374 
  375 #define wd33c93_read_reg(sc,regno,val)                                  \
  376     do {                                                                \
  377         bus_space_write_1((sc)->sc_regt,(sc)->sc_regh,SBIC_ADDR,(regno)); \
  378         (val) = bus_space_read_1((sc)->sc_regt,(sc)->sc_regh,SBIC_VAL); \
  379     } while (0)
  380 
  381 #define wd33c93_write_reg(sc,regno,val)                                 \
  382     do {                                                                \
  383         bus_space_write_1((sc)->sc_regt, (sc)->sc_regh, SBIC_ADDR, (regno)); \
  384         bus_space_write_1((sc)->sc_regt, (sc)->sc_regh, SBIC_VAL,  (val)); \
  385     } while (0)
  386 
  387 #define SET_SBIC_myid(sc,val)           wd33c93_write_reg(sc,SBIC_myid,val)
  388 #define GET_SBIC_myid(sc,val)           wd33c93_read_reg(sc,SBIC_myid,val)
  389 #define SET_SBIC_cdbsize(sc,val)        wd33c93_write_reg(sc,SBIC_cdbsize,val)
  390 #define GET_SBIC_cdbsize(sc,val)        wd33c93_read_reg(sc,SBIC_cdbsize,val)
  391 #define SET_SBIC_control(sc,val)        wd33c93_write_reg(sc,SBIC_control,val)
  392 #define GET_SBIC_control(sc,val)        wd33c93_read_reg(sc,SBIC_control,val)
  393 #define SET_SBIC_timeo(sc,val)          wd33c93_write_reg(sc,SBIC_timeo,val)
  394 #define GET_SBIC_timeo(sc,val)          wd33c93_read_reg(sc,SBIC_timeo,val)
  395 #define SET_SBIC_cdb1(sc,val)           wd33c93_write_reg(sc,SBIC_cdb1,val)
  396 #define GET_SBIC_cdb1(sc,val)           wd33c93_read_reg(sc,SBIC_cdb1,val)
  397 #define SET_SBIC_cdb2(sc,val)           wd33c93_write_reg(sc,SBIC_cdb2,val)
  398 #define GET_SBIC_cdb2(sc,val)           wd33c93_read_reg(sc,SBIC_cdb2,val)
  399 #define SET_SBIC_cdb3(sc,val)           wd33c93_write_reg(sc,SBIC_cdb3,val)
  400 #define GET_SBIC_cdb3(sc,val)           wd33c93_read_reg(sc,SBIC_cdb3,val)
  401 #define SET_SBIC_cdb4(sc,val)           wd33c93_write_reg(sc,SBIC_cdb4,val)
  402 #define GET_SBIC_cdb4(sc,val)           wd33c93_read_reg(sc,SBIC_cdb4,val)
  403 #define SET_SBIC_cdb5(sc,val)           wd33c93_write_reg(sc,SBIC_cdb5,val)
  404 #define GET_SBIC_cdb5(sc,val)           wd33c93_read_reg(sc,SBIC_cdb5,val)
  405 #define SET_SBIC_cdb6(sc,val)           wd33c93_write_reg(sc,SBIC_cdb6,val)
  406 #define GET_SBIC_cdb6(sc,val)           wd33c93_read_reg(sc,SBIC_cdb6,val)
  407 #define SET_SBIC_cdb7(sc,val)           wd33c93_write_reg(sc,SBIC_cdb7,val)
  408 #define GET_SBIC_cdb7(sc,val)           wd33c93_read_reg(sc,SBIC_cdb7,val)
  409 #define SET_SBIC_cdb8(sc,val)           wd33c93_write_reg(sc,SBIC_cdb8,val)
  410 #define GET_SBIC_cdb8(sc,val)           wd33c93_read_reg(sc,SBIC_cdb8,val)
  411 #define SET_SBIC_cdb9(sc,val)           wd33c93_write_reg(sc,SBIC_cdb9,val)
  412 #define GET_SBIC_cdb9(sc,val)           wd33c93_read_reg(sc,SBIC_cdb9,val)
  413 #define SET_SBIC_cdb10(sc,val)          wd33c93_write_reg(sc,SBIC_cdb10,val)
  414 #define GET_SBIC_cdb10(sc,val)          wd33c93_read_reg(sc,SBIC_cdb10,val)
  415 #define SET_SBIC_cdb11(sc,val)          wd33c93_write_reg(sc,SBIC_cdb11,val)
  416 #define GET_SBIC_cdb11(sc,val)          wd33c93_read_reg(sc,SBIC_cdb11,val)
  417 #define SET_SBIC_cdb12(sc,val)          wd33c93_write_reg(sc,SBIC_cdb12,val)
  418 #define GET_SBIC_cdb12(sc,val)          wd33c93_read_reg(sc,SBIC_cdb12,val)
  419 #define SET_SBIC_tlun(sc,val)           wd33c93_write_reg(sc,SBIC_tlun,val)
  420 #define GET_SBIC_tlun(sc,val)           wd33c93_read_reg(sc,SBIC_tlun,val)
  421 #define SET_SBIC_cmd_phase(sc,val)      wd33c93_write_reg(sc,SBIC_cmd_phase,val)
  422 #define GET_SBIC_cmd_phase(sc,val)      wd33c93_read_reg(sc,SBIC_cmd_phase,val)
  423 #define SET_SBIC_syn(sc,val)            wd33c93_write_reg(sc,SBIC_syn,val)
  424 #define GET_SBIC_syn(sc,val)            wd33c93_read_reg(sc,SBIC_syn,val)
  425 #define SET_SBIC_count_hi(sc,val)       wd33c93_write_reg(sc,SBIC_count_hi,val)
  426 #define GET_SBIC_count_hi(sc,val)       wd33c93_read_reg(sc,SBIC_count_hi,val)
  427 #define SET_SBIC_count_med(sc,val)      wd33c93_write_reg(sc,SBIC_count_med,val)
  428 #define GET_SBIC_count_med(sc,val)      wd33c93_read_reg(sc,SBIC_count_med,val)
  429 #define SET_SBIC_count_lo(sc,val)       wd33c93_write_reg(sc,SBIC_count_lo,val)
  430 #define GET_SBIC_count_lo(sc,val)       wd33c93_read_reg(sc,SBIC_count_lo,val)
  431 #define SET_SBIC_selid(sc,val)          wd33c93_write_reg(sc,SBIC_selid,val)
  432 #define GET_SBIC_selid(sc,val)          wd33c93_read_reg(sc,SBIC_selid,val)
  433 #define SET_SBIC_rselid(sc,val)         wd33c93_write_reg(sc,SBIC_rselid,val)
  434 #define GET_SBIC_rselid(sc,val)         wd33c93_read_reg(sc,SBIC_rselid,val)
  435 #define SET_SBIC_csr(sc,val)            wd33c93_write_reg(sc,SBIC_csr,val)
  436 #define GET_SBIC_csr(sc,val)            wd33c93_read_reg(sc,SBIC_csr,val)
  437 #define SET_SBIC_cmd(sc,val)            wd33c93_write_reg(sc,SBIC_cmd,val)
  438 #define GET_SBIC_cmd(sc,val)            wd33c93_read_reg(sc,SBIC_cmd,val)
  439 #define SET_SBIC_data(sc,val)           wd33c93_write_reg(sc,SBIC_data,val)
  440 #define GET_SBIC_data(sc,val)           wd33c93_read_reg(sc,SBIC_data,val)
  441 #define SET_SBIC_queue_tag(sc,val)      wd33c93_write_reg(sc,SBIC_queue_tag,val)
  442 #define GET_SBIC_queue_tag(sc,val)      wd33c93_read_reg(sc,SBIC_queue_tag,val)
  443 
  444 #define SBIC_TC_PUT(sc,val)                                             \
  445     do {                                                                \
  446         wd33c93_write_reg(sc,SBIC_count_hi,((val)>>16));                \
  447         bus_space_write_1((sc)->sc_regt, (sc)->sc_regh,                 \
  448                           SBIC_VAL, (val)>>8);                          \
  449         bus_space_write_1((sc)->sc_regt, (sc)->sc_regh,                 \
  450                           SBIC_VAL, (val));                             \
  451     } while (0)
  452 
  453 #define SBIC_TC_GET(sc,val)                                             \
  454     do {                                                                \
  455         wd33c93_read_reg(sc,SBIC_count_hi,(val));                       \
  456         (val) = ((val)<<8) | bus_space_read_1((sc)->sc_regt,            \
  457                                 (sc)->sc_regh,SBIC_VAL);                \
  458         (val) = ((val)<<8) | bus_space_read_1((sc)->sc_regt,            \
  459                                 (sc)->sc_regh,SBIC_VAL);                \
  460     } while (0)
  461 
  462 #define SBIC_LOAD_COMMAND(sc,cmd,cmdsize)                               \
  463     do {                                                                \
  464         int   n   = (cmdsize) - 1;                                      \
  465         char *ptr = (char *)(cmd);                                      \
  466         wd33c93_write_reg(regs, SBIC_cdb1, *ptr++);                     \
  467         while(n-- > 0)                                                  \
  468                 bus_space_write_1((sc)->sc_regt, (sc)->sc_regh,         \
  469                           SBIC_VAL, *ptr++); /* XXX write_multi */      \
  470     } while (0)
  471 
  472 #define GET_SBIC_asr(sc,val)                                            \
  473     do {                                                                \
  474         (val) = bus_space_read_1((sc)->sc_regt,(sc)->sc_regh,SBIC_ASR); \
  475     } while (0)
  476 
  477 
  478 #define WAIT_CIP(sc)                                                    \
  479     do {                                                                \
  480         while (bus_space_read_1((sc)->sc_regt,(sc)->sc_regh,            \
  481                         SBIC_ASR) & SBIC_ASR_CIP)                       \
  482                 /*nop*/;                                                \
  483     } while (0)
  484 
  485 /*
  486  * transmit a byte in programmed I/O mode
  487  */
  488 #define SEND_BYTE(sc, ch)                                               \
  489     do {                                                                \
  490         WAIT_CIP(sc);                                                   \
  491         SET_SBIC_cmd(sc, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO);            \
  492         SBIC_WAIT(sc, SBIC_ASR_DBR, 0);                                 \
  493         SET_SBIC_data(sc, ch);                                          \
  494     } while (0)
  495 
  496 /*
  497  * receive a byte in programmed I/O mode
  498  */
  499 #define RECV_BYTE(sc, ch)                                               \
  500     do {                                                                \
  501         WAIT_CIP(sc);                                                   \
  502         SET_SBIC_cmd(sc, SBIC_CMD_SBT | SBIC_CMD_XFER_INFO);            \
  503         SBIC_WAIT(sc, SBIC_ASR_DBR, 0);                                 \
  504         GET_SBIC_data(sc, ch);                                          \
  505     } while (0)

Cache object: 782a01ee2c7c2dfee79aa2b096754861


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