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sys/dev/ic/wdc.c
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1 /* $NetBSD: wdc.c,v 1.172.2.7 2004/09/17 04:04:57 jmc Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 3. All advertising materials mentioning features or use of this software 48 * must display the following acknowledgement: 49 * This product includes software developed by the NetBSD 50 * Foundation, Inc. and its contributors. 51 * 4. Neither the name of The NetBSD Foundation nor the names of its 52 * contributors may be used to endorse or promote products derived 53 * from this software without specific prior written permission. 54 * 55 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 57 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 58 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 59 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 60 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 61 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 62 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 63 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 64 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 65 * POSSIBILITY OF SUCH DAMAGE. 66 */ 67 68 /* 69 * CODE UNTESTED IN THE CURRENT REVISION: 70 */ 71 72 #include <sys/cdefs.h> 73 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.172.2.7 2004/09/17 04:04:57 jmc Exp $"); 74 75 #ifndef WDCDEBUG 76 #define WDCDEBUG 77 #endif /* WDCDEBUG */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/kernel.h> 82 #include <sys/conf.h> 83 #include <sys/buf.h> 84 #include <sys/device.h> 85 #include <sys/malloc.h> 86 #include <sys/pool.h> 87 #include <sys/syslog.h> 88 #include <sys/proc.h> 89 90 #include <machine/intr.h> 91 #include <machine/bus.h> 92 93 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 94 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 95 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 96 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 97 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 98 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 99 100 #include <dev/ata/atavar.h> 101 #include <dev/ata/atareg.h> 102 #include <dev/ic/wdcreg.h> 103 #include <dev/ic/wdcvar.h> 104 105 #include "locators.h" 106 107 #include "ataraid.h" 108 #include "atapibus.h" 109 #include "wd.h" 110 111 #if NATARAID > 0 112 #include <dev/ata/ata_raidvar.h> 113 #endif 114 115 #define WDCDELAY 100 /* 100 microseconds */ 116 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 117 #if 0 118 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 119 #define WDCNDELAY_DEBUG 50 120 #endif 121 122 /* When polling wait that much and then tsleep for 1/hz seconds */ 123 #define WDCDELAY_POLL 1 /* ms */ 124 125 /* timeout for the control commands */ 126 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 127 128 struct pool wdc_xfer_pool; 129 130 #if NWD > 0 131 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 132 #else 133 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 134 const struct ata_bustype wdc_ata_bustype = { 135 SCSIPI_BUSTYPE_ATA, 136 NULL, 137 NULL, 138 NULL, 139 NULL, 140 NULL, 141 NULL, 142 NULL 143 }; 144 #endif 145 146 static int wdcprobe1(struct wdc_channel*, int); 147 static void __wdcerror(struct wdc_channel*, char *); 148 static int __wdcwait_reset(struct wdc_channel *, int, int); 149 static void __wdc_reset_channel(struct wdc_channel *, int); 150 static void __wdccommand_done(struct wdc_channel *, struct ata_xfer *); 151 static void __wdccommand_done_end(struct wdc_channel *, struct ata_xfer *); 152 static void __wdccommand_kill_xfer(struct wdc_channel *, 153 struct ata_xfer *, int); 154 static void __wdccommand_start(struct wdc_channel *, struct ata_xfer *); 155 static int __wdccommand_intr(struct wdc_channel *, struct ata_xfer *, int); 156 static int __wdcwait(struct wdc_channel *, int, int, int); 157 158 #define DEBUG_INTR 0x01 159 #define DEBUG_XFERS 0x02 160 #define DEBUG_STATUS 0x04 161 #define DEBUG_FUNCS 0x08 162 #define DEBUG_PROBE 0x10 163 #define DEBUG_DETACH 0x20 164 #define DEBUG_DELAY 0x40 165 #ifdef WDCDEBUG 166 int wdcdebug_mask = 0; 167 int wdc_nxfer = 0; 168 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 169 #else 170 #define WDCDEBUG_PRINT(args, level) 171 #endif 172 173 /* 174 * A queue of atabus instances, used to ensure the same bus probe order 175 * for a given hardware configuration at each boot. 176 */ 177 struct atabus_initq_head atabus_initq_head = 178 TAILQ_HEAD_INITIALIZER(atabus_initq_head); 179 struct simplelock atabus_interlock = SIMPLELOCK_INITIALIZER; 180 181 /* Test to see controller with at last one attached drive is there. 182 * Returns a bit for each possible drive found (0x01 for drive 0, 183 * 0x02 for drive 1). 184 * Logic: 185 * - If a status register is at 0xff, assume there is no drive here 186 * (ISA has pull-up resistors). Similarly if the status register has 187 * the value we last wrote to the bus (for IDE interfaces without pullups). 188 * If no drive at all -> return. 189 * - reset the controller, wait for it to complete (may take up to 31s !). 190 * If timeout -> return. 191 * - test ATA/ATAPI signatures. If at last one drive found -> return. 192 * - try an ATA command on the master. 193 */ 194 195 static void 196 wdc_drvprobe(struct wdc_channel *chp) 197 { 198 struct ataparams params; 199 struct wdc_softc *wdc = chp->ch_wdc; 200 u_int8_t st0 = 0, st1 = 0; 201 int i, error; 202 203 if (wdcprobe1(chp, 0) == 0) { 204 /* No drives, abort the attach here. */ 205 return; 206 } 207 208 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 209 for (i = 0; i < mstohz(3000); i++) { 210 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 211 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 212 wdc->select(chp,0); 213 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 214 0, WDSD_IBM); 215 delay(10); /* 400ns delay */ 216 st0 = bus_space_read_1(chp->cmd_iot, 217 chp->cmd_iohs[wd_status], 0); 218 } 219 220 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 221 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 222 wdc->select(chp,1); 223 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 224 0, WDSD_IBM | 0x10); 225 delay(10); /* 400ns delay */ 226 st1 = bus_space_read_1(chp->cmd_iot, 227 chp->cmd_iohs[wd_status], 0); 228 } 229 230 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 231 == 0 || 232 (st0 & WDCS_DRDY)) && 233 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 234 == 0 || 235 (st1 & WDCS_DRDY))) 236 break; 237 tsleep(¶ms, PRIBIO, "atadrdy", 1); 238 } 239 if ((st0 & WDCS_DRDY) == 0) 240 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 241 if ((st1 & WDCS_DRDY) == 0) 242 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 243 244 WDCDEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 245 wdc->sc_dev.dv_xname, 246 chp->ch_channel, st0, st1), DEBUG_PROBE); 247 248 /* Wait a bit, some devices are weird just after a reset. */ 249 delay(5000); 250 251 for (i = 0; i < 2; i++) { 252 /* XXX This should be done by other code. */ 253 chp->ch_drive[i].chnl_softc = chp; 254 chp->ch_drive[i].drive = i; 255 256 /* 257 * Init error counter so that an error withing the first xfers 258 * will trigger a downgrade 259 */ 260 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 261 262 /* If controller can't do 16bit flag the drives as 32bit */ 263 if ((wdc->cap & 264 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 265 WDC_CAPABILITY_DATA32) 266 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 267 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 268 continue; 269 270 /* Shortcut in case we've been shutdown */ 271 if (chp->ch_flags & WDCF_SHUTDOWN) 272 return; 273 274 /* issue an identify, to try to detect ghosts */ 275 error = ata_get_params(&chp->ch_drive[i], 276 AT_WAIT | AT_POLL, ¶ms); 277 if (error != CMD_OK) { 278 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 279 280 /* Shortcut in case we've been shutdown */ 281 if (chp->ch_flags & WDCF_SHUTDOWN) 282 return; 283 284 error = ata_get_params(&chp->ch_drive[i], 285 AT_WAIT | AT_POLL, ¶ms); 286 } 287 if (error == CMD_OK) { 288 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 289 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 290 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 291 } else { 292 chp->ch_drive[i].drive_flags &= 293 ~(DRIVE_ATA | DRIVE_ATAPI); 294 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 295 wdc->sc_dev.dv_xname, 296 chp->ch_channel, i, error), DEBUG_PROBE); 297 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 298 continue; 299 /* 300 * Pre-ATA drive ? 301 * Test registers writability (Error register not 302 * writable, but cyllo is), then try an ATA command. 303 */ 304 if (wdc->cap & WDC_CAPABILITY_SELECT) 305 wdc->select(chp,i); 306 bus_space_write_1(chp->cmd_iot, 307 chp->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 308 delay(10); /* 400ns delay */ 309 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 310 0, 0x58); 311 bus_space_write_1(chp->cmd_iot, 312 chp->cmd_iohs[wd_cyl_lo], 0, 0xa5); 313 if (bus_space_read_1(chp->cmd_iot, 314 chp->cmd_iohs[wd_error], 0) == 0x58 || 315 bus_space_read_1(chp->cmd_iot, 316 chp->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 317 WDCDEBUG_PRINT(("%s:%d:%d: register " 318 "writability failed\n", 319 wdc->sc_dev.dv_xname, 320 chp->ch_channel, i), DEBUG_PROBE); 321 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 322 continue; 323 } 324 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 325 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 326 wdc->sc_dev.dv_xname, 327 chp->ch_channel, i), DEBUG_PROBE); 328 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 329 continue; 330 } 331 bus_space_write_1(chp->cmd_iot, 332 chp->cmd_iohs[wd_command], 0, WDCC_RECAL); 333 delay(10); /* 400ns delay */ 334 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 335 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 336 wdc->sc_dev.dv_xname, 337 chp->ch_channel, i), DEBUG_PROBE); 338 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 339 } else { 340 chp->ch_drive[0].drive_flags &= 341 ~(DRIVE_ATA | DRIVE_ATAPI); 342 chp->ch_drive[1].drive_flags &= 343 ~(DRIVE_ATA | DRIVE_ATAPI); 344 } 345 } 346 } 347 } 348 349 void 350 atabusconfig(struct atabus_softc *atabus_sc) 351 { 352 struct wdc_channel *chp = atabus_sc->sc_chan; 353 struct wdc_softc *wdc = chp->ch_wdc; 354 int i, error, need_delref = 0; 355 struct atabus_initq *atabus_initq = NULL; 356 357 if ((error = wdc_addref(chp)) != 0) { 358 aprint_error("%s: unable to enable controller\n", 359 wdc->sc_dev.dv_xname); 360 goto out; 361 } 362 need_delref = 1; 363 364 /* Probe for the drives. */ 365 (*wdc->drv_probe)(chp); 366 367 WDCDEBUG_PRINT(("atabusattach: ch_drive_flags 0x%x 0x%x\n", 368 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 369 DEBUG_PROBE); 370 371 /* If no drives, abort here */ 372 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 373 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 374 goto out; 375 376 /* Shortcut in case we've been shutdown */ 377 if (chp->ch_flags & WDCF_SHUTDOWN) 378 goto out; 379 380 /* Make sure the devices probe in atabus order to avoid jitter. */ 381 simple_lock(&atabus_interlock); 382 while(1) { 383 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 384 if (atabus_initq->atabus_sc == atabus_sc) 385 break; 386 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 387 &atabus_interlock); 388 } 389 simple_unlock(&atabus_interlock); 390 391 /* 392 * Attach an ATAPI bus, if needed. 393 */ 394 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 395 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 396 #if NATAPIBUS > 0 397 wdc_atapibus_attach(atabus_sc); 398 #else 399 /* 400 * Fake the autoconfig "not configured" message 401 */ 402 aprint_normal("atapibus at %s not configured\n", 403 wdc->sc_dev.dv_xname); 404 chp->atapibus = NULL; 405 chp->ch_drive[0].drive_flags &= ~DRIVE_ATAPI; 406 chp->ch_drive[1].drive_flags &= ~DRIVE_ATAPI; 407 #endif 408 } 409 410 for (i = 0; i < 2; i++) { 411 struct ata_device adev; 412 if ((chp->ch_drive[i].drive_flags & 413 (DRIVE_ATA | DRIVE_OLD)) == 0) { 414 continue; 415 } 416 memset(&adev, 0, sizeof(struct ata_device)); 417 adev.adev_bustype = &wdc_ata_bustype; 418 adev.adev_channel = chp->ch_channel; 419 adev.adev_openings = 1; 420 adev.adev_drv_data = &chp->ch_drive[i]; 421 chp->ata_drives[i] = config_found(&atabus_sc->sc_dev, 422 &adev, ataprint); 423 if (chp->ata_drives[i] != NULL) 424 wdc_probe_caps(&chp->ch_drive[i]); 425 else 426 chp->ch_drive[i].drive_flags &= 427 ~(DRIVE_ATA | DRIVE_OLD); 428 } 429 430 /* now that we know the drives, the controller can set its modes */ 431 if (wdc->cap & WDC_CAPABILITY_MODE) { 432 wdc->set_modes(chp); 433 wdc_print_modes(chp); 434 } 435 #if NATARAID > 0 436 if (wdc->cap & WDC_CAPABILITY_RAID) 437 for (i = 0; i < 2; i++) 438 if (chp->ata_drives[i] != NULL) 439 ata_raid_check_component(chp->ata_drives[i]); 440 #endif /* NATARAID > 0 */ 441 442 /* 443 * reset drive_flags for unattached devices, reset state for attached 444 * ones 445 */ 446 for (i = 0; i < 2; i++) { 447 if (chp->ch_drive[i].drv_softc == NULL) 448 chp->ch_drive[i].drive_flags = 0; 449 else 450 chp->ch_drive[i].state = 0; 451 } 452 453 out: 454 if (atabus_initq == NULL) { 455 simple_lock(&atabus_interlock); 456 while(1) { 457 atabus_initq = TAILQ_FIRST(&atabus_initq_head); 458 if (atabus_initq->atabus_sc == atabus_sc) 459 break; 460 ltsleep(&atabus_initq_head, PRIBIO, "ata_initq", 0, 461 &atabus_interlock); 462 } 463 simple_unlock(&atabus_interlock); 464 } 465 simple_lock(&atabus_interlock); 466 TAILQ_REMOVE(&atabus_initq_head, atabus_initq, atabus_initq); 467 simple_unlock(&atabus_interlock); 468 469 free(atabus_initq, M_DEVBUF); 470 wakeup(&atabus_initq_head); 471 472 config_pending_decr(); 473 if (need_delref) 474 wdc_delref(chp); 475 } 476 477 int 478 wdcprobe(struct wdc_channel *chp) 479 { 480 481 return (wdcprobe1(chp, 1)); 482 } 483 484 static int 485 wdcprobe1(struct wdc_channel *chp, int poll) 486 { 487 struct wdc_softc *wdc = chp->ch_wdc; 488 u_int8_t st0, st1, sc, sn, cl, ch; 489 u_int8_t ret_value = 0x03; 490 u_int8_t drive; 491 int s; 492 493 /* 494 * Sanity check to see if the wdc channel responds at all. 495 */ 496 497 s = splbio(); 498 if (wdc == NULL || 499 (wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 500 501 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 502 wdc->select(chp,0); 503 504 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 505 WDSD_IBM); 506 delay(10); /* 400ns delay */ 507 st0 = bus_space_read_1(chp->cmd_iot, 508 chp->cmd_iohs[wd_status], 0); 509 510 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 511 wdc->select(chp,1); 512 513 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 514 WDSD_IBM | 0x10); 515 delay(10); /* 400ns delay */ 516 st1 = bus_space_read_1(chp->cmd_iot, 517 chp->cmd_iohs[wd_status], 0); 518 519 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 520 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 521 chp->ch_channel, st0, st1), DEBUG_PROBE); 522 523 if (st0 == 0xff || st0 == WDSD_IBM) 524 ret_value &= ~0x01; 525 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 526 ret_value &= ~0x02; 527 /* Register writability test, drive 0. */ 528 if (ret_value & 0x01) { 529 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 530 wdc->select(chp,0); 531 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 532 0, WDSD_IBM); 533 bus_space_write_1(chp->cmd_iot, 534 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 535 cl = bus_space_read_1(chp->cmd_iot, 536 chp->cmd_iohs[wd_cyl_lo], 0); 537 if (cl != 0x02) { 538 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 539 "got 0x%x != 0x02\n", 540 wdc != NULL ? 541 wdc->sc_dev.dv_xname : "wdcprobe", 542 chp->ch_channel, cl), 543 DEBUG_PROBE); 544 ret_value &= ~0x01; 545 } 546 bus_space_write_1(chp->cmd_iot, 547 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 548 cl = bus_space_read_1(chp->cmd_iot, 549 chp->cmd_iohs[wd_cyl_lo], 0); 550 if (cl != 0x01) { 551 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 552 "got 0x%x != 0x01\n", 553 wdc != NULL ? 554 wdc->sc_dev.dv_xname : "wdcprobe", 555 chp->ch_channel, cl), 556 DEBUG_PROBE); 557 ret_value &= ~0x01; 558 } 559 bus_space_write_1(chp->cmd_iot, 560 chp->cmd_iohs[wd_sector], 0, 0x01); 561 cl = bus_space_read_1(chp->cmd_iot, 562 chp->cmd_iohs[wd_sector], 0); 563 if (cl != 0x01) { 564 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 565 "got 0x%x != 0x01\n", 566 wdc != NULL ? 567 wdc->sc_dev.dv_xname : "wdcprobe", 568 chp->ch_channel, cl), 569 DEBUG_PROBE); 570 ret_value &= ~0x01; 571 } 572 bus_space_write_1(chp->cmd_iot, 573 chp->cmd_iohs[wd_sector], 0, 0x02); 574 cl = bus_space_read_1(chp->cmd_iot, 575 chp->cmd_iohs[wd_sector], 0); 576 if (cl != 0x02) { 577 WDCDEBUG_PRINT(("%s:%d drive 0 wd_sector: " 578 "got 0x%x != 0x02\n", 579 wdc != NULL ? 580 wdc->sc_dev.dv_xname : "wdcprobe", 581 chp->ch_channel, cl), 582 DEBUG_PROBE); 583 ret_value &= ~0x01; 584 } 585 cl = bus_space_read_1(chp->cmd_iot, 586 chp->cmd_iohs[wd_cyl_lo], 0); 587 if (cl != 0x01) { 588 WDCDEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 589 "got 0x%x != 0x01\n", 590 wdc != NULL ? 591 wdc->sc_dev.dv_xname : "wdcprobe", 592 chp->ch_channel, cl), 593 DEBUG_PROBE); 594 ret_value &= ~0x01; 595 } 596 } 597 /* Register writability test, drive 1. */ 598 if (ret_value & 0x02) { 599 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 600 wdc->select(chp,1); 601 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 602 0, WDSD_IBM | 0x10); 603 bus_space_write_1(chp->cmd_iot, 604 chp->cmd_iohs[wd_cyl_lo], 0, 0x02); 605 cl = bus_space_read_1(chp->cmd_iot, 606 chp->cmd_iohs[wd_cyl_lo], 0); 607 if (cl != 0x02) { 608 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 609 "got 0x%x != 0x02\n", 610 wdc != NULL ? 611 wdc->sc_dev.dv_xname : "wdcprobe", 612 chp->ch_channel, cl), 613 DEBUG_PROBE); 614 ret_value &= ~0x02; 615 } 616 bus_space_write_1(chp->cmd_iot, 617 chp->cmd_iohs[wd_cyl_lo], 0, 0x01); 618 cl = bus_space_read_1(chp->cmd_iot, 619 chp->cmd_iohs[wd_cyl_lo], 0); 620 if (cl != 0x01) { 621 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 622 "got 0x%x != 0x01\n", 623 wdc != NULL ? 624 wdc->sc_dev.dv_xname : "wdcprobe", 625 chp->ch_channel, cl), 626 DEBUG_PROBE); 627 ret_value &= ~0x02; 628 } 629 bus_space_write_1(chp->cmd_iot, 630 chp->cmd_iohs[wd_sector], 0, 0x01); 631 cl = bus_space_read_1(chp->cmd_iot, 632 chp->cmd_iohs[wd_sector], 0); 633 if (cl != 0x01) { 634 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 635 "got 0x%x != 0x01\n", 636 wdc != NULL ? 637 wdc->sc_dev.dv_xname : "wdcprobe", 638 chp->ch_channel, cl), 639 DEBUG_PROBE); 640 ret_value &= ~0x02; 641 } 642 bus_space_write_1(chp->cmd_iot, 643 chp->cmd_iohs[wd_sector], 0, 0x02); 644 cl = bus_space_read_1(chp->cmd_iot, 645 chp->cmd_iohs[wd_sector], 0); 646 if (cl != 0x02) { 647 WDCDEBUG_PRINT(("%s:%d drive 1 wd_sector: " 648 "got 0x%x != 0x02\n", 649 wdc != NULL ? 650 wdc->sc_dev.dv_xname : "wdcprobe", 651 chp->ch_channel, cl), 652 DEBUG_PROBE); 653 ret_value &= ~0x02; 654 } 655 cl = bus_space_read_1(chp->cmd_iot, 656 chp->cmd_iohs[wd_cyl_lo], 0); 657 if (cl != 0x01) { 658 WDCDEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 659 "got 0x%x != 0x01\n", 660 wdc != NULL ? 661 wdc->sc_dev.dv_xname : "wdcprobe", 662 chp->ch_channel, cl), 663 DEBUG_PROBE); 664 ret_value &= ~0x02; 665 } 666 } 667 668 if (ret_value == 0) { 669 splx(s); 670 return 0; 671 } 672 } 673 674 675 #if 0 /* XXX this break some ATA or ATAPI devices */ 676 /* 677 * reset bus. Also send an ATAPI_RESET to devices, in case there are 678 * ATAPI device out there which don't react to the bus reset 679 */ 680 if (ret_value & 0x01) { 681 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 682 wdc->select(chp,0); 683 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 684 0, WDSD_IBM); 685 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 686 ATAPI_SOFT_RESET); 687 } 688 if (ret_value & 0x02) { 689 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 690 wdc->select(chp,0); 691 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 692 0, WDSD_IBM | 0x10); 693 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, 694 ATAPI_SOFT_RESET); 695 } 696 697 delay(5000); 698 #endif 699 700 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_SELECT)) 701 wdc->select(chp,0); 702 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 703 delay(10); /* 400ns delay */ 704 /* assert SRST, wait for reset to complete */ 705 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 706 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 707 DELAY(1000); 708 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 709 WDCTL_IDS | WDCTL_4BIT); 710 DELAY(2000); 711 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 712 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 713 delay(10); /* 400ns delay */ 714 /* ACK interrupt in case there is one pending left (Promise ATA100) */ 715 if (wdc != NULL && (wdc->cap & WDC_CAPABILITY_IRQACK)) 716 wdc->irqack(chp); 717 splx(s); 718 719 ret_value = __wdcwait_reset(chp, ret_value, poll); 720 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 721 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 722 ret_value), DEBUG_PROBE); 723 724 /* if reset failed, there's nothing here */ 725 if (ret_value == 0) 726 return 0; 727 728 /* 729 * Test presence of drives. First test register signatures looking 730 * for ATAPI devices. If it's not an ATAPI and reset said there may 731 * be something here assume it's ATA or OLD. Ghost will be killed 732 * later in attach routine. 733 */ 734 for (drive = 0; drive < 2; drive++) { 735 if ((ret_value & (0x01 << drive)) == 0) 736 continue; 737 if (wdc != NULL && wdc->cap & WDC_CAPABILITY_SELECT) 738 wdc->select(chp,drive); 739 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 740 WDSD_IBM | (drive << 4)); 741 delay(10); /* 400ns delay */ 742 /* Save registers contents */ 743 sc = bus_space_read_1(chp->cmd_iot, 744 chp->cmd_iohs[wd_seccnt], 0); 745 sn = bus_space_read_1(chp->cmd_iot, 746 chp->cmd_iohs[wd_sector], 0); 747 cl = bus_space_read_1(chp->cmd_iot, 748 chp->cmd_iohs[wd_cyl_lo], 0); 749 ch = bus_space_read_1(chp->cmd_iot, 750 chp->cmd_iohs[wd_cyl_hi], 0); 751 752 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 753 "cl=0x%x ch=0x%x\n", 754 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 755 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 756 /* 757 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 758 * we get wrong values here, so ignore it. 759 */ 760 if (cl == 0x14 && ch == 0xeb) { 761 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 762 } else { 763 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 764 if (wdc == NULL || 765 (wdc->cap & WDC_CAPABILITY_PREATA) != 0) 766 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 767 } 768 } 769 return (ret_value); 770 } 771 772 void 773 wdcattach(struct wdc_channel *chp) 774 { 775 struct wdc_softc *wdc = chp->ch_wdc; 776 static int inited = 0; 777 778 if (chp->ch_flags & WDCF_DISABLED) 779 return; 780 781 /* initialise global data */ 782 callout_init(&chp->ch_callout); 783 if (wdc->drv_probe == NULL) 784 wdc->drv_probe = wdc_drvprobe; 785 if (inited == 0) { 786 /* Initialize the ata_xfer pool. */ 787 pool_init(&wdc_xfer_pool, sizeof(struct ata_xfer), 0, 788 0, 0, "wdcspl", NULL); 789 inited++; 790 } 791 TAILQ_INIT(&chp->ch_queue->queue_xfer); 792 chp->ch_queue->queue_freeze = 0; 793 794 chp->atabus = config_found(&wdc->sc_dev, chp, atabusprint); 795 } 796 797 int 798 wdcactivate(struct device *self, enum devact act) 799 { 800 struct wdc_softc *wdc = (struct wdc_softc *)self; 801 int s, i, error = 0; 802 803 s = splbio(); 804 switch (act) { 805 case DVACT_ACTIVATE: 806 error = EOPNOTSUPP; 807 break; 808 809 case DVACT_DEACTIVATE: 810 for (i = 0; i < wdc->nchannels; i++) { 811 error = config_deactivate(wdc->channels[i]->atabus); 812 if (error) 813 break; 814 } 815 break; 816 } 817 splx(s); 818 return (error); 819 } 820 821 int 822 wdcdetach(struct device *self, int flags) 823 { 824 struct wdc_softc *wdc = (struct wdc_softc *)self; 825 struct wdc_channel *chp; 826 int i, error = 0; 827 828 for (i = 0; i < wdc->nchannels; i++) { 829 chp = wdc->channels[i]; 830 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 831 wdc->sc_dev.dv_xname, chp->atabus->dv_xname), DEBUG_DETACH); 832 error = config_detach(chp->atabus, flags); 833 if (error) 834 break; 835 } 836 return (error); 837 } 838 839 /* 840 * Start I/O on a controller, for the given channel. 841 * The first xfer may be not for our channel if the channel queues 842 * are shared. 843 */ 844 void 845 wdcstart(struct wdc_channel *chp) 846 { 847 struct wdc_softc *wdc = chp->ch_wdc; 848 struct ata_xfer *xfer; 849 850 #ifdef WDC_DIAGNOSTIC 851 int spl1, spl2; 852 853 spl1 = splbio(); 854 spl2 = splbio(); 855 if (spl2 != spl1) { 856 printf("wdcstart: not at splbio()\n"); 857 panic("wdcstart"); 858 } 859 splx(spl2); 860 splx(spl1); 861 #endif /* WDC_DIAGNOSTIC */ 862 863 /* is there a xfer ? */ 864 if ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) == NULL) 865 return; 866 867 /* adjust chp, in case we have a shared queue */ 868 chp = xfer->c_chp; 869 870 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 871 return; /* channel aleady active */ 872 } 873 if (__predict_false(chp->ch_queue->queue_freeze > 0)) { 874 return; /* queue froozen */ 875 } 876 #ifdef DIAGNOSTIC 877 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 878 panic("wdcstart: channel waiting for irq"); 879 #endif 880 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 881 if (!(*wdc->claim_hw)(chp, 0)) 882 return; 883 884 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 885 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 886 chp->ch_flags |= WDCF_ACTIVE; 887 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_RESET) { 888 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_RESET; 889 chp->ch_drive[xfer->c_drive].state = 0; 890 } 891 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 892 KASSERT(xfer->c_flags & C_POLL); 893 xfer->c_start(chp, xfer); 894 } 895 896 /* restart an interrupted I/O */ 897 void 898 wdcrestart(void *v) 899 { 900 struct wdc_channel *chp = v; 901 int s; 902 903 s = splbio(); 904 wdcstart(chp); 905 splx(s); 906 } 907 908 909 /* 910 * Interrupt routine for the controller. Acknowledge the interrupt, check for 911 * errors on the current operation, mark it done if necessary, and start the 912 * next request. Also check for a partially done transfer, and continue with 913 * the next chunk if so. 914 */ 915 int 916 wdcintr(void *arg) 917 { 918 struct wdc_channel *chp = arg; 919 struct wdc_softc *wdc = chp->ch_wdc; 920 struct ata_xfer *xfer; 921 int ret; 922 923 if ((wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 924 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 925 DEBUG_INTR); 926 return (0); 927 } 928 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 929 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 930 /* try to clear the pending interrupt anyway */ 931 (void)bus_space_read_1(chp->cmd_iot, 932 chp->cmd_iohs[wd_status], 0); 933 return (0); 934 } 935 936 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 937 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 938 if (chp->ch_flags & WDCF_DMA_WAIT) { 939 wdc->dma_status = 940 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 941 xfer->c_drive, 0); 942 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 943 /* IRQ not for us, not detected by DMA engine */ 944 return 0; 945 } 946 chp->ch_flags &= ~WDCF_DMA_WAIT; 947 } 948 chp->ch_flags &= ~WDCF_IRQ_WAIT; 949 ret = xfer->c_intr(chp, xfer, 1); 950 if (ret == 0) /* irq was not for us, still waiting for irq */ 951 chp->ch_flags |= WDCF_IRQ_WAIT; 952 return (ret); 953 } 954 955 /* Put all disk in RESET state */ 956 void 957 wdc_reset_channel(struct ata_drive_datas *drvp, int flags) 958 { 959 struct wdc_channel *chp = drvp->chnl_softc; 960 struct wdc_softc *wdc = chp->ch_wdc; 961 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 962 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 963 DEBUG_FUNCS); 964 965 966 __wdc_reset_channel(chp, flags); 967 } 968 969 static void 970 __wdc_reset_channel(struct wdc_channel *chp, int flags) 971 { 972 struct ata_xfer *xfer; 973 int drive; 974 975 /* 976 * look for pending xfers. If we have a shared queue, we'll also reset 977 * the other channel if the current xfer is running on it. 978 * Then we'll freese the queue, and dequeue only the xfers for this 979 * channel. xfer->c_kill_xfer() will reset any ATAPI device when 980 * needed. 981 */ 982 chp->ch_queue->queue_freeze++; 983 if ((flags & AT_RST_NOCMD) == 0) { 984 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 985 if (xfer && xfer->c_chp != chp) 986 __wdc_reset_channel(xfer->c_chp, flags); 987 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 988 xfer != 0; 989 xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) { 990 if ((flags & AT_RST_EMERG) == 0) 991 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 992 else 993 wdc_free_xfer(chp, xfer); 994 } 995 } 996 if ((flags & AT_POLL) == 0) { 997 if (chp->ch_flags & WDCF_TH_RESET) { 998 /* no need to schedule a reset more than one time */ 999 chp->ch_queue->queue_freeze--; 1000 return; 1001 } 1002 chp->ch_flags |= WDCF_TH_RESET; 1003 wakeup(&chp->ch_thread); 1004 return; 1005 } 1006 (void) wdcreset(chp, RESET_POLL); 1007 for (drive = 0; drive < 2; drive++) { 1008 chp->ch_drive[drive].state = 0; 1009 } 1010 if ((flags & AT_RST_EMERG) == 0) { 1011 chp->ch_queue->queue_freeze--; 1012 wdcstart(chp); 1013 } else { 1014 /* make sure that we can use polled commands */ 1015 TAILQ_INIT(&chp->ch_queue->queue_xfer); 1016 chp->ch_queue->queue_freeze = 0; 1017 } 1018 } 1019 1020 int 1021 wdcreset(struct wdc_channel *chp, int poll) 1022 { 1023 struct wdc_softc *wdc = chp->ch_wdc; 1024 int drv_mask1, drv_mask2; 1025 int s = 0; 1026 1027 if (wdc->cap & WDC_CAPABILITY_SELECT) 1028 wdc->select(chp,0); 1029 if (poll != RESET_SLEEP) 1030 s = splbio(); 1031 /* master */ 1032 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1033 delay(10); /* 400ns delay */ 1034 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1035 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1036 delay(2000); 1037 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_error], 0); 1038 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1039 WDCTL_4BIT | WDCTL_IDS); 1040 delay(10); /* 400ns delay */ 1041 if (poll != RESET_SLEEP) { 1042 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1043 wdc->irqack(chp); 1044 splx(s); 1045 } 1046 1047 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1048 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1049 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1050 (poll == RESET_SLEEP) ? 0 : 1); 1051 if (drv_mask2 != drv_mask1) { 1052 printf("%s channel %d: reset failed for", 1053 wdc->sc_dev.dv_xname, chp->ch_channel); 1054 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1055 printf(" drive 0"); 1056 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1057 printf(" drive 1"); 1058 printf("\n"); 1059 } 1060 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1061 return (drv_mask1 != drv_mask2) ? 1 : 0; 1062 } 1063 1064 static int 1065 __wdcwait_reset(struct wdc_channel *chp, int drv_mask, int poll) 1066 { 1067 struct wdc_softc *wdc = chp->ch_wdc; 1068 int timeout, nloop; 1069 u_int8_t st0 = 0, st1 = 0; 1070 #ifdef WDCDEBUG 1071 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1072 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1073 #endif 1074 1075 if (poll) 1076 nloop = WDCNDELAY_RST; 1077 else 1078 nloop = WDC_RESET_WAIT * hz / 1000; 1079 /* wait for BSY to deassert */ 1080 for (timeout = 0; timeout < nloop; timeout++) { 1081 if ((drv_mask & 0x01) != 0) { 1082 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1083 wdc->select(chp,0); 1084 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1085 0, WDSD_IBM); /* master */ 1086 delay(10); 1087 st0 = bus_space_read_1(chp->cmd_iot, 1088 chp->cmd_iohs[wd_status], 0); 1089 #ifdef WDCDEBUG 1090 sc0 = bus_space_read_1(chp->cmd_iot, 1091 chp->cmd_iohs[wd_seccnt], 0); 1092 sn0 = bus_space_read_1(chp->cmd_iot, 1093 chp->cmd_iohs[wd_sector], 0); 1094 cl0 = bus_space_read_1(chp->cmd_iot, 1095 chp->cmd_iohs[wd_cyl_lo], 0); 1096 ch0 = bus_space_read_1(chp->cmd_iot, 1097 chp->cmd_iohs[wd_cyl_hi], 0); 1098 #endif 1099 } 1100 if ((drv_mask & 0x02) != 0) { 1101 if (wdc && wdc->cap & WDC_CAPABILITY_SELECT) 1102 wdc->select(chp,1); 1103 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 1104 0, WDSD_IBM | 0x10); /* slave */ 1105 delay(10); 1106 st1 = bus_space_read_1(chp->cmd_iot, 1107 chp->cmd_iohs[wd_status], 0); 1108 #ifdef WDCDEBUG 1109 sc1 = bus_space_read_1(chp->cmd_iot, 1110 chp->cmd_iohs[wd_seccnt], 0); 1111 sn1 = bus_space_read_1(chp->cmd_iot, 1112 chp->cmd_iohs[wd_sector], 0); 1113 cl1 = bus_space_read_1(chp->cmd_iot, 1114 chp->cmd_iohs[wd_cyl_lo], 0); 1115 ch1 = bus_space_read_1(chp->cmd_iot, 1116 chp->cmd_iohs[wd_cyl_hi], 0); 1117 #endif 1118 } 1119 1120 if ((drv_mask & 0x01) == 0) { 1121 /* no master */ 1122 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1123 /* No master, slave is ready, it's done */ 1124 goto end; 1125 } 1126 } else if ((drv_mask & 0x02) == 0) { 1127 /* no slave */ 1128 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1129 /* No slave, master is ready, it's done */ 1130 goto end; 1131 } 1132 } else { 1133 /* Wait for both master and slave to be ready */ 1134 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1135 goto end; 1136 } 1137 } 1138 if (poll) 1139 delay(WDCDELAY); 1140 else 1141 tsleep(&nloop, PRIBIO, "atarst", 1); 1142 } 1143 /* Reset timed out. Maybe it's because drv_mask was not right */ 1144 if (st0 & WDCS_BSY) 1145 drv_mask &= ~0x01; 1146 if (st1 & WDCS_BSY) 1147 drv_mask &= ~0x02; 1148 end: 1149 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1150 "cl=0x%x ch=0x%x\n", 1151 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1152 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1153 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1154 "cl=0x%x ch=0x%x\n", 1155 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", 1156 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1157 1158 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1159 wdc != NULL ? wdc->sc_dev.dv_xname : "wdcprobe", chp->ch_channel, 1160 st0, st1), DEBUG_PROBE); 1161 1162 return drv_mask; 1163 } 1164 1165 /* 1166 * Wait for a drive to be !BSY, and have mask in its status register. 1167 * return -1 for a timeout after "timeout" ms. 1168 */ 1169 static int 1170 __wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout) 1171 { 1172 struct wdc_softc *wdc = chp->ch_wdc; 1173 u_char status; 1174 int time = 0; 1175 1176 WDCDEBUG_PRINT(("__wdcwait %s:%d\n", wdc != NULL ? 1177 wdc->sc_dev.dv_xname : "none", 1178 chp->ch_channel), DEBUG_STATUS); 1179 chp->ch_error = 0; 1180 1181 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1182 1183 for (;;) { 1184 chp->ch_status = status = 1185 bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_status], 0); 1186 if ((status & (WDCS_BSY | mask)) == bits) 1187 break; 1188 if (++time > timeout) { 1189 WDCDEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1190 "status %x error %x (mask 0x%x bits 0x%x)\n", 1191 time, status, 1192 bus_space_read_1(chp->cmd_iot, 1193 chp->cmd_iohs[wd_error], 0), mask, bits), 1194 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1195 return(WDCWAIT_TOUT); 1196 } 1197 delay(WDCDELAY); 1198 } 1199 #ifdef WDCDEBUG 1200 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 1201 printf("__wdcwait: did busy-wait, time=%d\n", time); 1202 #endif 1203 if (status & WDCS_ERR) 1204 chp->ch_error = bus_space_read_1(chp->cmd_iot, 1205 chp->cmd_iohs[wd_error], 0); 1206 #ifdef WDCNDELAY_DEBUG 1207 /* After autoconfig, there should be no long delays. */ 1208 if (!cold && time > WDCNDELAY_DEBUG) { 1209 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1210 if (xfer == NULL) 1211 printf("%s channel %d: warning: busy-wait took %dus\n", 1212 wdc->sc_dev.dv_xname, chp->ch_channel, 1213 WDCDELAY * time); 1214 else 1215 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1216 wdc->sc_dev.dv_xname, chp->ch_channel, 1217 xfer->drive, 1218 WDCDELAY * time); 1219 } 1220 #endif 1221 return(WDCWAIT_OK); 1222 } 1223 1224 /* 1225 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1226 * thread if possible 1227 */ 1228 int 1229 wdcwait(struct wdc_channel *chp, int mask, int bits, int timeout, int flags) 1230 { 1231 int error, i, timeout_hz = mstohz(timeout); 1232 1233 if (timeout_hz == 0 || 1234 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1235 error = __wdcwait(chp, mask, bits, timeout); 1236 else { 1237 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1238 if (error != 0) { 1239 if ((chp->ch_flags & WDCF_TH_RUN) || 1240 (flags & AT_WAIT)) { 1241 /* 1242 * we're running in the channel thread 1243 * or some userland thread context 1244 */ 1245 for (i = 0; i < timeout_hz; i++) { 1246 if (__wdcwait(chp, mask, bits, 1247 WDCDELAY_POLL) == 0) { 1248 error = 0; 1249 break; 1250 } 1251 tsleep(&chp, PRIBIO, "atapoll", 1); 1252 } 1253 } else { 1254 /* 1255 * we're probably in interrupt context, 1256 * ask the thread to come back here 1257 */ 1258 #ifdef DIAGNOSTIC 1259 if (chp->ch_queue->queue_freeze > 0) 1260 panic("wdcwait: queue_freeze"); 1261 #endif 1262 chp->ch_queue->queue_freeze++; 1263 wakeup(&chp->ch_thread); 1264 return(WDCWAIT_THR); 1265 } 1266 } 1267 } 1268 return (error); 1269 } 1270 1271 1272 /* 1273 * Busy-wait for DMA to complete 1274 */ 1275 int 1276 wdc_dmawait(struct wdc_channel *chp, struct ata_xfer *xfer, int timeout) 1277 { 1278 struct wdc_softc *wdc = chp->ch_wdc; 1279 int time; 1280 1281 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 1282 wdc->dma_status = 1283 (*wdc->dma_finish)(wdc->dma_arg, 1284 chp->ch_channel, xfer->c_drive, 0); 1285 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1286 return 0; 1287 delay(WDCDELAY); 1288 } 1289 /* timeout, force a DMA halt */ 1290 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1291 chp->ch_channel, xfer->c_drive, 1); 1292 return 1; 1293 } 1294 1295 void 1296 wdctimeout(void *arg) 1297 { 1298 struct wdc_channel *chp = (struct wdc_channel *)arg; 1299 struct wdc_softc *wdc = chp->ch_wdc; 1300 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 1301 int s; 1302 1303 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1304 1305 s = splbio(); 1306 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 1307 __wdcerror(chp, "lost interrupt"); 1308 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1309 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1310 xfer->c_bcount, 1311 xfer->c_skip); 1312 if (chp->ch_flags & WDCF_DMA_WAIT) { 1313 wdc->dma_status = 1314 (*wdc->dma_finish)(wdc->dma_arg, 1315 chp->ch_channel, xfer->c_drive, 1); 1316 chp->ch_flags &= ~WDCF_DMA_WAIT; 1317 } 1318 /* 1319 * Call the interrupt routine. If we just missed an interrupt, 1320 * it will do what's needed. Else, it will take the needed 1321 * action (reset the device). 1322 * Before that we need to reinstall the timeout callback, 1323 * in case it will miss another irq while in this transfer 1324 * We arbitray chose it to be 1s 1325 */ 1326 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1327 xfer->c_flags |= C_TIMEOU; 1328 chp->ch_flags &= ~WDCF_IRQ_WAIT; 1329 xfer->c_intr(chp, xfer, 1); 1330 } else 1331 __wdcerror(chp, "missing untimeout"); 1332 splx(s); 1333 } 1334 1335 /* 1336 * Probe drive's capabilities, for use by the controller later 1337 * Assumes drvp points to an existing drive. 1338 * XXX this should be a controller-indep function 1339 */ 1340 void 1341 wdc_probe_caps(struct ata_drive_datas *drvp) 1342 { 1343 struct ataparams params, params2; 1344 struct wdc_channel *chp = drvp->chnl_softc; 1345 struct wdc_softc *wdc = chp->ch_wdc; 1346 struct device *drv_dev = drvp->drv_softc; 1347 int i, printed; 1348 char *sep = ""; 1349 int cf_flags; 1350 1351 if (ata_get_params(drvp, AT_WAIT, ¶ms) != CMD_OK) { 1352 /* IDENTIFY failed. Can't tell more about the device */ 1353 return; 1354 } 1355 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 1356 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 1357 /* 1358 * Controller claims 16 and 32 bit transfers. 1359 * Re-do an IDENTIFY with 32-bit transfers, 1360 * and compare results. 1361 */ 1362 drvp->drive_flags |= DRIVE_CAP32; 1363 ata_get_params(drvp, AT_WAIT, ¶ms2); 1364 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 1365 /* Not good. fall back to 16bits */ 1366 drvp->drive_flags &= ~DRIVE_CAP32; 1367 } else { 1368 aprint_normal("%s: 32-bit data port\n", 1369 drv_dev->dv_xname); 1370 } 1371 } 1372 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 1373 if (params.atap_ata_major > 0x01 && 1374 params.atap_ata_major != 0xffff) { 1375 for (i = 14; i > 0; i--) { 1376 if (params.atap_ata_major & (1 << i)) { 1377 aprint_normal("%s: ATA version %d\n", 1378 drv_dev->dv_xname, i); 1379 drvp->ata_vers = i; 1380 break; 1381 } 1382 } 1383 } 1384 #endif 1385 1386 /* An ATAPI device is at last PIO mode 3 */ 1387 if (drvp->drive_flags & DRIVE_ATAPI) 1388 drvp->PIO_mode = 3; 1389 1390 /* 1391 * It's not in the specs, but it seems that some drive 1392 * returns 0xffff in atap_extensions when this field is invalid 1393 */ 1394 if (params.atap_extensions != 0xffff && 1395 (params.atap_extensions & WDC_EXT_MODES)) { 1396 printed = 0; 1397 /* 1398 * XXX some drives report something wrong here (they claim to 1399 * support PIO mode 8 !). As mode is coded on 3 bits in 1400 * SET FEATURE, limit it to 7 (so limit i to 4). 1401 * If higher mode than 7 is found, abort. 1402 */ 1403 for (i = 7; i >= 0; i--) { 1404 if ((params.atap_piomode_supp & (1 << i)) == 0) 1405 continue; 1406 if (i > 4) 1407 return; 1408 /* 1409 * See if mode is accepted. 1410 * If the controller can't set its PIO mode, 1411 * assume the defaults are good, so don't try 1412 * to set it 1413 */ 1414 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1415 /* 1416 * It's OK to pool here, it's fast enouth 1417 * to not bother waiting for interrupt 1418 */ 1419 if (ata_set_mode(drvp, 0x08 | (i + 3), 1420 AT_WAIT) != CMD_OK) 1421 continue; 1422 if (!printed) { 1423 aprint_normal("%s: drive supports PIO mode %d", 1424 drv_dev->dv_xname, i + 3); 1425 sep = ","; 1426 printed = 1; 1427 } 1428 /* 1429 * If controller's driver can't set its PIO mode, 1430 * get the highter one for the drive. 1431 */ 1432 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1433 wdc->PIO_cap >= i + 3) { 1434 drvp->PIO_mode = i + 3; 1435 drvp->PIO_cap = i + 3; 1436 break; 1437 } 1438 } 1439 if (!printed) { 1440 /* 1441 * We didn't find a valid PIO mode. 1442 * Assume the values returned for DMA are buggy too 1443 */ 1444 return; 1445 } 1446 drvp->drive_flags |= DRIVE_MODE; 1447 printed = 0; 1448 for (i = 7; i >= 0; i--) { 1449 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1450 continue; 1451 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1452 (wdc->cap & WDC_CAPABILITY_MODE)) 1453 if (ata_set_mode(drvp, 0x20 | i, AT_WAIT) 1454 != CMD_OK) 1455 continue; 1456 if (!printed) { 1457 aprint_normal("%s DMA mode %d", sep, i); 1458 sep = ","; 1459 printed = 1; 1460 } 1461 if (wdc->cap & WDC_CAPABILITY_DMA) { 1462 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1463 wdc->DMA_cap < i) 1464 continue; 1465 drvp->DMA_mode = i; 1466 drvp->DMA_cap = i; 1467 drvp->drive_flags |= DRIVE_DMA; 1468 } 1469 break; 1470 } 1471 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1472 printed = 0; 1473 for (i = 7; i >= 0; i--) { 1474 if ((params.atap_udmamode_supp & (1 << i)) 1475 == 0) 1476 continue; 1477 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1478 (wdc->cap & WDC_CAPABILITY_UDMA)) 1479 if (ata_set_mode(drvp, 0x40 | i, 1480 AT_WAIT) != CMD_OK) 1481 continue; 1482 if (!printed) { 1483 aprint_normal("%s Ultra-DMA mode %d", 1484 sep, i); 1485 if (i == 2) 1486 aprint_normal(" (Ultra/33)"); 1487 else if (i == 4) 1488 aprint_normal(" (Ultra/66)"); 1489 else if (i == 5) 1490 aprint_normal(" (Ultra/100)"); 1491 else if (i == 6) 1492 aprint_normal(" (Ultra/133)"); 1493 sep = ","; 1494 printed = 1; 1495 } 1496 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1497 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1498 wdc->UDMA_cap < i) 1499 continue; 1500 drvp->UDMA_mode = i; 1501 drvp->UDMA_cap = i; 1502 drvp->drive_flags |= DRIVE_UDMA; 1503 } 1504 break; 1505 } 1506 } 1507 aprint_normal("\n"); 1508 } 1509 1510 /* Try to guess ATA version here, if it didn't get reported */ 1511 if (drvp->ata_vers == 0) { 1512 if (drvp->drive_flags & DRIVE_UDMA) 1513 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1514 else if (drvp->PIO_cap > 2) 1515 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1516 } 1517 cf_flags = drv_dev->dv_cfdata->cf_flags; 1518 if (cf_flags & ATA_CONFIG_PIO_SET) { 1519 drvp->PIO_mode = 1520 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1521 drvp->drive_flags |= DRIVE_MODE; 1522 } 1523 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1524 /* don't care about DMA modes */ 1525 return; 1526 } 1527 if (cf_flags & ATA_CONFIG_DMA_SET) { 1528 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1529 ATA_CONFIG_DMA_DISABLE) { 1530 drvp->drive_flags &= ~DRIVE_DMA; 1531 } else { 1532 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1533 ATA_CONFIG_DMA_OFF; 1534 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1535 } 1536 } 1537 if ((wdc->cap & WDC_CAPABILITY_UDMA) == 0) { 1538 /* don't care about UDMA modes */ 1539 return; 1540 } 1541 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1542 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1543 ATA_CONFIG_UDMA_DISABLE) { 1544 drvp->drive_flags &= ~DRIVE_UDMA; 1545 } else { 1546 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1547 ATA_CONFIG_UDMA_OFF; 1548 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1549 } 1550 } 1551 } 1552 1553 /* 1554 * downgrade the transfer mode of a drive after an error. return 1 if 1555 * downgrade was possible, 0 otherwise. 1556 */ 1557 int 1558 wdc_downgrade_mode(struct ata_drive_datas *drvp, int flags) 1559 { 1560 struct wdc_channel *chp = drvp->chnl_softc; 1561 struct wdc_softc *wdc = chp->ch_wdc; 1562 struct device *drv_dev = drvp->drv_softc; 1563 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1564 1565 /* if drive or controller don't know its mode, we can't do much */ 1566 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1567 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1568 return 0; 1569 /* current drive mode was set by a config flag, let it this way */ 1570 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1571 (cf_flags & ATA_CONFIG_DMA_SET) || 1572 (cf_flags & ATA_CONFIG_UDMA_SET)) 1573 return 0; 1574 1575 /* 1576 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1577 * Maybe we didn't properly notice the cable type 1578 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1579 * It helps in some cases. 1580 */ 1581 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1582 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1583 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1584 drv_dev->dv_xname, drvp->UDMA_mode); 1585 } 1586 1587 /* 1588 * If we were using ultra-DMA, don't downgrade to multiword DMA 1589 * if we noticed a CRC error. It has been noticed that CRC errors 1590 * in ultra-DMA lead to silent data corruption in multiword DMA. 1591 * Data corruption is less likely to occur in PIO mode. 1592 */ 1593 else if ((drvp->drive_flags & DRIVE_UDMA) && 1594 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1595 drvp->drive_flags &= ~DRIVE_UDMA; 1596 drvp->drive_flags |= DRIVE_DMA; 1597 drvp->DMA_mode = drvp->DMA_cap; 1598 printf("%s: transfer error, downgrading to DMA mode %d\n", 1599 drv_dev->dv_xname, drvp->DMA_mode); 1600 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1601 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1602 drvp->PIO_mode = drvp->PIO_cap; 1603 printf("%s: transfer error, downgrading to PIO mode %d\n", 1604 drv_dev->dv_xname, drvp->PIO_mode); 1605 } else /* already using PIO, can't downgrade */ 1606 return 0; 1607 1608 wdc->set_modes(chp); 1609 wdc_print_modes(chp); 1610 /* reset the channel, which will shedule all drives for setup */ 1611 wdc_reset_channel(drvp, flags | AT_RST_NOCMD); 1612 return 1; 1613 } 1614 1615 int 1616 wdc_exec_command(struct ata_drive_datas *drvp, struct wdc_command *wdc_c) 1617 { 1618 struct wdc_channel *chp = drvp->chnl_softc; 1619 struct wdc_softc *wdc = chp->ch_wdc; 1620 struct ata_xfer *xfer; 1621 int s, ret; 1622 1623 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1624 wdc->sc_dev.dv_xname, chp->ch_channel, drvp->drive), 1625 DEBUG_FUNCS); 1626 1627 /* set up an xfer and queue. Wait for completion */ 1628 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1629 WDC_NOSLEEP); 1630 if (xfer == NULL) { 1631 return WDC_TRY_AGAIN; 1632 } 1633 1634 if (wdc->cap & WDC_CAPABILITY_NOIRQ) 1635 wdc_c->flags |= AT_POLL; 1636 if (wdc_c->flags & AT_POLL) 1637 xfer->c_flags |= C_POLL; 1638 xfer->c_drive = drvp->drive; 1639 xfer->c_databuf = wdc_c->data; 1640 xfer->c_bcount = wdc_c->bcount; 1641 xfer->c_cmd = wdc_c; 1642 xfer->c_start = __wdccommand_start; 1643 xfer->c_intr = __wdccommand_intr; 1644 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1645 1646 s = splbio(); 1647 wdc_exec_xfer(chp, xfer); 1648 #ifdef DIAGNOSTIC 1649 if ((wdc_c->flags & AT_POLL) != 0 && 1650 (wdc_c->flags & AT_DONE) == 0) 1651 panic("wdc_exec_command: polled command not done"); 1652 #endif 1653 if (wdc_c->flags & AT_DONE) { 1654 ret = WDC_COMPLETE; 1655 } else { 1656 if (wdc_c->flags & AT_WAIT) { 1657 while ((wdc_c->flags & AT_DONE) == 0) { 1658 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1659 } 1660 ret = WDC_COMPLETE; 1661 } else { 1662 ret = WDC_QUEUED; 1663 } 1664 } 1665 splx(s); 1666 return ret; 1667 } 1668 1669 static void 1670 __wdccommand_start(struct wdc_channel *chp, struct ata_xfer *xfer) 1671 { 1672 struct wdc_softc *wdc = chp->ch_wdc; 1673 int drive = xfer->c_drive; 1674 struct wdc_command *wdc_c = xfer->c_cmd; 1675 1676 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1677 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1678 DEBUG_FUNCS); 1679 1680 if (wdc->cap & WDC_CAPABILITY_SELECT) 1681 wdc->select(chp,drive); 1682 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1683 WDSD_IBM | (drive << 4)); 1684 switch(wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1685 wdc_c->r_st_bmask, wdc_c->timeout, wdc_c->flags)) { 1686 case WDCWAIT_OK: 1687 break; 1688 case WDCWAIT_TOUT: 1689 wdc_c->flags |= AT_TIMEOU; 1690 __wdccommand_done(chp, xfer); 1691 return; 1692 case WDCWAIT_THR: 1693 return; 1694 } 1695 if (wdc_c->flags & AT_POLL) { 1696 /* polled command, disable interrupts */ 1697 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1698 WDCTL_4BIT | WDCTL_IDS); 1699 } 1700 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1701 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1702 1703 if ((wdc_c->flags & AT_POLL) == 0) { 1704 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1705 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1706 wdctimeout, chp); 1707 return; 1708 } 1709 /* 1710 * Polled command. Wait for drive ready or drq. Done in intr(). 1711 * Wait for at last 400ns for status bit to be valid. 1712 */ 1713 delay(10); /* 400ns delay */ 1714 __wdccommand_intr(chp, xfer, 0); 1715 } 1716 1717 static int 1718 __wdccommand_intr(struct wdc_channel *chp, struct ata_xfer *xfer, int irq) 1719 { 1720 struct wdc_softc *wdc = chp->ch_wdc; 1721 struct wdc_command *wdc_c = xfer->c_cmd; 1722 int bcount = wdc_c->bcount; 1723 char *data = wdc_c->data; 1724 int wflags; 1725 1726 if ((wdc_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1727 /* both wait and poll, we can tsleep here */ 1728 wflags = AT_WAIT | AT_POLL; 1729 } else { 1730 wflags = AT_POLL; 1731 } 1732 1733 again: 1734 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1735 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1736 DEBUG_INTR); 1737 /* 1738 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1739 * Reselect again, it doesn't hurt for others commands, and the time 1740 * penalty for the extra regiter write is acceptable, 1741 * wdc_exec_command() isn't called often (mosly for autoconfig) 1742 */ 1743 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1744 WDSD_IBM | (xfer->c_drive << 4)); 1745 if ((wdc_c->flags & AT_XFDONE) != 0) { 1746 /* 1747 * We have completed a data xfer. The drive should now be 1748 * in its initial state 1749 */ 1750 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, 1751 wdc_c->r_st_bmask, (irq == 0) ? wdc_c->timeout : 0, 1752 wflags) == WDCWAIT_TOUT) { 1753 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1754 return 0; /* IRQ was not for us */ 1755 wdc_c->flags |= AT_TIMEOU; 1756 } 1757 goto out; 1758 } 1759 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1760 (irq == 0) ? wdc_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1761 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1762 return 0; /* IRQ was not for us */ 1763 wdc_c->flags |= AT_TIMEOU; 1764 goto out; 1765 } 1766 if (wdc->cap & WDC_CAPABILITY_IRQACK) 1767 wdc->irqack(chp); 1768 if (wdc_c->flags & AT_READ) { 1769 if ((chp->ch_status & WDCS_DRQ) == 0) { 1770 wdc_c->flags |= AT_TIMEOU; 1771 goto out; 1772 } 1773 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1774 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1775 0, (u_int32_t*)data, bcount >> 2); 1776 data += bcount & 0xfffffffc; 1777 bcount = bcount & 0x03; 1778 } 1779 if (bcount > 0) 1780 bus_space_read_multi_2(chp->cmd_iot, 1781 chp->cmd_iohs[wd_data], 0, 1782 (u_int16_t *)data, bcount >> 1); 1783 /* at this point the drive should be in its initial state */ 1784 wdc_c->flags |= AT_XFDONE; 1785 /* XXX should read status register here ? */ 1786 } else if (wdc_c->flags & AT_WRITE) { 1787 if ((chp->ch_status & WDCS_DRQ) == 0) { 1788 wdc_c->flags |= AT_TIMEOU; 1789 goto out; 1790 } 1791 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_CAP32) { 1792 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1793 0, (u_int32_t*)data, bcount >> 2); 1794 data += bcount & 0xfffffffc; 1795 bcount = bcount & 0x03; 1796 } 1797 if (bcount > 0) 1798 bus_space_write_multi_2(chp->cmd_iot, 1799 chp->cmd_iohs[wd_data], 0, 1800 (u_int16_t *)data, bcount >> 1); 1801 wdc_c->flags |= AT_XFDONE; 1802 if ((wdc_c->flags & AT_POLL) == 0) { 1803 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1804 callout_reset(&chp->ch_callout, 1805 wdc_c->timeout / 1000 * hz, wdctimeout, chp); 1806 return 1; 1807 } else { 1808 goto again; 1809 } 1810 } 1811 out: 1812 __wdccommand_done(chp, xfer); 1813 return 1; 1814 } 1815 1816 static void 1817 __wdccommand_done(struct wdc_channel *chp, struct ata_xfer *xfer) 1818 { 1819 struct wdc_softc *wdc = chp->ch_wdc; 1820 struct wdc_command *wdc_c = xfer->c_cmd; 1821 1822 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1823 wdc->sc_dev.dv_xname, chp->ch_channel, xfer->c_drive), 1824 DEBUG_FUNCS); 1825 1826 1827 if (chp->ch_status & WDCS_DWF) 1828 wdc_c->flags |= AT_DF; 1829 if (chp->ch_status & WDCS_ERR) { 1830 wdc_c->flags |= AT_ERROR; 1831 wdc_c->r_error = chp->ch_error; 1832 } 1833 if ((wdc_c->flags & AT_READREG) != 0 && 1834 (wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1835 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1836 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, 1837 chp->cmd_iohs[wd_sdh], 0); 1838 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, 1839 chp->cmd_iohs[wd_cyl_hi], 0) << 8; 1840 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, 1841 chp->cmd_iohs[wd_cyl_lo], 0); 1842 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, 1843 chp->cmd_iohs[wd_sector], 0); 1844 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, 1845 chp->cmd_iohs[wd_seccnt], 0); 1846 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, 1847 chp->cmd_iohs[wd_error], 0); 1848 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, 1849 chp->cmd_iohs[wd_precomp], 0); 1850 } 1851 __wdccommand_done_end(chp, xfer); 1852 } 1853 1854 static void 1855 __wdccommand_done_end(struct wdc_channel *chp, struct ata_xfer *xfer) 1856 { 1857 struct wdc_command *wdc_c = xfer->c_cmd; 1858 1859 callout_stop(&chp->ch_callout); 1860 wdc_c->flags |= AT_DONE; 1861 if (wdc_c->flags & AT_POLL) { 1862 /* enable interrupts */ 1863 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 1864 WDCTL_4BIT); 1865 delay(10); /* some drives need a little delay here */ 1866 } 1867 wdc_free_xfer(chp, xfer); 1868 if (wdc_c->flags & AT_WAIT) 1869 wakeup(wdc_c); 1870 else if (wdc_c->callback) 1871 wdc_c->callback(wdc_c->callback_arg); 1872 wdcstart(chp); 1873 return; 1874 } 1875 1876 static void 1877 __wdccommand_kill_xfer(struct wdc_channel *chp, struct ata_xfer *xfer, 1878 int reason) 1879 { 1880 struct wdc_command *wdc_c = xfer->c_cmd; 1881 1882 switch (reason) { 1883 case KILL_GONE: 1884 wdc_c->flags |= AT_GONE; 1885 break; 1886 case KILL_RESET: 1887 wdc_c->flags |= AT_RESET; 1888 break; 1889 default: 1890 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1891 reason); 1892 panic("__wdccommand_kill_xfer"); 1893 } 1894 __wdccommand_done_end(chp, xfer); 1895 1896 } 1897 1898 /* 1899 * Send a command. The drive should be ready. 1900 * Assumes interrupts are blocked. 1901 */ 1902 void 1903 wdccommand(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1904 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1905 u_int8_t precomp) 1906 { 1907 struct wdc_softc *wdc = chp->ch_wdc; 1908 1909 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1910 "sector=%d count=%d precomp=%d\n", wdc->sc_dev.dv_xname, 1911 chp->ch_channel, drive, command, cylin, head, sector, count, 1912 precomp), DEBUG_FUNCS); 1913 1914 if (wdc->cap & WDC_CAPABILITY_SELECT) 1915 wdc->select(chp,drive); 1916 1917 /* Select drive, head, and addressing mode. */ 1918 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1919 WDSD_IBM | (drive << 4) | head); 1920 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1921 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_precomp], 0, 1922 precomp); 1923 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_lo], 0, cylin); 1924 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_cyl_hi], 1925 0, cylin >> 8); 1926 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sector], 0, sector); 1927 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1928 1929 /* Send command. */ 1930 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1931 return; 1932 } 1933 1934 /* 1935 * Send a 48-bit addressing command. The drive should be ready. 1936 * Assumes interrupts are blocked. 1937 */ 1938 void 1939 wdccommandext(struct wdc_channel *chp, u_int8_t drive, u_int8_t command, 1940 u_int64_t blkno, u_int16_t count) 1941 { 1942 struct wdc_softc *wdc = chp->ch_wdc; 1943 1944 WDCDEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1945 "count=%d\n", wdc->sc_dev.dv_xname, 1946 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1947 DEBUG_FUNCS); 1948 1949 if (wdc->cap & WDC_CAPABILITY_SELECT) 1950 wdc->select(chp,drive); 1951 1952 /* Select drive, head, and addressing mode. */ 1953 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1954 (drive << 4) | WDSD_LBA); 1955 1956 /* previous */ 1957 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1958 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 1959 0, count >> 8); 1960 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1961 0, blkno >> 40); 1962 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1963 0, blkno >> 32); 1964 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 1965 0, blkno >> 24); 1966 1967 /* current */ 1968 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_features], 0, 0); 1969 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_seccnt], 0, count); 1970 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_hi], 1971 0, blkno >> 16); 1972 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_mi], 1973 0, blkno >> 8); 1974 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_lba_lo], 0, blkno); 1975 1976 /* Send command. */ 1977 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 1978 return; 1979 } 1980 1981 /* 1982 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1983 * tested by the caller. 1984 */ 1985 void 1986 wdccommandshort(struct wdc_channel *chp, int drive, int command) 1987 { 1988 struct wdc_softc *wdc = chp->ch_wdc; 1989 1990 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1991 wdc->sc_dev.dv_xname, chp->ch_channel, drive, command), 1992 DEBUG_FUNCS); 1993 1994 if (wdc->cap & WDC_CAPABILITY_SELECT) 1995 wdc->select(chp,drive); 1996 1997 /* Select drive. */ 1998 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_sdh], 0, 1999 WDSD_IBM | (drive << 4)); 2000 2001 bus_space_write_1(chp->cmd_iot, chp->cmd_iohs[wd_command], 0, command); 2002 } 2003 2004 /* Add a command to the queue and start controller. Must be called at splbio */ 2005 void 2006 wdc_exec_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 2007 { 2008 2009 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 2010 chp->ch_channel, xfer->c_drive), DEBUG_XFERS); 2011 2012 /* complete xfer setup */ 2013 xfer->c_chp = chp; 2014 2015 /* insert at the end of command list */ 2016 TAILQ_INSERT_TAIL(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 2017 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 2018 chp->ch_flags), DEBUG_XFERS); 2019 wdcstart(chp); 2020 } 2021 2022 struct ata_xfer * 2023 wdc_get_xfer(int flags) 2024 { 2025 struct ata_xfer *xfer; 2026 int s; 2027 2028 s = splbio(); 2029 xfer = pool_get(&wdc_xfer_pool, 2030 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 2031 splx(s); 2032 if (xfer != NULL) { 2033 memset(xfer, 0, sizeof(struct ata_xfer)); 2034 } 2035 return xfer; 2036 } 2037 2038 void 2039 wdc_free_xfer(struct wdc_channel *chp, struct ata_xfer *xfer) 2040 { 2041 struct wdc_softc *wdc = chp->ch_wdc; 2042 int s; 2043 2044 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 2045 (*wdc->free_hw)(chp); 2046 s = splbio(); 2047 chp->ch_flags &= ~WDCF_ACTIVE; 2048 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, xfer, c_xferchain); 2049 pool_put(&wdc_xfer_pool, xfer); 2050 splx(s); 2051 } 2052 2053 /* 2054 * Kill off all pending xfers for a wdc_channel. 2055 * 2056 * Must be called at splbio(). 2057 */ 2058 void 2059 wdc_kill_pending(struct wdc_channel *chp) 2060 { 2061 struct ata_xfer *xfer; 2062 2063 while ((xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer)) != NULL) { 2064 chp = xfer->c_chp; 2065 (*xfer->c_kill_xfer)(chp, xfer, KILL_GONE); 2066 } 2067 } 2068 2069 static void 2070 __wdcerror(struct wdc_channel *chp, char *msg) 2071 { 2072 struct wdc_softc *wdc = chp->ch_wdc; 2073 struct ata_xfer *xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 2074 2075 if (xfer == NULL) 2076 printf("%s:%d: %s\n", wdc->sc_dev.dv_xname, chp->ch_channel, 2077 msg); 2078 else 2079 printf("%s:%d:%d: %s\n", wdc->sc_dev.dv_xname, 2080 chp->ch_channel, xfer->c_drive, msg); 2081 } 2082 2083 /* 2084 * the bit bucket 2085 */ 2086 void 2087 wdcbit_bucket(struct wdc_channel *chp, int size) 2088 { 2089 2090 for (; size >= 2; size -= 2) 2091 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2092 if (size) 2093 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_iohs[wd_data], 0); 2094 } 2095 2096 int 2097 wdc_addref(struct wdc_channel *chp) 2098 { 2099 struct wdc_softc *wdc = chp->ch_wdc; 2100 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2101 int s, error = 0; 2102 2103 s = splbio(); 2104 if (adapt->adapt_refcnt++ == 0 && 2105 adapt->adapt_enable != NULL) { 2106 error = (*adapt->adapt_enable)(&wdc->sc_dev, 1); 2107 if (error) 2108 adapt->adapt_refcnt--; 2109 } 2110 splx(s); 2111 return (error); 2112 } 2113 2114 void 2115 wdc_delref(struct wdc_channel *chp) 2116 { 2117 struct wdc_softc *wdc = chp->ch_wdc; 2118 struct scsipi_adapter *adapt = &wdc->sc_atapi_adapter._generic; 2119 int s; 2120 2121 s = splbio(); 2122 if (adapt->adapt_refcnt-- == 1 && 2123 adapt->adapt_enable != NULL) 2124 (void) (*adapt->adapt_enable)(&wdc->sc_dev, 0); 2125 splx(s); 2126 } 2127 2128 void 2129 wdc_print_modes(struct wdc_channel *chp) 2130 { 2131 struct wdc_softc *wdc = chp->ch_wdc; 2132 int drive; 2133 struct ata_drive_datas *drvp; 2134 2135 for (drive = 0; drive < 2; drive++) { 2136 drvp = &chp->ch_drive[drive]; 2137 if ((drvp->drive_flags & DRIVE) == 0) 2138 continue; 2139 aprint_normal("%s(%s:%d:%d): using PIO mode %d", 2140 drvp->drv_softc->dv_xname, 2141 wdc->sc_dev.dv_xname, 2142 chp->ch_channel, drive, drvp->PIO_mode); 2143 if (drvp->drive_flags & DRIVE_DMA) 2144 aprint_normal(", DMA mode %d", drvp->DMA_mode); 2145 if (drvp->drive_flags & DRIVE_UDMA) { 2146 aprint_normal(", Ultra-DMA mode %d", drvp->UDMA_mode); 2147 if (drvp->UDMA_mode == 2) 2148 aprint_normal(" (Ultra/33)"); 2149 else if (drvp->UDMA_mode == 4) 2150 aprint_normal(" (Ultra/66)"); 2151 else if (drvp->UDMA_mode == 5) 2152 aprint_normal(" (Ultra/100)"); 2153 else if (drvp->UDMA_mode == 6) 2154 aprint_normal(" (Ultra/133)"); 2155 } 2156 if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) 2157 aprint_normal(" (using DMA data transfers)"); 2158 aprint_normal("\n"); 2159 } 2160 }
Cache object: 2b2a7d476daacd6fb848163f761b8d5e
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