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sys/dev/ic/wdc.c
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1 /* $NetBSD: wdc.c,v 1.255.4.2 2009/10/18 16:39:13 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /*- 33 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 34 * All rights reserved. 35 * 36 * This code is derived from software contributed to The NetBSD Foundation 37 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 38 * 39 * Redistribution and use in source and binary forms, with or without 40 * modification, are permitted provided that the following conditions 41 * are met: 42 * 1. Redistributions of source code must retain the above copyright 43 * notice, this list of conditions and the following disclaimer. 44 * 2. Redistributions in binary form must reproduce the above copyright 45 * notice, this list of conditions and the following disclaimer in the 46 * documentation and/or other materials provided with the distribution. 47 * 48 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 49 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 50 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 51 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 52 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 53 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 54 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 55 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 56 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 57 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 58 * POSSIBILITY OF SUCH DAMAGE. 59 */ 60 61 /* 62 * CODE UNTESTED IN THE CURRENT REVISION: 63 */ 64 65 #include <sys/cdefs.h> 66 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.255.4.2 2009/10/18 16:39:13 bouyer Exp $"); 67 68 #include "opt_ata.h" 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/conf.h> 74 #include <sys/buf.h> 75 #include <sys/device.h> 76 #include <sys/malloc.h> 77 #include <sys/syslog.h> 78 #include <sys/proc.h> 79 80 #include <sys/intr.h> 81 #include <sys/bus.h> 82 83 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 84 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 85 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 86 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 87 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 88 #define bus_space_read_stream_2 bus_space_read_2 89 #define bus_space_read_stream_4 bus_space_read_4 90 #define bus_space_write_stream_2 bus_space_write_2 91 #define bus_space_write_stream_4 bus_space_write_4 92 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 93 94 #include <dev/ata/atavar.h> 95 #include <dev/ata/atareg.h> 96 #include <dev/ata/satareg.h> 97 #include <dev/ata/satavar.h> 98 #include <dev/ic/wdcreg.h> 99 #include <dev/ic/wdcvar.h> 100 101 #include "locators.h" 102 103 #include "atapibus.h" 104 #include "wd.h" 105 #include "sata.h" 106 107 #define WDCDELAY 100 /* 100 microseconds */ 108 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 109 #if 0 110 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 111 #define WDCNDELAY_DEBUG 50 112 #endif 113 114 /* When polling wait that much and then tsleep for 1/hz seconds */ 115 #define WDCDELAY_POLL 1 /* ms */ 116 117 /* timeout for the control commands */ 118 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 119 120 /* 121 * timeout when waiting for BSY to deassert when probing. 122 * set to 5s. From the standards this could be up to 31, but we can't 123 * wait that much at boot time, and 5s seems to be enouth. 124 */ 125 #define WDC_PROBE_WAIT 5 126 127 128 #if NWD > 0 129 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 130 #else 131 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 132 const struct ata_bustype wdc_ata_bustype = { 133 SCSIPI_BUSTYPE_ATA, 134 NULL, /* wdc_ata_bio */ 135 NULL, /* wdc_reset_drive */ 136 wdc_reset_channel, 137 wdc_exec_command, 138 NULL, /* ata_get_params */ 139 NULL, /* wdc_ata_addref */ 140 NULL, /* wdc_ata_delref */ 141 NULL /* ata_kill_pending */ 142 }; 143 #endif 144 145 /* Flags to wdcreset(). */ 146 #define RESET_POLL 1 147 #define RESET_SLEEP 0 /* wdcreset() will use tsleep() */ 148 149 static int wdcprobe1(struct ata_channel *, int); 150 static int wdcreset(struct ata_channel *, int); 151 static void __wdcerror(struct ata_channel *, const char *); 152 static int __wdcwait_reset(struct ata_channel *, int, int); 153 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 154 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 155 static void __wdccommand_kill_xfer(struct ata_channel *, 156 struct ata_xfer *, int); 157 static void __wdccommand_start(struct ata_channel *, struct ata_xfer *); 158 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 159 static int __wdcwait(struct ata_channel *, int, int, int); 160 161 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 162 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 163 164 #define DEBUG_INTR 0x01 165 #define DEBUG_XFERS 0x02 166 #define DEBUG_STATUS 0x04 167 #define DEBUG_FUNCS 0x08 168 #define DEBUG_PROBE 0x10 169 #define DEBUG_DETACH 0x20 170 #define DEBUG_DELAY 0x40 171 #ifdef ATADEBUG 172 extern int atadebug_mask; /* init'ed in ata.c */ 173 int wdc_nxfer = 0; 174 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 175 #else 176 #define ATADEBUG_PRINT(args, level) 177 #endif 178 179 /* 180 * Initialize the "shadow register" handles for a standard wdc controller. 181 */ 182 void 183 wdc_init_shadow_regs(struct ata_channel *chp) 184 { 185 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 186 187 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 188 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 189 } 190 191 /* 192 * Allocate a wdc_regs array, based on the number of channels. 193 */ 194 void 195 wdc_allocate_regs(struct wdc_softc *wdc) 196 { 197 198 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 199 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 200 } 201 202 #if NSATA > 0 203 /* 204 * probe drives on SATA controllers with standard SATA registers: 205 * bring the PHYs online, read the drive signature and set drive flags 206 * appropriately. 207 */ 208 void 209 wdc_sataprobe(struct ata_channel *chp) 210 { 211 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 212 uint8_t st = 0, sc, sn, cl, ch; 213 int i, s; 214 215 /* XXX This should be done by other code. */ 216 for (i = 0; i < chp->ch_ndrive; i++) { 217 chp->ch_drive[i].chnl_softc = chp; 218 chp->ch_drive[i].drive = i; 219 } 220 221 /* reset the PHY and bring online */ 222 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 223 wdr->sata_status)) { 224 case SStatus_DET_DEV: 225 /* wait 5s for BSY to clear */ 226 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 227 bus_space_write_1(wdr->cmd_iot, 228 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 229 delay(10); /* 400ns delay */ 230 st = bus_space_read_1(wdr->cmd_iot, 231 wdr->cmd_iohs[wd_status], 0); 232 if ((st & WDCS_BSY) == 0) 233 break; 234 tsleep(&chp, PRIBIO, "sataprb", 1); 235 } 236 if (i == WDC_PROBE_WAIT * hz) 237 aprint_error_dev(chp->ch_atac->atac_dev, 238 "BSY never cleared, status 0x%02x\n", st); 239 sc = bus_space_read_1(wdr->cmd_iot, 240 wdr->cmd_iohs[wd_seccnt], 0); 241 sn = bus_space_read_1(wdr->cmd_iot, 242 wdr->cmd_iohs[wd_sector], 0); 243 cl = bus_space_read_1(wdr->cmd_iot, 244 wdr->cmd_iohs[wd_cyl_lo], 0); 245 ch = bus_space_read_1(wdr->cmd_iot, 246 wdr->cmd_iohs[wd_cyl_hi], 0); 247 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 248 "cl=0x%x ch=0x%x\n", 249 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 250 sc, sn, cl, ch), DEBUG_PROBE); 251 /* 252 * sc and sn are supposed to be 0x1 for ATAPI, but in some 253 * cases we get wrong values here, so ignore it. 254 */ 255 s = splbio(); 256 if (cl == 0x14 && ch == 0xeb) 257 chp->ch_drive[0].drive_flags |= DRIVE_ATAPI; 258 else 259 chp->ch_drive[0].drive_flags |= DRIVE_ATA; 260 splx(s); 261 262 /* 263 * issue a reset in case only the interface part of the drive 264 * is up 265 */ 266 if (wdcreset(chp, RESET_SLEEP) != 0) 267 chp->ch_drive[0].drive_flags = 0; 268 break; 269 270 default: 271 break; 272 } 273 } 274 #endif /* NSATA > 0 */ 275 276 277 /* Test to see controller with at last one attached drive is there. 278 * Returns a bit for each possible drive found (0x01 for drive 0, 279 * 0x02 for drive 1). 280 * Logic: 281 * - If a status register is at 0xff, assume there is no drive here 282 * (ISA has pull-up resistors). Similarly if the status register has 283 * the value we last wrote to the bus (for IDE interfaces without pullups). 284 * If no drive at all -> return. 285 * - reset the controller, wait for it to complete (may take up to 31s !). 286 * If timeout -> return. 287 * - test ATA/ATAPI signatures. If at last one drive found -> return. 288 * - try an ATA command on the master. 289 */ 290 291 void 292 wdc_drvprobe(struct ata_channel *chp) 293 { 294 struct ataparams params; 295 struct atac_softc *atac = chp->ch_atac; 296 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 297 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 298 u_int8_t st0 = 0, st1 = 0; 299 int i, j, error, s; 300 301 if (wdcprobe1(chp, 0) == 0) { 302 /* No drives, abort the attach here. */ 303 return; 304 } 305 306 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 307 for (i = 0; i < mstohz(3000); i++) { 308 if (chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 309 if (wdc->select) 310 wdc->select(chp,0); 311 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 312 0, WDSD_IBM); 313 delay(10); /* 400ns delay */ 314 st0 = bus_space_read_1(wdr->cmd_iot, 315 wdr->cmd_iohs[wd_status], 0); 316 } 317 318 if (chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) { 319 if (wdc->select) 320 wdc->select(chp,1); 321 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 322 0, WDSD_IBM | 0x10); 323 delay(10); /* 400ns delay */ 324 st1 = bus_space_read_1(wdr->cmd_iot, 325 wdr->cmd_iohs[wd_status], 0); 326 } 327 328 if (((chp->ch_drive[0].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 329 == 0 || 330 (st0 & WDCS_DRDY)) && 331 ((chp->ch_drive[1].drive_flags & (DRIVE_ATA|DRIVE_OLD)) 332 == 0 || 333 (st1 & WDCS_DRDY))) 334 break; 335 tsleep(¶ms, PRIBIO, "atadrdy", 1); 336 } 337 s = splbio(); 338 if ((st0 & WDCS_DRDY) == 0) 339 chp->ch_drive[0].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 340 if ((st1 & WDCS_DRDY) == 0) 341 chp->ch_drive[1].drive_flags &= ~(DRIVE_ATA|DRIVE_OLD); 342 splx(s); 343 344 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 345 device_xname(atac->atac_dev), 346 chp->ch_channel, st0, st1), DEBUG_PROBE); 347 348 /* Wait a bit, some devices are weird just after a reset. */ 349 delay(5000); 350 351 for (i = 0; i < chp->ch_ndrive; i++) { 352 /* XXX This should be done by other code. */ 353 chp->ch_drive[i].chnl_softc = chp; 354 chp->ch_drive[i].drive = i; 355 356 #if NATA_DMA 357 /* 358 * Init error counter so that an error withing the first xfers 359 * will trigger a downgrade 360 */ 361 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 362 #endif 363 364 /* If controller can't do 16bit flag the drives as 32bit */ 365 if ((atac->atac_cap & 366 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 367 s = splbio(); 368 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 369 splx(s); 370 } 371 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 372 continue; 373 374 /* Shortcut in case we've been shutdown */ 375 if (chp->ch_flags & ATACH_SHUTDOWN) 376 return; 377 378 /* 379 * Issue an identify, to try to detect ghosts. 380 * Note that we can't use interrupts here, because if there 381 * is no devices, we will get a command aborted without 382 * interrupts. 383 */ 384 error = ata_get_params(&chp->ch_drive[i], 385 AT_WAIT | AT_POLL, ¶ms); 386 if (error != CMD_OK) { 387 tsleep(¶ms, PRIBIO, "atacnf", mstohz(1000)); 388 389 /* Shortcut in case we've been shutdown */ 390 if (chp->ch_flags & ATACH_SHUTDOWN) 391 return; 392 393 error = ata_get_params(&chp->ch_drive[i], 394 AT_WAIT | AT_POLL, ¶ms); 395 } 396 if (error == CMD_OK) { 397 /* If IDENTIFY succeeded, this is not an OLD ctrl */ 398 s = splbio(); 399 for (j = 0; j < chp->ch_ndrive; j++) 400 chp->ch_drive[j].drive_flags &= ~DRIVE_OLD; 401 splx(s); 402 } else { 403 s = splbio(); 404 chp->ch_drive[i].drive_flags &= 405 ~(DRIVE_ATA | DRIVE_ATAPI); 406 splx(s); 407 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 408 device_xname(atac->atac_dev), 409 chp->ch_channel, i, error), DEBUG_PROBE); 410 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 411 continue; 412 /* 413 * Pre-ATA drive ? 414 * Test registers writability (Error register not 415 * writable, but cyllo is), then try an ATA command. 416 */ 417 if (wdc->select) 418 wdc->select(chp,i); 419 bus_space_write_1(wdr->cmd_iot, 420 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 421 delay(10); /* 400ns delay */ 422 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 423 0, 0x58); 424 bus_space_write_1(wdr->cmd_iot, 425 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 426 if (bus_space_read_1(wdr->cmd_iot, 427 wdr->cmd_iohs[wd_error], 0) == 0x58 || 428 bus_space_read_1(wdr->cmd_iot, 429 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 430 ATADEBUG_PRINT(("%s:%d:%d: register " 431 "writability failed\n", 432 device_xname(atac->atac_dev), 433 chp->ch_channel, i), DEBUG_PROBE); 434 s = splbio(); 435 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 436 splx(s); 437 continue; 438 } 439 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 440 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 441 device_xname(atac->atac_dev), 442 chp->ch_channel, i), DEBUG_PROBE); 443 s = splbio(); 444 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 445 splx(s); 446 continue; 447 } 448 bus_space_write_1(wdr->cmd_iot, 449 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 450 delay(10); /* 400ns delay */ 451 if (wdc_wait_for_ready(chp, 10000, 0) == WDCWAIT_TOUT) { 452 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 453 device_xname(atac->atac_dev), 454 chp->ch_channel, i), DEBUG_PROBE); 455 s = splbio(); 456 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 457 splx(s); 458 } else { 459 s = splbio(); 460 for (j = 0; j < chp->ch_ndrive; j++) 461 chp->ch_drive[j].drive_flags &= 462 ~(DRIVE_ATA | DRIVE_ATAPI); 463 splx(s); 464 } 465 } 466 } 467 } 468 469 int 470 wdcprobe(struct ata_channel *chp) 471 { 472 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 473 /* default reset method */ 474 if (wdc->reset == NULL) 475 wdc->reset = wdc_do_reset; 476 477 return (wdcprobe1(chp, 1)); 478 } 479 480 static int 481 wdcprobe1(struct ata_channel *chp, int poll) 482 { 483 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 484 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 485 u_int8_t st0 = 0, st1 = 0, sc, sn, cl, ch; 486 u_int8_t ret_value = 0x03; 487 u_int8_t drive; 488 int s; 489 /* XXX if poll, wdc_probe_count is 0. */ 490 int wdc_probe_count = 491 poll ? (WDC_PROBE_WAIT / WDCDELAY) 492 : (WDC_PROBE_WAIT * hz); 493 494 /* 495 * Sanity check to see if the wdc channel responds at all. 496 */ 497 498 s = splbio(); 499 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 500 while (wdc_probe_count-- > 0) { 501 if (wdc->select) 502 wdc->select(chp,0); 503 504 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 505 0, WDSD_IBM); 506 delay(10); /* 400ns delay */ 507 st0 = bus_space_read_1(wdr->cmd_iot, 508 wdr->cmd_iohs[wd_status], 0); 509 510 if (wdc->select) 511 wdc->select(chp,1); 512 513 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 514 0, WDSD_IBM | 0x10); 515 delay(10); /* 400ns delay */ 516 st1 = bus_space_read_1(wdr->cmd_iot, 517 wdr->cmd_iohs[wd_status], 0); 518 if ((st0 & WDCS_BSY) == 0) 519 break; 520 } 521 522 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 523 device_xname(chp->ch_atac->atac_dev), 524 chp->ch_channel, st0, st1), DEBUG_PROBE); 525 526 if (st0 == 0xff || st0 == WDSD_IBM) 527 ret_value &= ~0x01; 528 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 529 ret_value &= ~0x02; 530 /* Register writability test, drive 0. */ 531 if (ret_value & 0x01) { 532 if (wdc->select) 533 wdc->select(chp,0); 534 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 535 0, WDSD_IBM); 536 bus_space_write_1(wdr->cmd_iot, 537 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 538 cl = bus_space_read_1(wdr->cmd_iot, 539 wdr->cmd_iohs[wd_cyl_lo], 0); 540 if (cl != 0x02) { 541 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 542 "got 0x%x != 0x02\n", 543 device_xname(chp->ch_atac->atac_dev), 544 chp->ch_channel, cl), 545 DEBUG_PROBE); 546 ret_value &= ~0x01; 547 } 548 bus_space_write_1(wdr->cmd_iot, 549 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 550 cl = bus_space_read_1(wdr->cmd_iot, 551 wdr->cmd_iohs[wd_cyl_lo], 0); 552 if (cl != 0x01) { 553 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 554 "got 0x%x != 0x01\n", 555 device_xname(chp->ch_atac->atac_dev), 556 chp->ch_channel, cl), 557 DEBUG_PROBE); 558 ret_value &= ~0x01; 559 } 560 bus_space_write_1(wdr->cmd_iot, 561 wdr->cmd_iohs[wd_sector], 0, 0x01); 562 cl = bus_space_read_1(wdr->cmd_iot, 563 wdr->cmd_iohs[wd_sector], 0); 564 if (cl != 0x01) { 565 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 566 "got 0x%x != 0x01\n", 567 device_xname(chp->ch_atac->atac_dev), 568 chp->ch_channel, cl), 569 DEBUG_PROBE); 570 ret_value &= ~0x01; 571 } 572 bus_space_write_1(wdr->cmd_iot, 573 wdr->cmd_iohs[wd_sector], 0, 0x02); 574 cl = bus_space_read_1(wdr->cmd_iot, 575 wdr->cmd_iohs[wd_sector], 0); 576 if (cl != 0x02) { 577 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 578 "got 0x%x != 0x02\n", 579 device_xname(chp->ch_atac->atac_dev), 580 chp->ch_channel, cl), 581 DEBUG_PROBE); 582 ret_value &= ~0x01; 583 } 584 cl = bus_space_read_1(wdr->cmd_iot, 585 wdr->cmd_iohs[wd_cyl_lo], 0); 586 if (cl != 0x01) { 587 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 588 "got 0x%x != 0x01\n", 589 device_xname(chp->ch_atac->atac_dev), 590 chp->ch_channel, cl), 591 DEBUG_PROBE); 592 ret_value &= ~0x01; 593 } 594 } 595 /* Register writability test, drive 1. */ 596 if (ret_value & 0x02) { 597 if (wdc->select) 598 wdc->select(chp,1); 599 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 600 0, WDSD_IBM | 0x10); 601 bus_space_write_1(wdr->cmd_iot, 602 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 603 cl = bus_space_read_1(wdr->cmd_iot, 604 wdr->cmd_iohs[wd_cyl_lo], 0); 605 if (cl != 0x02) { 606 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 607 "got 0x%x != 0x02\n", 608 device_xname(chp->ch_atac->atac_dev), 609 chp->ch_channel, cl), 610 DEBUG_PROBE); 611 ret_value &= ~0x02; 612 } 613 bus_space_write_1(wdr->cmd_iot, 614 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 615 cl = bus_space_read_1(wdr->cmd_iot, 616 wdr->cmd_iohs[wd_cyl_lo], 0); 617 if (cl != 0x01) { 618 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 619 "got 0x%x != 0x01\n", 620 device_xname(chp->ch_atac->atac_dev), 621 chp->ch_channel, cl), 622 DEBUG_PROBE); 623 ret_value &= ~0x02; 624 } 625 bus_space_write_1(wdr->cmd_iot, 626 wdr->cmd_iohs[wd_sector], 0, 0x01); 627 cl = bus_space_read_1(wdr->cmd_iot, 628 wdr->cmd_iohs[wd_sector], 0); 629 if (cl != 0x01) { 630 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 631 "got 0x%x != 0x01\n", 632 device_xname(chp->ch_atac->atac_dev), 633 chp->ch_channel, cl), 634 DEBUG_PROBE); 635 ret_value &= ~0x02; 636 } 637 bus_space_write_1(wdr->cmd_iot, 638 wdr->cmd_iohs[wd_sector], 0, 0x02); 639 cl = bus_space_read_1(wdr->cmd_iot, 640 wdr->cmd_iohs[wd_sector], 0); 641 if (cl != 0x02) { 642 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 643 "got 0x%x != 0x02\n", 644 device_xname(chp->ch_atac->atac_dev), 645 chp->ch_channel, cl), 646 DEBUG_PROBE); 647 ret_value &= ~0x02; 648 } 649 cl = bus_space_read_1(wdr->cmd_iot, 650 wdr->cmd_iohs[wd_cyl_lo], 0); 651 if (cl != 0x01) { 652 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 653 "got 0x%x != 0x01\n", 654 device_xname(chp->ch_atac->atac_dev), 655 chp->ch_channel, cl), 656 DEBUG_PROBE); 657 ret_value &= ~0x02; 658 } 659 } 660 661 if (ret_value == 0) { 662 splx(s); 663 return 0; 664 } 665 } 666 667 668 #if 0 /* XXX this break some ATA or ATAPI devices */ 669 /* 670 * reset bus. Also send an ATAPI_RESET to devices, in case there are 671 * ATAPI device out there which don't react to the bus reset 672 */ 673 if (ret_value & 0x01) { 674 if (wdc->select) 675 wdc->select(chp,0); 676 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 677 0, WDSD_IBM); 678 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 679 ATAPI_SOFT_RESET); 680 } 681 if (ret_value & 0x02) { 682 if (wdc->select) 683 wdc->select(chp,0); 684 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 685 0, WDSD_IBM | 0x10); 686 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 687 ATAPI_SOFT_RESET); 688 } 689 690 delay(5000); 691 #endif 692 693 wdc->reset(chp, RESET_POLL); 694 DELAY(2000); 695 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 696 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 697 splx(s); 698 699 ret_value = __wdcwait_reset(chp, ret_value, poll); 700 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 701 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 702 ret_value), DEBUG_PROBE); 703 704 /* if reset failed, there's nothing here */ 705 if (ret_value == 0) 706 return 0; 707 708 /* 709 * Test presence of drives. First test register signatures looking 710 * for ATAPI devices. If it's not an ATAPI and reset said there may 711 * be something here assume it's ATA or OLD. Ghost will be killed 712 * later in attach routine. 713 */ 714 for (drive = 0; drive < chp->ch_ndrive; drive++) { 715 if ((ret_value & (0x01 << drive)) == 0) 716 continue; 717 if (wdc->select) 718 wdc->select(chp,drive); 719 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 720 WDSD_IBM | (drive << 4)); 721 delay(10); /* 400ns delay */ 722 /* Save registers contents */ 723 sc = bus_space_read_1(wdr->cmd_iot, 724 wdr->cmd_iohs[wd_seccnt], 0); 725 sn = bus_space_read_1(wdr->cmd_iot, 726 wdr->cmd_iohs[wd_sector], 0); 727 cl = bus_space_read_1(wdr->cmd_iot, 728 wdr->cmd_iohs[wd_cyl_lo], 0); 729 ch = bus_space_read_1(wdr->cmd_iot, 730 wdr->cmd_iohs[wd_cyl_hi], 0); 731 732 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 733 "cl=0x%x ch=0x%x\n", 734 device_xname(chp->ch_atac->atac_dev), 735 chp->ch_channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 736 /* 737 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 738 * we get wrong values here, so ignore it. 739 */ 740 s = splbio(); 741 if (cl == 0x14 && ch == 0xeb) { 742 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 743 } else { 744 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 745 if ((wdc->cap & WDC_CAPABILITY_PREATA) != 0) 746 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 747 } 748 splx(s); 749 } 750 return (ret_value); 751 } 752 753 void 754 wdcattach(struct ata_channel *chp) 755 { 756 struct atac_softc *atac = chp->ch_atac; 757 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 758 759 KASSERT(chp->ch_ndrive > 0 && chp->ch_ndrive < 3); 760 761 /* default data transfer methods */ 762 if (wdc->datain_pio == NULL) 763 wdc->datain_pio = wdc_datain_pio; 764 if (wdc->dataout_pio == NULL) 765 wdc->dataout_pio = wdc_dataout_pio; 766 /* default reset method */ 767 if (wdc->reset == NULL) 768 wdc->reset = wdc_do_reset; 769 770 /* initialise global data */ 771 if (atac->atac_bustype_ata == NULL) 772 atac->atac_bustype_ata = &wdc_ata_bustype; 773 if (atac->atac_probe == NULL) 774 atac->atac_probe = wdc_drvprobe; 775 #if NATAPIBUS > 0 776 if (atac->atac_atapibus_attach == NULL) 777 atac->atac_atapibus_attach = wdc_atapibus_attach; 778 #endif 779 780 ata_channel_attach(chp); 781 } 782 783 int 784 wdcactivate(device_t self, enum devact act) 785 { 786 struct atac_softc *atac = device_private(self); 787 struct ata_channel *chp; 788 int s, i, error = 0; 789 790 s = splbio(); 791 switch (act) { 792 case DVACT_ACTIVATE: 793 error = EOPNOTSUPP; 794 break; 795 796 case DVACT_DEACTIVATE: 797 for (i = 0; i < atac->atac_nchannels; i++) { 798 chp = atac->atac_channels[i]; 799 if (chp->atabus == NULL) 800 continue; 801 error = config_deactivate(chp->atabus); 802 if (error) 803 break; 804 } 805 break; 806 } 807 splx(s); 808 return (error); 809 } 810 811 void 812 wdc_childdetached(device_t self, device_t child) 813 { 814 struct atac_softc *atac = device_private(self); 815 struct ata_channel *chp; 816 int i; 817 818 for (i = 0; i < atac->atac_nchannels; i++) { 819 chp = atac->atac_channels[i]; 820 if (child == chp->atabus) { 821 chp->atabus = NULL; 822 return; 823 } 824 } 825 } 826 827 int 828 wdcdetach(device_t self, int flags) 829 { 830 struct atac_softc *atac = device_private(self); 831 struct ata_channel *chp; 832 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 833 int i, error = 0; 834 835 for (i = 0; i < atac->atac_nchannels; i++) { 836 chp = atac->atac_channels[i]; 837 if (chp->atabus == NULL) 838 continue; 839 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 840 device_xname(atac->atac_dev), device_xname(chp->atabus)), 841 DEBUG_DETACH); 842 if ((error = config_detach(chp->atabus, flags)) != 0) 843 return error; 844 } 845 if (adapt->adapt_refcnt != 0) 846 return EBUSY; 847 return 0; 848 } 849 850 /* restart an interrupted I/O */ 851 void 852 wdcrestart(void *v) 853 { 854 struct ata_channel *chp = v; 855 int s; 856 857 s = splbio(); 858 atastart(chp); 859 splx(s); 860 } 861 862 863 /* 864 * Interrupt routine for the controller. Acknowledge the interrupt, check for 865 * errors on the current operation, mark it done if necessary, and start the 866 * next request. Also check for a partially done transfer, and continue with 867 * the next chunk if so. 868 */ 869 int 870 wdcintr(void *arg) 871 { 872 struct ata_channel *chp = arg; 873 struct atac_softc *atac = chp->ch_atac; 874 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 875 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 876 struct ata_xfer *xfer; 877 int ret; 878 879 if (!device_is_active(atac->atac_dev)) { 880 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 881 DEBUG_INTR); 882 return (0); 883 } 884 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 885 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 886 /* try to clear the pending interrupt anyway */ 887 (void)bus_space_read_1(wdr->cmd_iot, 888 wdr->cmd_iohs[wd_status], 0); 889 return (0); 890 } 891 892 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 893 xfer = chp->ch_queue->active_xfer; 894 #ifdef DIAGNOSTIC 895 if (xfer == NULL) 896 panic("wdcintr: no xfer"); 897 if (xfer->c_chp != chp) { 898 printf("channel %d expected %d\n", xfer->c_chp->ch_channel, 899 chp->ch_channel); 900 panic("wdcintr: wrong channel"); 901 } 902 #endif 903 #if NATA_DMA || NATA_PIOBM 904 if (chp->ch_flags & ATACH_DMA_WAIT) { 905 wdc->dma_status = 906 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 907 xfer->c_drive, WDC_DMAEND_END); 908 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 909 /* IRQ not for us, not detected by DMA engine */ 910 return 0; 911 } 912 chp->ch_flags &= ~ATACH_DMA_WAIT; 913 } 914 #endif 915 chp->ch_flags &= ~ATACH_IRQ_WAIT; 916 ret = xfer->c_intr(chp, xfer, 1); 917 if (ret == 0) /* irq was not for us, still waiting for irq */ 918 chp->ch_flags |= ATACH_IRQ_WAIT; 919 return (ret); 920 } 921 922 /* Put all disk in RESET state */ 923 void 924 wdc_reset_drive(struct ata_drive_datas *drvp, int flags) 925 { 926 struct ata_channel *chp = drvp->chnl_softc; 927 928 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 929 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 930 drvp->drive), DEBUG_FUNCS); 931 932 ata_reset_channel(chp, flags); 933 } 934 935 void 936 wdc_reset_channel(struct ata_channel *chp, int flags) 937 { 938 TAILQ_HEAD(, ata_xfer) reset_xfer; 939 struct ata_xfer *xfer, *next_xfer; 940 #if NATA_DMA || NATA_PIOBM 941 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 942 #endif 943 944 TAILQ_INIT(&reset_xfer); 945 946 chp->ch_flags &= ~ATACH_IRQ_WAIT; 947 948 /* 949 * if the current command if on an ATAPI device, issue a 950 * ATAPI_SOFT_RESET 951 */ 952 xfer = chp->ch_queue->active_xfer; 953 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 954 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 955 if (flags & AT_WAIT) 956 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 957 else 958 delay(1000); 959 } 960 961 /* reset the channel */ 962 if (flags & AT_WAIT) 963 (void) wdcreset(chp, RESET_SLEEP); 964 else 965 (void) wdcreset(chp, RESET_POLL); 966 967 /* 968 * wait a bit after reset; in case the DMA engines needs some time 969 * to recover. 970 */ 971 if (flags & AT_WAIT) 972 tsleep(&flags, PRIBIO, "atardl", mstohz(1) + 1); 973 else 974 delay(1000); 975 /* 976 * look for pending xfers. If we have a shared queue, we'll also reset 977 * the other channel if the current xfer is running on it. 978 * Then we'll dequeue only the xfers for this channel. 979 */ 980 if ((flags & AT_RST_NOCMD) == 0) { 981 /* 982 * move all xfers queued for this channel to the reset queue, 983 * and then process the current xfer and then the reset queue. 984 * We have to use a temporary queue because c_kill_xfer() 985 * may requeue commands. 986 */ 987 for (xfer = TAILQ_FIRST(&chp->ch_queue->queue_xfer); 988 xfer != NULL; xfer = next_xfer) { 989 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 990 if (xfer->c_chp != chp) 991 continue; 992 TAILQ_REMOVE(&chp->ch_queue->queue_xfer, 993 xfer, c_xferchain); 994 TAILQ_INSERT_TAIL(&reset_xfer, xfer, c_xferchain); 995 } 996 xfer = chp->ch_queue->active_xfer; 997 if (xfer) { 998 if (xfer->c_chp != chp) 999 ata_reset_channel(xfer->c_chp, flags); 1000 else { 1001 callout_stop(&chp->ch_callout); 1002 #if NATA_DMA || NATA_PIOBM 1003 /* 1004 * If we're waiting for DMA, stop the 1005 * DMA engine 1006 */ 1007 if (chp->ch_flags & ATACH_DMA_WAIT) { 1008 (*wdc->dma_finish)( 1009 wdc->dma_arg, 1010 chp->ch_channel, 1011 xfer->c_drive, 1012 WDC_DMAEND_ABRT_QUIET); 1013 chp->ch_flags &= ~ATACH_DMA_WAIT; 1014 } 1015 #endif 1016 chp->ch_queue->active_xfer = NULL; 1017 if ((flags & AT_RST_EMERG) == 0) 1018 xfer->c_kill_xfer( 1019 chp, xfer, KILL_RESET); 1020 } 1021 } 1022 1023 for (xfer = TAILQ_FIRST(&reset_xfer); 1024 xfer != NULL; xfer = next_xfer) { 1025 next_xfer = TAILQ_NEXT(xfer, c_xferchain); 1026 TAILQ_REMOVE(&reset_xfer, xfer, c_xferchain); 1027 if ((flags & AT_RST_EMERG) == 0) 1028 xfer->c_kill_xfer(chp, xfer, KILL_RESET); 1029 } 1030 } 1031 } 1032 1033 static int 1034 wdcreset(struct ata_channel *chp, int poll) 1035 { 1036 struct atac_softc *atac = chp->ch_atac; 1037 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1038 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1039 int drv_mask1, drv_mask2; 1040 1041 wdc->reset(chp, poll); 1042 1043 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 1044 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 1045 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1046 (poll == RESET_SLEEP) ? 0 : 1); 1047 if (drv_mask2 != drv_mask1) { 1048 aprint_error("%s channel %d: reset failed for", 1049 device_xname(atac->atac_dev), chp->ch_channel); 1050 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1051 aprint_normal(" drive 0"); 1052 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1053 aprint_normal(" drive 1"); 1054 aprint_normal("\n"); 1055 } 1056 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 1057 return (drv_mask1 != drv_mask2) ? 1 : 0; 1058 } 1059 1060 void 1061 wdc_do_reset(struct ata_channel *chp, int poll) 1062 { 1063 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1064 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1065 int s = 0; 1066 1067 if (poll != RESET_SLEEP) 1068 s = splbio(); 1069 if (wdc->select) 1070 wdc->select(chp,0); 1071 /* master */ 1072 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1073 delay(10); /* 400ns delay */ 1074 /* assert SRST, wait for reset to complete */ 1075 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1076 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1077 delay(2000); 1078 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1079 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1080 WDCTL_4BIT | WDCTL_IDS); 1081 delay(10); /* 400ns delay */ 1082 if (poll != RESET_SLEEP) { 1083 /* ACK interrupt in case there is one pending left */ 1084 if (wdc->irqack) 1085 wdc->irqack(chp); 1086 splx(s); 1087 } 1088 } 1089 1090 static int 1091 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1092 { 1093 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1094 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1095 int timeout, nloop; 1096 u_int8_t st0 = 0, st1 = 0; 1097 #ifdef ATADEBUG 1098 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1099 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1100 #endif 1101 1102 if (poll) 1103 nloop = WDCNDELAY_RST; 1104 else 1105 nloop = WDC_RESET_WAIT * hz / 1000; 1106 /* wait for BSY to deassert */ 1107 for (timeout = 0; timeout < nloop; timeout++) { 1108 if ((drv_mask & 0x01) != 0) { 1109 if (wdc->select) 1110 wdc->select(chp,0); 1111 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1112 0, WDSD_IBM); /* master */ 1113 delay(10); 1114 st0 = bus_space_read_1(wdr->cmd_iot, 1115 wdr->cmd_iohs[wd_status], 0); 1116 #ifdef ATADEBUG 1117 sc0 = bus_space_read_1(wdr->cmd_iot, 1118 wdr->cmd_iohs[wd_seccnt], 0); 1119 sn0 = bus_space_read_1(wdr->cmd_iot, 1120 wdr->cmd_iohs[wd_sector], 0); 1121 cl0 = bus_space_read_1(wdr->cmd_iot, 1122 wdr->cmd_iohs[wd_cyl_lo], 0); 1123 ch0 = bus_space_read_1(wdr->cmd_iot, 1124 wdr->cmd_iohs[wd_cyl_hi], 0); 1125 #endif 1126 } 1127 if ((drv_mask & 0x02) != 0) { 1128 if (wdc->select) 1129 wdc->select(chp,1); 1130 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1131 0, WDSD_IBM | 0x10); /* slave */ 1132 delay(10); 1133 st1 = bus_space_read_1(wdr->cmd_iot, 1134 wdr->cmd_iohs[wd_status], 0); 1135 #ifdef ATADEBUG 1136 sc1 = bus_space_read_1(wdr->cmd_iot, 1137 wdr->cmd_iohs[wd_seccnt], 0); 1138 sn1 = bus_space_read_1(wdr->cmd_iot, 1139 wdr->cmd_iohs[wd_sector], 0); 1140 cl1 = bus_space_read_1(wdr->cmd_iot, 1141 wdr->cmd_iohs[wd_cyl_lo], 0); 1142 ch1 = bus_space_read_1(wdr->cmd_iot, 1143 wdr->cmd_iohs[wd_cyl_hi], 0); 1144 #endif 1145 } 1146 1147 if ((drv_mask & 0x01) == 0) { 1148 /* no master */ 1149 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1150 /* No master, slave is ready, it's done */ 1151 goto end; 1152 } 1153 if ((drv_mask & 0x02) == 0) { 1154 /* No master, no slave: it's done */ 1155 goto end; 1156 } 1157 } else if ((drv_mask & 0x02) == 0) { 1158 /* no slave */ 1159 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1160 /* No slave, master is ready, it's done */ 1161 goto end; 1162 } 1163 } else { 1164 /* Wait for both master and slave to be ready */ 1165 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1166 goto end; 1167 } 1168 } 1169 if (poll) 1170 delay(WDCDELAY); 1171 else 1172 tsleep(&nloop, PRIBIO, "atarst", 1); 1173 } 1174 /* Reset timed out. Maybe it's because drv_mask was not right */ 1175 if (st0 & WDCS_BSY) 1176 drv_mask &= ~0x01; 1177 if (st1 & WDCS_BSY) 1178 drv_mask &= ~0x02; 1179 end: 1180 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1181 "cl=0x%x ch=0x%x\n", 1182 device_xname(chp->ch_atac->atac_dev), 1183 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1184 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1185 "cl=0x%x ch=0x%x\n", 1186 device_xname(chp->ch_atac->atac_dev), 1187 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1188 1189 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1190 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1191 st0, st1), DEBUG_PROBE); 1192 1193 return drv_mask; 1194 } 1195 1196 /* 1197 * Wait for a drive to be !BSY, and have mask in its status register. 1198 * return -1 for a timeout after "timeout" ms. 1199 */ 1200 static int 1201 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout) 1202 { 1203 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1204 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1205 u_char status; 1206 int xtime = 0; 1207 1208 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1209 device_xname(chp->ch_atac->atac_dev), 1210 chp->ch_channel), DEBUG_STATUS); 1211 chp->ch_error = 0; 1212 1213 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1214 1215 for (;;) { 1216 chp->ch_status = status = 1217 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1218 if ((status & (WDCS_BSY | mask)) == bits) 1219 break; 1220 if (++xtime > timeout) { 1221 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1222 "status %x error %x (mask 0x%x bits 0x%x)\n", 1223 xtime, status, 1224 bus_space_read_1(wdr->cmd_iot, 1225 wdr->cmd_iohs[wd_error], 0), mask, bits), 1226 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1227 return(WDCWAIT_TOUT); 1228 } 1229 delay(WDCDELAY); 1230 } 1231 #ifdef ATADEBUG 1232 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1233 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1234 #endif 1235 if (status & WDCS_ERR) 1236 chp->ch_error = bus_space_read_1(wdr->cmd_iot, 1237 wdr->cmd_iohs[wd_error], 0); 1238 #ifdef WDCNDELAY_DEBUG 1239 /* After autoconfig, there should be no long delays. */ 1240 if (!cold && xtime > WDCNDELAY_DEBUG) { 1241 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1242 if (xfer == NULL) 1243 printf("%s channel %d: warning: busy-wait took %dus\n", 1244 device_xname(chp->ch_atac->atac_dev), 1245 chp->ch_channel, WDCDELAY * xtime); 1246 else 1247 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1248 device_xname(chp->ch_atac->atac_dev), 1249 chp->ch_channel, xfer->c_drive, 1250 WDCDELAY * xtime); 1251 } 1252 #endif 1253 return(WDCWAIT_OK); 1254 } 1255 1256 /* 1257 * Call __wdcwait(), polling using tsleep() or waking up the kernel 1258 * thread if possible 1259 */ 1260 int 1261 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags) 1262 { 1263 int error, i, timeout_hz = mstohz(timeout); 1264 1265 if (timeout_hz == 0 || 1266 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1267 error = __wdcwait(chp, mask, bits, timeout); 1268 else { 1269 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL); 1270 if (error != 0) { 1271 if ((chp->ch_flags & ATACH_TH_RUN) || 1272 (flags & AT_WAIT)) { 1273 /* 1274 * we're running in the channel thread 1275 * or some userland thread context 1276 */ 1277 for (i = 0; i < timeout_hz; i++) { 1278 if (__wdcwait(chp, mask, bits, 1279 WDCDELAY_POLL) == 0) { 1280 error = 0; 1281 break; 1282 } 1283 tsleep(&chp, PRIBIO, "atapoll", 1); 1284 } 1285 } else { 1286 /* 1287 * we're probably in interrupt context, 1288 * ask the thread to come back here 1289 */ 1290 #ifdef DIAGNOSTIC 1291 if (chp->ch_queue->queue_freeze > 0) 1292 panic("wdcwait: queue_freeze"); 1293 #endif 1294 chp->ch_queue->queue_freeze++; 1295 wakeup(&chp->ch_thread); 1296 return(WDCWAIT_THR); 1297 } 1298 } 1299 } 1300 return (error); 1301 } 1302 1303 1304 #if NATA_DMA 1305 /* 1306 * Busy-wait for DMA to complete 1307 */ 1308 int 1309 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1310 { 1311 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1312 int xtime; 1313 1314 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1315 wdc->dma_status = 1316 (*wdc->dma_finish)(wdc->dma_arg, 1317 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1318 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1319 return 0; 1320 delay(WDCDELAY); 1321 } 1322 /* timeout, force a DMA halt */ 1323 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1324 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1325 return 1; 1326 } 1327 #endif 1328 1329 void 1330 wdctimeout(void *arg) 1331 { 1332 struct ata_channel *chp = (struct ata_channel *)arg; 1333 #if NATA_DMA || NATA_PIOBM 1334 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1335 #endif 1336 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1337 int s; 1338 1339 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1340 1341 s = splbio(); 1342 if ((chp->ch_flags & ATACH_IRQ_WAIT) != 0) { 1343 __wdcerror(chp, "lost interrupt"); 1344 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1345 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1346 xfer->c_bcount, 1347 xfer->c_skip); 1348 #if NATA_DMA || NATA_PIOBM 1349 if (chp->ch_flags & ATACH_DMA_WAIT) { 1350 wdc->dma_status = 1351 (*wdc->dma_finish)(wdc->dma_arg, 1352 chp->ch_channel, xfer->c_drive, 1353 WDC_DMAEND_ABRT); 1354 chp->ch_flags &= ~ATACH_DMA_WAIT; 1355 } 1356 #endif 1357 /* 1358 * Call the interrupt routine. If we just missed an interrupt, 1359 * it will do what's needed. Else, it will take the needed 1360 * action (reset the device). 1361 * Before that we need to reinstall the timeout callback, 1362 * in case it will miss another irq while in this transfer 1363 * We arbitray chose it to be 1s 1364 */ 1365 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 1366 xfer->c_flags |= C_TIMEOU; 1367 chp->ch_flags &= ~ATACH_IRQ_WAIT; 1368 xfer->c_intr(chp, xfer, 1); 1369 } else 1370 __wdcerror(chp, "missing untimeout"); 1371 splx(s); 1372 } 1373 1374 int 1375 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_command *ata_c) 1376 { 1377 struct ata_channel *chp = drvp->chnl_softc; 1378 struct ata_xfer *xfer; 1379 int s, ret; 1380 1381 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1382 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1383 drvp->drive), DEBUG_FUNCS); 1384 1385 /* set up an xfer and queue. Wait for completion */ 1386 xfer = ata_get_xfer(ata_c->flags & AT_WAIT ? ATAXF_CANSLEEP : 1387 ATAXF_NOSLEEP); 1388 if (xfer == NULL) { 1389 return ATACMD_TRY_AGAIN; 1390 } 1391 1392 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1393 ata_c->flags |= AT_POLL; 1394 if (ata_c->flags & AT_POLL) 1395 xfer->c_flags |= C_POLL; 1396 if (ata_c->flags & AT_WAIT) 1397 xfer->c_flags |= C_WAIT; 1398 xfer->c_drive = drvp->drive; 1399 xfer->c_databuf = ata_c->data; 1400 xfer->c_bcount = ata_c->bcount; 1401 xfer->c_cmd = ata_c; 1402 xfer->c_start = __wdccommand_start; 1403 xfer->c_intr = __wdccommand_intr; 1404 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1405 1406 s = splbio(); 1407 ata_exec_xfer(chp, xfer); 1408 #ifdef DIAGNOSTIC 1409 if ((ata_c->flags & AT_POLL) != 0 && 1410 (ata_c->flags & AT_DONE) == 0) 1411 panic("wdc_exec_command: polled command not done"); 1412 #endif 1413 if (ata_c->flags & AT_DONE) { 1414 ret = ATACMD_COMPLETE; 1415 } else { 1416 if (ata_c->flags & AT_WAIT) { 1417 while ((ata_c->flags & AT_DONE) == 0) { 1418 tsleep(ata_c, PRIBIO, "wdccmd", 0); 1419 } 1420 ret = ATACMD_COMPLETE; 1421 } else { 1422 ret = ATACMD_QUEUED; 1423 } 1424 } 1425 splx(s); 1426 return ret; 1427 } 1428 1429 static void 1430 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1431 { 1432 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1433 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1434 int drive = xfer->c_drive; 1435 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1436 struct ata_command *ata_c = xfer->c_cmd; 1437 1438 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1439 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1440 xfer->c_drive), 1441 DEBUG_FUNCS); 1442 1443 if (wdc->select) 1444 wdc->select(chp,drive); 1445 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1446 WDSD_IBM | (drive << 4)); 1447 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1448 ata_c->r_st_bmask, ata_c->timeout, wait_flags)) { 1449 case WDCWAIT_OK: 1450 break; 1451 case WDCWAIT_TOUT: 1452 ata_c->flags |= AT_TIMEOU; 1453 __wdccommand_done(chp, xfer); 1454 return; 1455 case WDCWAIT_THR: 1456 return; 1457 } 1458 if (ata_c->flags & AT_POLL) { 1459 /* polled command, disable interrupts */ 1460 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1461 WDCTL_4BIT | WDCTL_IDS); 1462 } 1463 wdccommand(chp, drive, ata_c->r_command, ata_c->r_cyl, ata_c->r_head, 1464 ata_c->r_sector, ata_c->r_count, ata_c->r_features); 1465 1466 if ((ata_c->flags & AT_POLL) == 0) { 1467 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1468 callout_reset(&chp->ch_callout, ata_c->timeout / 1000 * hz, 1469 wdctimeout, chp); 1470 return; 1471 } 1472 /* 1473 * Polled command. Wait for drive ready or drq. Done in intr(). 1474 * Wait for at last 400ns for status bit to be valid. 1475 */ 1476 delay(10); /* 400ns delay */ 1477 __wdccommand_intr(chp, xfer, 0); 1478 } 1479 1480 static int 1481 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1482 { 1483 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1484 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1485 struct ata_command *ata_c = xfer->c_cmd; 1486 int bcount = ata_c->bcount; 1487 char *data = ata_c->data; 1488 int wflags; 1489 int drive_flags; 1490 1491 if (ata_c->r_command == WDCC_IDENTIFY || 1492 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1493 /* 1494 * The IDENTIFY data has been designed as an array of 1495 * u_int16_t, so we can byteswap it on the fly. 1496 * Historically it's what we have always done so keeping it 1497 * here ensure binary backward compatibility. 1498 */ 1499 drive_flags = DRIVE_NOSTREAM | 1500 chp->ch_drive[xfer->c_drive].drive_flags; 1501 } else { 1502 /* 1503 * Other data structure are opaque and should be transfered 1504 * as is. 1505 */ 1506 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1507 } 1508 1509 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1510 /* both wait and poll, we can tsleep here */ 1511 wflags = AT_WAIT | AT_POLL; 1512 } else { 1513 wflags = AT_POLL; 1514 } 1515 1516 again: 1517 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1518 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1519 xfer->c_drive), DEBUG_INTR); 1520 /* 1521 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1522 * Reselect again, it doesn't hurt for others commands, and the time 1523 * penalty for the extra regiter write is acceptable, 1524 * wdc_exec_command() isn't called often (mosly for autoconfig) 1525 */ 1526 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1527 WDSD_IBM | (xfer->c_drive << 4)); 1528 if ((ata_c->flags & AT_XFDONE) != 0) { 1529 /* 1530 * We have completed a data xfer. The drive should now be 1531 * in its initial state 1532 */ 1533 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1534 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1535 wflags) == WDCWAIT_TOUT) { 1536 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1537 return 0; /* IRQ was not for us */ 1538 ata_c->flags |= AT_TIMEOU; 1539 } 1540 goto out; 1541 } 1542 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1543 (irq == 0) ? ata_c->timeout : 0, wflags) == WDCWAIT_TOUT) { 1544 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1545 return 0; /* IRQ was not for us */ 1546 ata_c->flags |= AT_TIMEOU; 1547 goto out; 1548 } 1549 if (wdc->irqack) 1550 wdc->irqack(chp); 1551 if (ata_c->flags & AT_READ) { 1552 if ((chp->ch_status & WDCS_DRQ) == 0) { 1553 ata_c->flags |= AT_TIMEOU; 1554 goto out; 1555 } 1556 wdc->datain_pio(chp, drive_flags, data, bcount); 1557 /* at this point the drive should be in its initial state */ 1558 ata_c->flags |= AT_XFDONE; 1559 /* 1560 * XXX checking the status register again here cause some 1561 * hardware to timeout. 1562 */ 1563 } else if (ata_c->flags & AT_WRITE) { 1564 if ((chp->ch_status & WDCS_DRQ) == 0) { 1565 ata_c->flags |= AT_TIMEOU; 1566 goto out; 1567 } 1568 wdc->dataout_pio(chp, drive_flags, data, bcount); 1569 ata_c->flags |= AT_XFDONE; 1570 if ((ata_c->flags & AT_POLL) == 0) { 1571 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1572 callout_reset(&chp->ch_callout, 1573 mstohz(ata_c->timeout), wdctimeout, chp); 1574 return 1; 1575 } else { 1576 goto again; 1577 } 1578 } 1579 out: 1580 __wdccommand_done(chp, xfer); 1581 return 1; 1582 } 1583 1584 static void 1585 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1586 { 1587 struct atac_softc *atac = chp->ch_atac; 1588 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1589 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1590 struct ata_command *ata_c = xfer->c_cmd; 1591 1592 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1593 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1594 ata_c->flags), DEBUG_FUNCS); 1595 1596 1597 if (chp->ch_status & WDCS_DWF) 1598 ata_c->flags |= AT_DF; 1599 if (chp->ch_status & WDCS_ERR) { 1600 ata_c->flags |= AT_ERROR; 1601 ata_c->r_error = chp->ch_error; 1602 } 1603 if ((ata_c->flags & AT_READREG) != 0 && 1604 device_is_active(atac->atac_dev) && 1605 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1606 ata_c->r_head = bus_space_read_1(wdr->cmd_iot, 1607 wdr->cmd_iohs[wd_sdh], 0); 1608 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1609 wdr->cmd_iohs[wd_seccnt], 0); 1610 ata_c->r_sector = bus_space_read_1(wdr->cmd_iot, 1611 wdr->cmd_iohs[wd_sector], 0); 1612 ata_c->r_cyl = bus_space_read_1(wdr->cmd_iot, 1613 wdr->cmd_iohs[wd_cyl_hi], 0) << 8; 1614 ata_c->r_cyl |= bus_space_read_1(wdr->cmd_iot, 1615 wdr->cmd_iohs[wd_cyl_lo], 0); 1616 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1617 wdr->cmd_iohs[wd_error], 0); 1618 ata_c->r_features = bus_space_read_1(wdr->cmd_iot, 1619 wdr->cmd_iohs[wd_features], 0); 1620 } 1621 callout_stop(&chp->ch_callout); 1622 chp->ch_queue->active_xfer = NULL; 1623 if (ata_c->flags & AT_POLL) { 1624 /* enable interrupts */ 1625 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1626 WDCTL_4BIT); 1627 delay(10); /* some drives need a little delay here */ 1628 } 1629 if (chp->ch_drive[xfer->c_drive].drive_flags & DRIVE_WAITDRAIN) { 1630 __wdccommand_kill_xfer(chp, xfer, KILL_GONE); 1631 chp->ch_drive[xfer->c_drive].drive_flags &= ~DRIVE_WAITDRAIN; 1632 wakeup(&chp->ch_queue->active_xfer); 1633 } else 1634 __wdccommand_done_end(chp, xfer); 1635 } 1636 1637 static void 1638 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1639 { 1640 struct ata_command *ata_c = xfer->c_cmd; 1641 1642 ata_c->flags |= AT_DONE; 1643 ata_free_xfer(chp, xfer); 1644 if (ata_c->flags & AT_WAIT) 1645 wakeup(ata_c); 1646 else if (ata_c->callback) 1647 ata_c->callback(ata_c->callback_arg); 1648 atastart(chp); 1649 return; 1650 } 1651 1652 static void 1653 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1654 int reason) 1655 { 1656 struct ata_command *ata_c = xfer->c_cmd; 1657 1658 switch (reason) { 1659 case KILL_GONE: 1660 ata_c->flags |= AT_GONE; 1661 break; 1662 case KILL_RESET: 1663 ata_c->flags |= AT_RESET; 1664 break; 1665 default: 1666 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1667 reason); 1668 panic("__wdccommand_kill_xfer"); 1669 } 1670 __wdccommand_done_end(chp, xfer); 1671 } 1672 1673 /* 1674 * Send a command. The drive should be ready. 1675 * Assumes interrupts are blocked. 1676 */ 1677 void 1678 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1679 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1680 u_int8_t features) 1681 { 1682 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1683 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1684 1685 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1686 "sector=%d count=%d features=%d\n", 1687 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1688 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1689 1690 if (wdc->select) 1691 wdc->select(chp,drive); 1692 1693 /* Select drive, head, and addressing mode. */ 1694 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1695 WDSD_IBM | (drive << 4) | head); 1696 /* Load parameters into the wd_features register. */ 1697 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1698 features); 1699 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1700 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1701 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1702 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1703 0, cylin >> 8); 1704 1705 /* Send command. */ 1706 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1707 return; 1708 } 1709 1710 /* 1711 * Send a 48-bit addressing command. The drive should be ready. 1712 * Assumes interrupts are blocked. 1713 */ 1714 void 1715 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1716 u_int64_t blkno, u_int16_t count) 1717 { 1718 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1719 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1720 1721 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%x blkno=%d " 1722 "count=%d\n", device_xname(chp->ch_atac->atac_dev), 1723 chp->ch_channel, drive, command, (u_int32_t) blkno, count), 1724 DEBUG_FUNCS); 1725 1726 if (wdc->select) 1727 wdc->select(chp,drive); 1728 1729 /* Select drive, head, and addressing mode. */ 1730 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1731 (drive << 4) | WDSD_LBA); 1732 1733 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1734 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1735 0); 1736 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1737 0, count); 1738 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1739 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1740 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1741 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1742 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1743 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1744 } else { 1745 /* previous */ 1746 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1747 0); 1748 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1749 0, count >> 8); 1750 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1751 0, blkno >> 24); 1752 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1753 0, blkno >> 32); 1754 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1755 0, blkno >> 40); 1756 1757 /* current */ 1758 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1759 0); 1760 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, 1761 count); 1762 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 0, 1763 blkno); 1764 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1765 0, blkno >> 8); 1766 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1767 0, blkno >> 16); 1768 } 1769 1770 /* Send command. */ 1771 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1772 return; 1773 } 1774 1775 /* 1776 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1777 * tested by the caller. 1778 */ 1779 void 1780 wdccommandshort(struct ata_channel *chp, int drive, int command) 1781 { 1782 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1783 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1784 1785 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1786 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1787 command), DEBUG_FUNCS); 1788 1789 if (wdc->select) 1790 wdc->select(chp,drive); 1791 1792 /* Select drive. */ 1793 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1794 WDSD_IBM | (drive << 4)); 1795 1796 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1797 } 1798 1799 static void 1800 __wdcerror(struct ata_channel *chp, const char *msg) 1801 { 1802 struct atac_softc *atac = chp->ch_atac; 1803 struct ata_xfer *xfer = chp->ch_queue->active_xfer; 1804 1805 if (xfer == NULL) 1806 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1807 chp->ch_channel, msg); 1808 else 1809 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1810 chp->ch_channel, xfer->c_drive, msg); 1811 } 1812 1813 /* 1814 * the bit bucket 1815 */ 1816 void 1817 wdcbit_bucket(struct ata_channel *chp, int size) 1818 { 1819 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1820 1821 for (; size >= 2; size -= 2) 1822 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1823 if (size) 1824 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1825 } 1826 1827 static void 1828 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1829 { 1830 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1831 1832 #ifndef __NO_STRICT_ALIGNMENT 1833 if ((uintptr_t)bf & 1) 1834 goto unaligned; 1835 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1836 goto unaligned; 1837 #endif 1838 1839 if (flags & DRIVE_NOSTREAM) { 1840 if (flags & DRIVE_CAP32) { 1841 bus_space_read_multi_4(wdr->data32iot, 1842 wdr->data32ioh, 0, bf, len >> 2); 1843 bf = (char *)bf + (len & ~3); 1844 len &= 3; 1845 } 1846 if (len) { 1847 bus_space_read_multi_2(wdr->cmd_iot, 1848 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1849 } 1850 } else { 1851 if (flags & DRIVE_CAP32) { 1852 bus_space_read_multi_stream_4(wdr->data32iot, 1853 wdr->data32ioh, 0, bf, len >> 2); 1854 bf = (char *)bf + (len & ~3); 1855 len &= 3; 1856 } 1857 if (len) { 1858 bus_space_read_multi_stream_2(wdr->cmd_iot, 1859 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1860 } 1861 } 1862 return; 1863 1864 #ifndef __NO_STRICT_ALIGNMENT 1865 unaligned: 1866 if (flags & DRIVE_NOSTREAM) { 1867 if (flags & DRIVE_CAP32) { 1868 while (len > 3) { 1869 uint32_t val; 1870 1871 val = bus_space_read_4(wdr->data32iot, 1872 wdr->data32ioh, 0); 1873 memcpy(bf, &val, 4); 1874 bf = (char *)bf + 4; 1875 len -= 4; 1876 } 1877 } 1878 while (len > 1) { 1879 uint16_t val; 1880 1881 val = bus_space_read_2(wdr->cmd_iot, 1882 wdr->cmd_iohs[wd_data], 0); 1883 memcpy(bf, &val, 2); 1884 bf = (char *)bf + 2; 1885 len -= 2; 1886 } 1887 } else { 1888 if (flags & DRIVE_CAP32) { 1889 while (len > 3) { 1890 uint32_t val; 1891 1892 val = bus_space_read_stream_4(wdr->data32iot, 1893 wdr->data32ioh, 0); 1894 memcpy(bf, &val, 4); 1895 bf = (char *)bf + 4; 1896 len -= 4; 1897 } 1898 } 1899 while (len > 1) { 1900 uint16_t val; 1901 1902 val = bus_space_read_stream_2(wdr->cmd_iot, 1903 wdr->cmd_iohs[wd_data], 0); 1904 memcpy(bf, &val, 2); 1905 bf = (char *)bf + 2; 1906 len -= 2; 1907 } 1908 } 1909 #endif 1910 } 1911 1912 static void 1913 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1914 { 1915 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1916 1917 #ifndef __NO_STRICT_ALIGNMENT 1918 if ((uintptr_t)bf & 1) 1919 goto unaligned; 1920 if ((flags & DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1921 goto unaligned; 1922 #endif 1923 1924 if (flags & DRIVE_NOSTREAM) { 1925 if (flags & DRIVE_CAP32) { 1926 bus_space_write_multi_4(wdr->data32iot, 1927 wdr->data32ioh, 0, bf, len >> 2); 1928 bf = (char *)bf + (len & ~3); 1929 len &= 3; 1930 } 1931 if (len) { 1932 bus_space_write_multi_2(wdr->cmd_iot, 1933 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1934 } 1935 } else { 1936 if (flags & DRIVE_CAP32) { 1937 bus_space_write_multi_stream_4(wdr->data32iot, 1938 wdr->data32ioh, 0, bf, len >> 2); 1939 bf = (char *)bf + (len & ~3); 1940 len &= 3; 1941 } 1942 if (len) { 1943 bus_space_write_multi_stream_2(wdr->cmd_iot, 1944 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1945 } 1946 } 1947 return; 1948 1949 #ifndef __NO_STRICT_ALIGNMENT 1950 unaligned: 1951 if (flags & DRIVE_NOSTREAM) { 1952 if (flags & DRIVE_CAP32) { 1953 while (len > 3) { 1954 uint32_t val; 1955 1956 memcpy(&val, bf, 4); 1957 bus_space_write_4(wdr->data32iot, 1958 wdr->data32ioh, 0, val); 1959 bf = (char *)bf + 4; 1960 len -= 4; 1961 } 1962 } 1963 while (len > 1) { 1964 uint16_t val; 1965 1966 memcpy(&val, bf, 2); 1967 bus_space_write_2(wdr->cmd_iot, 1968 wdr->cmd_iohs[wd_data], 0, val); 1969 bf = (char *)bf + 2; 1970 len -= 2; 1971 } 1972 } else { 1973 if (flags & DRIVE_CAP32) { 1974 while (len > 3) { 1975 uint32_t val; 1976 1977 memcpy(&val, bf, 4); 1978 bus_space_write_stream_4(wdr->data32iot, 1979 wdr->data32ioh, 0, val); 1980 bf = (char *)bf + 4; 1981 len -= 4; 1982 } 1983 } 1984 while (len > 1) { 1985 uint16_t val; 1986 1987 memcpy(&val, bf, 2); 1988 bus_space_write_stream_2(wdr->cmd_iot, 1989 wdr->cmd_iohs[wd_data], 0, val); 1990 bf = (char *)bf + 2; 1991 len -= 2; 1992 } 1993 } 1994 #endif 1995 }
Cache object: 2bbda58c2188062bd6e9ef964adff3b0
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