FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/wdcvar.h
1 /* $NetBSD: wdcvar.h,v 1.82.2.1 2005/08/18 20:02:40 tron Exp $ */
2
3 /*-
4 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #ifndef _DEV_IC_WDCVAR_H_
40 #define _DEV_IC_WDCVAR_H_
41
42 #include <sys/callout.h>
43
44 #include <dev/ic/wdcreg.h>
45
46 #define WAITTIME (10 * hz) /* time to wait for a completion */
47 /* this is a lot for hard drives, but not for cdroms */
48
49 #define WDC_NREG 8 /* number of command registers */
50 #define WDC_NSHADOWREG 2 /* number of command "shadow" registers */
51
52 struct wdc_regs {
53 /* Our registers */
54 bus_space_tag_t cmd_iot;
55 bus_space_handle_t cmd_baseioh;
56 bus_space_handle_t cmd_iohs[WDC_NREG+WDC_NSHADOWREG];
57 bus_space_tag_t ctl_iot;
58 bus_space_handle_t ctl_ioh;
59
60 /* data32{iot,ioh} are only used for 32-bit data xfers */
61 bus_space_tag_t data32iot;
62 bus_space_handle_t data32ioh;
63 };
64
65 /*
66 * Per-controller data
67 */
68 struct wdc_softc {
69 struct atac_softc sc_atac; /* generic ATA controller info */
70
71 struct wdc_regs *regs; /* register array (per-channel) */
72
73 int cap; /* controller capabilities */
74 #define WDC_CAPABILITY_NO_EXTRA_RESETS 0x0100 /* only reset once */
75 #define WDC_CAPABILITY_PREATA 0x0200 /* ctrl can be a pre-ata one */
76 #define WDC_CAPABILITY_WIDEREGS 0x0400 /* Ctrl has wide (16bit) registers */
77
78 /* if WDC_CAPABILITY_DMA set in 'cap' */
79 void *dma_arg;
80 int (*dma_init)(void *, int, int, void *, size_t, int);
81 void (*dma_start)(void *, int, int);
82 int (*dma_finish)(void *, int, int, int);
83 /* flags passed to dma_init */
84 #define WDC_DMA_READ 0x01
85 #define WDC_DMA_IRQW 0x02
86 #define WDC_DMA_LBA48 0x04
87
88 /* values passed to dma_finish */
89 #define WDC_DMAEND_END 0 /* check for proper end of a DMA xfer */
90 #define WDC_DMAEND_ABRT 1 /* abort a DMA xfer, verbose */
91 #define WDC_DMAEND_ABRT_QUIET 2 /* abort a DMA xfer, quiet */
92
93 int dma_status; /* status returned from dma_finish() */
94 #define WDC_DMAST_NOIRQ 0x01 /* missing IRQ */
95 #define WDC_DMAST_ERR 0x02 /* DMA error */
96 #define WDC_DMAST_UNDER 0x04 /* DMA underrun */
97
98 /* Optional callback to select drive. */
99 void (*select)(struct ata_channel *,int);
100
101 /* Optional callback to ack IRQ. */
102 void (*irqack)(struct ata_channel *);
103
104 /* Optional callback to perform a bus reset */
105 void (*reset)(struct ata_channel *, int);
106
107 /* overridden if the backend has a different data transfer method */
108 void (*datain_pio)(struct ata_channel *, int, void *, size_t);
109 void (*dataout_pio)(struct ata_channel *, int, void *, size_t);
110 };
111
112 /* Given an ata_channel, get the wdc_softc. */
113 #define CHAN_TO_WDC(chp) ((struct wdc_softc *)(chp)->ch_atac)
114
115 /* Given an ata_channel, get the wdc_regs. */
116 #define CHAN_TO_WDC_REGS(chp) (&CHAN_TO_WDC(chp)->regs[(chp)->ch_channel])
117
118 /*
119 * Public functions which can be called by ATA or ATAPI specific parts,
120 * or bus-specific backends.
121 */
122
123 void wdc_allocate_regs(struct wdc_softc *);
124 void wdc_init_shadow_regs(struct ata_channel *);
125
126 int wdcprobe(struct ata_channel *);
127 void wdcattach(struct ata_channel *);
128 int wdcdetach(struct device *, int);
129 int wdcactivate(struct device *, enum devact);
130 int wdcintr(void *);
131
132 void wdcrestart(void*);
133
134 int wdcwait(struct ata_channel *, int, int, int, int);
135 #define WDCWAIT_OK 0 /* we have what we asked */
136 #define WDCWAIT_TOUT -1 /* timed out */
137 #define WDCWAIT_THR 1 /* return, the kernel thread has been awakened */
138
139 void wdcbit_bucket(struct ata_channel *, int);
140
141 int wdc_dmawait(struct ata_channel *, struct ata_xfer *, int);
142 void wdccommand(struct ata_channel *, u_int8_t, u_int8_t, u_int16_t,
143 u_int8_t, u_int8_t, u_int8_t, u_int8_t);
144 void wdccommandext(struct ata_channel *, u_int8_t, u_int8_t, u_int64_t,
145 u_int16_t);
146 void wdccommandshort(struct ata_channel *, int, int);
147 void wdctimeout(void *arg);
148 void wdc_reset_drive(struct ata_drive_datas *, int);
149 void wdc_reset_channel(struct ata_channel *, int);
150 void wdc_do_reset(struct ata_channel *, int);
151
152 int wdc_exec_command(struct ata_drive_datas *, struct ata_command*);
153
154 /*
155 * ST506 spec says that if READY or SEEKCMPLT go off, then the read or write
156 * command is aborted.
157 */
158 #define wdc_wait_for_drq(chp, timeout, flags) \
159 wdcwait((chp), WDCS_DRQ, WDCS_DRQ, (timeout), (flags))
160 #define wdc_wait_for_unbusy(chp, timeout, flags) \
161 wdcwait((chp), 0, 0, (timeout), (flags))
162 #define wdc_wait_for_ready(chp, timeout, flags) \
163 wdcwait((chp), WDCS_DRDY, WDCS_DRDY, (timeout), (flags))
164
165 /* ATA/ATAPI specs says a device can take 31s to reset */
166 #define WDC_RESET_WAIT 31000
167
168 void wdc_atapibus_attach(struct atabus_softc *);
169
170 #endif /* _DEV_IC_WDCVAR_H_ */
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