The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ic/z8530.h

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    1 /*-
    2  * Copyright (c) 2003 Marcel Moolenaar
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  *
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   18  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   19  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   20  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   21  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   22  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   23  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   24  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   25  *
   26  * $FreeBSD: releng/9.0/sys/dev/ic/z8530.h 155967 2006-02-24 02:03:35Z marcel $
   27  */
   28 
   29 #ifndef _DEV_IC_Z8530_H_
   30 #define _DEV_IC_Z8530_H_
   31 
   32 /*
   33  * Channel B control:   0
   34  * Channel B data:      1
   35  * Channel A control:   2
   36  * Channel A data:      3
   37  */
   38 
   39 /* The following apply when using a device-scoped bus handle */
   40 #define CHAN_A          2
   41 #define CHAN_B          0
   42 
   43 #define REG_CTRL        0
   44 #define REG_DATA        1
   45 
   46 /* Write registers. */
   47 #define WR_CR           0       /* Command Register. */
   48 #define WR_IDT          1       /* Interrupt and Data Transfer Mode. */
   49 #define WR_IV           2       /* Interrupt Vector (shared). */
   50 #define WR_RPC          3       /* Receive Parameters and Control. */
   51 #define WR_MPM          4       /* Miscellaneous Parameters and Modes. */
   52 #define WR_TPC          5       /* Transmit Parameters and Control. */
   53 #define WR_SCAF         6       /* Sync Character or (SDLC) Address Field. */
   54 #define WR_SCF          7       /* Sync Character or (SDCL) Flag. */
   55 #define WR_EFC          7       /* Extended Feature and FIFO Control. */
   56 #define WR_TB           8       /* Transmit Buffer. */
   57 #define WR_MIC          9       /* Master Interrupt Control (shared). */
   58 #define WR_MCB1         10      /* Miscellaneous Control Bits (part 1 :-). */
   59 #define WR_CMC          11      /* Clock Mode Control. */
   60 #define WR_TCL          12      /* BRG Time Constant Low. */
   61 #define WR_TCH          13      /* BRG Time Constant High. */
   62 #define WR_MCB2         14      /* Miscellaneous Control Bits (part 2 :-). */
   63 #define WR_IC           15      /* Interrupt Control. */
   64 
   65 /* Read registers. */
   66 #define RR_BES          0       /* Buffer and External Status. */
   67 #define RR_SRC          1       /* Special Receive Condition. */
   68 #define RR_IV           2       /* Interrupt Vector. */
   69 #define RR_IP           3       /* Interrupt Pending (ch A only). */
   70 #define RR_MPM          4       /* Miscellaneous Parameters and Modes. */
   71 #define RR_TPC          5       /* Transmit Parameters and Control. */
   72 #define RR_BCL          6       /* Byte Count Low. */
   73 #define RR_BCH          7       /* Byte Count High. */
   74 #define RR_RB           8       /* Receive Buffer. */
   75 #define RR_RPC          9       /* Receive Parameters and Control. */
   76 #define RR_MSB          10      /* Miscellaneous Status Bits. */
   77 #define RR_MCB1         11      /* Miscellaneous Control Bits (part 1). */
   78 #define RR_TCL          12      /* BRG Time Constant Low. */
   79 #define RR_TCH          13      /* BRG Time Constant High. */
   80 #define RR_EFC          14      /* Extended Feature and FIFO Control. */
   81 #define RR_IC           15      /* Interrupt Control. */
   82 
   83 /* Buffer and External Status (RR0). */
   84 #define BES_BRK         0x80    /* Break (Abort). */
   85 #define BES_TXU         0x40    /* Tx Underrun (EOM). */
   86 #define BES_CTS         0x20    /* CTS. */
   87 #define BES_SYNC        0x10    /* Sync. */
   88 #define BES_DCD         0x08    /* DCD. */
   89 #define BES_TXE         0x04    /* Tx Empty. */
   90 #define BES_ZC          0x02    /* Zero Count. */
   91 #define BES_RXA         0x01    /* Rx Available. */
   92 
   93 /* Clock Mode Control (WR11). */
   94 #define CMC_XTAL        0x80    /* -RTxC connects to quartz crystal. */
   95 #define CMC_RC_DPLL     0x60    /* Rx Clock from DPLL. */
   96 #define CMC_RC_BRG      0x40    /* Rx Clock from BRG. */
   97 #define CMC_RC_TRXC     0x20    /* Rx Clock from -TRxC. */
   98 #define CMC_RC_RTXC     0x00    /* Rx Clock from -RTxC. */
   99 #define CMC_TC_DPLL     0x18    /* Tx Clock from DPLL */
  100 #define CMC_TC_BRG      0x10    /* Tx Clock from BRG */
  101 #define CMC_TC_TRXC     0x08    /* Tx Clock from -TRxC. */
  102 #define CMC_TC_RTXC     0x00    /* Tx Clock from -RTxC. */
  103 #define CMC_TRXC_OUT    0x04    /* -TRxC is output. */
  104 #define CMC_TRXC_DPLL   0x03    /* -TRxC from DPLL */
  105 #define CMC_TRXC_BRG    0x02    /* -TRxC from BRG */
  106 #define CMC_TRXC_XMIT   0x01    /* -TRxC from Tx clock. */
  107 #define CMC_TRXC_XTAL   0x00    /* -TRxC from XTAL. */
  108 
  109 /* Command Register (WR0). */
  110 #define CR_RSTTXU       0xc0    /* Reset Tx. Underrun/EOM. */
  111 #define CR_RSTTXCRC     0x80    /* Reset Tx. CRC. */
  112 #define CR_RSTRXCRC     0x40    /* Reset Rx. CRC. */
  113 #define CR_RSTIUS       0x38    /* Reset Int. Under Service. */
  114 #define CR_RSTERR       0x30    /* Error Reset. */
  115 #define CR_RSTTXI       0x28    /* Reset Tx. Int. */
  116 #define CR_ENARXI       0x20    /* Enable Rx. Int. */
  117 #define CR_ABORT        0x18    /* Send Abort. */
  118 #define CR_RSTXSI       0x10    /* Reset Ext/Status Int. */
  119 
  120 /* Extended Feature and FIFO Control (WR7 prime). */
  121 #define EFC_ERE         0x40    /* Extended Read Enable. */
  122 #define EFC_FE          0x20    /* Transmit FIFO Empty. */
  123 #define EFC_RQT         0x10    /* Request Timing. */
  124 #define EFC_FHF         0x08    /* Receive FIFO Half Full. */
  125 #define EFC_RTS         0x04    /* Auto RTS Deactivation. */
  126 #define EFC_EOM         0x02    /* Auto EOM Reset. */
  127 #define EFC_FLAG        0x01    /* Auto SDLC Flag on Tx. */
  128 
  129 /* Interrupt Control (WR15). */
  130 #define IC_BRK          0x80    /* Break (Abort) IE. */
  131 #define IC_TXU          0x40    /* Tx Underrun IE. */
  132 #define IC_CTS          0x20    /* CTS IE. */
  133 #define IC_SYNC         0x10    /* Sync IE. */
  134 #define IC_DCD          0x08    /* DCD IE. */
  135 #define IC_FIFO         0x04    /* SDLC FIFO Enable. */
  136 #define IC_ZC           0x02    /* Zero Count IE. */
  137 #define IC_EF           0x01    /* Extended Feature Enable. */
  138 
  139 /* Interrupt and Data Transfer Mode (WR1). */
  140 #define IDT_WRE         0x80    /* Wait/DMA Request Enable. */
  141 #define IDT_REQ         0x40    /* DMA Request. */
  142 #define IDT_WRR         0x20    /* Wait/DMA Reuest on Receive. */
  143 #define IDT_RISC        0x18    /* Rx Int. on Special Condition Only. */
  144 #define IDT_RIA         0x10    /* Rx Int. on All Characters. */
  145 #define IDT_RIF         0x08    /* Rx Int. on First Character. */
  146 #define IDT_PSC         0x04    /* Parity is Special Condition. */
  147 #define IDT_TIE         0x02    /* Tx Int. Enable. */
  148 #define IDT_XIE         0x01    /* Ext. Int. Enable. */
  149 
  150 /* Interrupt Pending (RR3). */
  151 #define IP_RIA          0x20    /* Rx. Int. ch. A. */
  152 #define IP_TIA          0x10    /* Tx. Int. ch. A. */ 
  153 #define IP_SIA          0x08    /* Ext/Status Int. ch. A. */
  154 #define IP_RIB          0x04    /* Rx. Int. ch. B. */
  155 #define IP_TIB          0x02    /* Tx. Int. ch. B. */
  156 #define IP_SIB          0x01    /* Ext/Status Int. ch. B. */
  157 
  158 /* Interrupt Vector Status Low (RR2). */
  159 #define IV_SCA          0x0e    /* Special Condition ch. A. */
  160 #define IV_RAA          0x0c    /* Receive Available ch. A. */
  161 #define IV_XSA          0x0a    /* External/Status Change ch. A. */
  162 #define IV_TEA          0x08    /* Transmitter Empty ch. A. */
  163 #define IV_SCB          0x06    /* Special Condition ch. B. */
  164 #define IV_RAB          0x04    /* Receive Available ch. B. */
  165 #define IV_XSB          0x02    /* External/Status Change ch. B. */
  166 #define IV_TEB          0x00    /* Transmitter Empty ch. B. */
  167 
  168 /* Miscellaneous Control Bits part 1 (WR10). */
  169 #define MCB1_CRC1       0x80    /* CRC presets to 1. */
  170 #define MCB1_FM0        0x60    /* FM0 Encoding. */
  171 #define MCB1_FM1        0x40    /* FM1 Encoding. */
  172 #define MCB1_NRZI       0x20    /* NRZI Encoding. */
  173 #define MCB1_NRZ        0x00    /* NRZ Encoding. */
  174 #define MCB1_AOP        0x10    /* Active On Poll. */
  175 #define MCB1_MI         0x08    /* Mark Idle. */
  176 #define MCB1_AOU        0x04    /* Abort On Underrun. */
  177 #define MCB1_LM         0x02    /* Loop Mode. */
  178 #define MCB1_SIX        0x01    /* 6 or 12 bit SYNC. */
  179 
  180 /* Miscellaneous Control Bits part 2 (WR14). */
  181 #define MCB2_NRZI       0xe0    /* DPLL - NRZI mode. */
  182 #define MCB2_FM         0xc0    /* DPLL - FM mode. */
  183 #define MCB2_RTXC       0xa0    /* DPLL - Clock from -RTxC. */
  184 #define MCB2_BRG        0x80    /* DPLL - Clock from BRG. */
  185 #define MCB2_OFF        0x60    /* DPLL - Disable. */
  186 #define MCB2_RMC        0x40    /* DPLL - Reset Missing Clock. */
  187 #define MCB2_ESM        0x20    /* DPLL - Enter Search Mode. */
  188 #define MCB2_LL         0x10    /* Local Loopback. */
  189 #define MCB2_AE         0x08    /* Auto Echo. */
  190 #define MCB2_REQ        0x04    /* Request Function. */
  191 #define MCB2_PCLK       0x02    /* BRG source is PCLK. */
  192 #define MCB2_BRGE       0x01    /* BRG enable. */
  193 
  194 /* Master Interrupt Control (WR9). */
  195 #define MIC_FHR         0xc0    /* Force Hardware Reset. */
  196 #define MIC_CRA         0x80    /* Channel Reset A. */
  197 #define MIC_CRB         0x40    /* Channel Reset B. */
  198 #define MIC_SIE         0x20    /* Software INTACK Enable. */
  199 #define MIC_SH          0x10    /* Status High. */
  200 #define MIC_MIE         0x08    /* Master Interrupt Enable. */
  201 #define MIC_DLC         0x04    /* Disable Lower Chain. */
  202 #define MIC_NV          0x02    /* No Vector. */
  203 #define MIC_VIS         0x01    /* Vector Includes Status. */
  204 
  205 /* Transmit/Receive Miscellaneous Parameters and Modes (WR4). */
  206 #define MPM_CM64        0xc0    /* X64 Clock Mode. */
  207 #define MPM_CM32        0x80    /* X32 Clock Mode. */
  208 #define MPM_CM16        0x40    /* X16 Clock Mode. */
  209 #define MPM_CM1         0x00    /* X1 Clock Mode. */
  210 #define MPM_EXT         0x30    /* External Sync Mode. */
  211 #define MPM_SDLC        0x20    /* SDLC mode. */
  212 #define MPM_BI          0x10    /* 16-bit Sync (bi-sync). */
  213 #define MPM_MONO        0x00    /* 8-bit Sync (mono-sync). */
  214 #define MPM_SB2         0x0c    /* Async mode: 2 stopbits. */
  215 #define MPM_SB15        0x08    /* Async mode: 1.5 stopbits. */
  216 #define MPM_SB1         0x04    /* Async mode: 1 stopbit. */
  217 #define MPM_SYNC        0x00    /* Sync Mode Enable. */
  218 #define MPM_EVEN        0x02    /* Async mode: even parity. */
  219 #define MPM_PE          0x01    /* Async mode: parity enable. */
  220 
  221 /* Receive Parameters and Control (WR3). */
  222 #define RPC_RB8         0xc0    /* 8 databits. */
  223 #define RPC_RB6         0x80    /* 6 databits. */
  224 #define RPC_RB7         0x40    /* 7 databits. */
  225 #define RPC_RB5         0x00    /* 5 databits. */
  226 #define RPC_AE          0x20    /* Auto Enable. */
  227 #define RPC_EHM         0x10    /* Enter Hunt Mode. */
  228 #define RPC_CRC         0x08    /* CRC Enable. */
  229 #define RPC_ASM         0x04    /* Address Search Mode. */
  230 #define RPC_LI          0x02    /* SYNC Character Load Inhibit */
  231 #define RPC_RXE         0x01    /* Receiver Enable */
  232 
  233 /* Special Receive Condition (RR1). */
  234 #define SRC_EOF         0x80    /* End Of Frame. */
  235 #define SRC_FE          0x40    /* Framing Error. */
  236 #define SRC_OVR         0x20    /* Rx. Overrun. */
  237 #define SRC_PE          0x10    /* Parity Error. */
  238 #define SRC_RC0         0x08    /* Residue Code 0. */
  239 #define SRC_RC1         0x04    /* Residue Code 1. */
  240 #define SRC_RC2         0x02    /* Residue Code 2. */
  241 #define SRC_AS          0x01    /* All Sent. */
  242 
  243 /* Transmit Parameter and Control (WR5). */
  244 #define TPC_DTR         0x80    /* DTR. */
  245 #define TPC_TB8         0x60    /* 8 databits. */
  246 #define TPC_TB6         0x40    /* 6 databits. */
  247 #define TPC_TB7         0x20    /* 7 databits. */
  248 #define TPC_TB5         0x00    /* 5 or fewer databits. */
  249 #define TPC_BRK         0x10    /* Send break. */
  250 #define TPC_TXE         0x08    /* Transmitter Enable. */
  251 #define TPC_CRC16       0x04    /* CRC16. */
  252 #define TPC_RTS         0x02    /* RTS. */
  253 #define TPC_CRC         0x01    /* CRC Enable. */
  254 
  255 #endif /* _DEV_IC_Z8530_H_ */

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