Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/dev/ice/virtchnl_lan_desc.h
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1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright (c) 2021, Intel Corporation 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * 3. Neither the name of the Intel Corporation nor the names of its 16 * contributors may be used to endorse or promote products derived from 17 * this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /*$FreeBSD$*/ 32 33 #ifndef _VIRTCHNL_LAN_DESC_H_ 34 #define _VIRTCHNL_LAN_DESC_H_ 35 36 /* Rx */ 37 /* For splitq virtchnl_rx_flex_desc_adv desc members */ 38 #define VIRTCHNL_RX_FLEX_DESC_ADV_RXDID_S 0 39 #define VIRTCHNL_RX_FLEX_DESC_ADV_RXDID_M \ 40 MAKEMASK(0xFUL, VIRTCHNL_RX_FLEX_DESC_ADV_RXDID_S) 41 #define VIRTCHNL_RX_FLEX_DESC_ADV_PTYPE_S 0 42 #define VIRTCHNL_RX_FLEX_DESC_ADV_PTYPE_M \ 43 MAKEMASK(0x3FFUL, VIRTCHNL_RX_FLEX_DESC_ADV_PTYPE_S) 44 #define VIRTCHNL_RX_FLEX_DESC_ADV_UMBCAST_S 10 45 #define VIRTCHNL_RX_FLEX_DESC_ADV_UMBCAST_M \ 46 MAKEMASK(0x3UL, VIRTCHNL_RX_FLEX_DESC_ADV_UMBCAST_S) 47 #define VIRTCHNL_RX_FLEX_DESC_ADV_FF0_S 12 48 #define VIRTCHNL_RX_FLEX_DESC_ADV_FF0_M \ 49 MAKEMASK(0xFUL, VIRTCHNL_RX_FLEX_DESC_ADV_FF0_S) 50 #define VIRTCHNL_RX_FLEX_DESC_ADV_LEN_PBUF_S 0 51 #define VIRTCHNL_RX_FLEX_DESC_ADV_LEN_PBUF_M \ 52 MAKEMASK(0x3FFFUL, VIRTCHNL_RX_FLEX_DESC_ADV_LEN_PBUF_S) 53 #define VIRTCHNL_RX_FLEX_DESC_ADV_GEN_S 14 54 #define VIRTCHNL_RX_FLEX_DESC_ADV_GEN_M \ 55 BIT_ULL(VIRTCHNL_RX_FLEX_DESC_ADV_GEN_S) 56 #define VIRTCHNL_RX_FLEX_DESC_ADV_BUFQ_ID_S 15 57 #define VIRTCHNL_RX_FLEX_DESC_ADV_BUFQ_ID_M \ 58 BIT_ULL(VIRTCHNL_RX_FLEX_DESC_ADV_BUFQ_ID_S) 59 #define VIRTCHNL_RX_FLEX_DESC_ADV_LEN_HDR_S 0 60 #define VIRTCHNL_RX_FLEX_DESC_ADV_LEN_HDR_M \ 61 MAKEMASK(0x3FFUL, VIRTCHNL_RX_FLEX_DESC_ADV_LEN_HDR_S) 62 #define VIRTCHNL_RX_FLEX_DESC_ADV_RSC_S 10 63 #define VIRTCHNL_RX_FLEX_DESC_ADV_RSC_M \ 64 BIT_ULL(VIRTCHNL_RX_FLEX_DESC_ADV_RSC_S) 65 #define VIRTCHNL_RX_FLEX_DESC_ADV_SPH_S 11 66 #define VIRTCHNL_RX_FLEX_DESC_ADV_SPH_M \ 67 BIT_ULL(VIRTCHNL_RX_FLEX_DESC_ADV_SPH_S) 68 #define VIRTCHNL_RX_FLEX_DESC_ADV_MISS_S 12 69 #define VIRTCHNL_RX_FLEX_DESC_ADV_MISS_M \ 70 BIT_ULL(VIRTCHNL_RX_FLEX_DESC_ADV_MISS_S) 71 #define VIRTCHNL_RX_FLEX_DESC_ADV_FF1_S 13 72 #define VIRTCHNL_RX_FLEX_DESC_ADV_FF1_M \ 73 MAKEMASK(0x7UL, VIRTCHNL_RX_FLEX_DESC_ADV_FF1_M) 74 75 enum virtchnl_rx_flex_desc_adv_status_error_0_qw1_bits { 76 /* Note: These are predefined bit offsets */ 77 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_DD_S = 0, 78 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_EOF_S, 79 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_HBO_S, 80 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_L3L4P_S, 81 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_XSUM_IPE_S, 82 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_XSUM_L4E_S, 83 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_XSUM_EIPE_S, 84 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_XSUM_EUDPE_S, 85 }; 86 87 enum virtchnl_rx_flex_desc_adv_status_error_0_qw0_bits { 88 /* Note: These are predefined bit offsets */ 89 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_LPBK_S = 0, 90 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_IPV6EXADD_S, 91 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_RXE_S, 92 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_CRCP_S, 93 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_RSS_VALID_S, 94 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_L2TAG1P_S, 95 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_XTRMD0_VALID_S, 96 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_XTRMD1_VALID_S, 97 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS0_LAST /* this entry must be last!!! */ 98 }; 99 100 enum virtchnl_rx_flex_desc_adv_status_error_1_bits { 101 /* Note: These are predefined bit offsets */ 102 /* 2 bits */ 103 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS1_RSVD_S = 0, 104 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS1_ATRAEFAIL_S = 2, 105 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS1_L2TAG2P_S = 3, 106 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS1_XTRMD2_VALID_S = 4, 107 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS1_XTRMD3_VALID_S = 5, 108 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS1_XTRMD4_VALID_S = 6, 109 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS1_XTRMD5_VALID_S = 7, 110 VIRTCHNL_RX_FLEX_DESC_ADV_STATUS1_LAST /* this entry must be last!!! */ 111 }; 112 113 /* for singleq (flex) virtchnl_rx_flex_desc fields */ 114 /* for virtchnl_rx_flex_desc.ptype_flex_flags0 member */ 115 #define VIRTCHNL_RX_FLEX_DESC_PTYPE_S 0 116 #define VIRTCHNL_RX_FLEX_DESC_PTYPE_M \ 117 MAKEMASK(0x3FFUL, VIRTCHNL_RX_FLEX_DESC_PTYPE_S) /* 10-bits */ 118 119 /* for virtchnl_rx_flex_desc.pkt_length member */ 120 #define VIRTCHNL_RX_FLEX_DESC_PKT_LEN_S 0 121 #define VIRTCHNL_RX_FLEX_DESC_PKT_LEN_M \ 122 MAKEMASK(0x3FFFUL, VIRTCHNL_RX_FLEX_DESC_PKT_LEN_S) /* 14-bits */ 123 124 enum virtchnl_rx_flex_desc_status_error_0_bits { 125 /* Note: These are predefined bit offsets */ 126 VIRTCHNL_RX_FLEX_DESC_STATUS0_DD_S = 0, 127 VIRTCHNL_RX_FLEX_DESC_STATUS0_EOF_S, 128 VIRTCHNL_RX_FLEX_DESC_STATUS0_HBO_S, 129 VIRTCHNL_RX_FLEX_DESC_STATUS0_L3L4P_S, 130 VIRTCHNL_RX_FLEX_DESC_STATUS0_XSUM_IPE_S, 131 VIRTCHNL_RX_FLEX_DESC_STATUS0_XSUM_L4E_S, 132 VIRTCHNL_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S, 133 VIRTCHNL_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S, 134 VIRTCHNL_RX_FLEX_DESC_STATUS0_LPBK_S, 135 VIRTCHNL_RX_FLEX_DESC_STATUS0_IPV6EXADD_S, 136 VIRTCHNL_RX_FLEX_DESC_STATUS0_RXE_S, 137 VIRTCHNL_RX_FLEX_DESC_STATUS0_CRCP_S, 138 VIRTCHNL_RX_FLEX_DESC_STATUS0_RSS_VALID_S, 139 VIRTCHNL_RX_FLEX_DESC_STATUS0_L2TAG1P_S, 140 VIRTCHNL_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S, 141 VIRTCHNL_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S, 142 VIRTCHNL_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */ 143 }; 144 145 enum virtchnl_rx_flex_desc_status_error_1_bits { 146 /* Note: These are predefined bit offsets */ 147 VIRTCHNL_RX_FLEX_DESC_STATUS1_CPM_S = 0, /* 4 bits */ 148 VIRTCHNL_RX_FLEX_DESC_STATUS1_NAT_S = 4, 149 VIRTCHNL_RX_FLEX_DESC_STATUS1_CRYPTO_S = 5, 150 /* [10:6] reserved */ 151 VIRTCHNL_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11, 152 VIRTCHNL_RX_FLEX_DESC_STATUS1_XTRMD2_VALID_S = 12, 153 VIRTCHNL_RX_FLEX_DESC_STATUS1_XTRMD3_VALID_S = 13, 154 VIRTCHNL_RX_FLEX_DESC_STATUS1_XTRMD4_VALID_S = 14, 155 VIRTCHNL_RX_FLEX_DESC_STATUS1_XTRMD5_VALID_S = 15, 156 VIRTCHNL_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */ 157 }; 158 159 /* For singleq (non flex) virtchnl_singleq_base_rx_desc legacy desc members */ 160 #define VIRTCHNL_RX_BASE_DESC_QW1_LEN_SPH_S 63 161 #define VIRTCHNL_RX_BASE_DESC_QW1_LEN_SPH_M \ 162 BIT_ULL(VIRTCHNL_RX_BASE_DESC_QW1_LEN_SPH_S) 163 #define VIRTCHNL_RX_BASE_DESC_QW1_LEN_HBUF_S 52 164 #define VIRTCHNL_RX_BASE_DESC_QW1_LEN_HBUF_M \ 165 MAKEMASK(0x7FFULL, VIRTCHNL_RX_BASE_DESC_QW1_LEN_HBUF_S) 166 #define VIRTCHNL_RX_BASE_DESC_QW1_LEN_PBUF_S 38 167 #define VIRTCHNL_RX_BASE_DESC_QW1_LEN_PBUF_M \ 168 MAKEMASK(0x3FFFULL, VIRTCHNL_RX_BASE_DESC_QW1_LEN_PBUF_S) 169 #define VIRTCHNL_RX_BASE_DESC_QW1_PTYPE_S 30 170 #define VIRTCHNL_RX_BASE_DESC_QW1_PTYPE_M \ 171 MAKEMASK(0xFFULL, VIRTCHNL_RX_BASE_DESC_QW1_PTYPE_S) 172 #define VIRTCHNL_RX_BASE_DESC_QW1_ERROR_S 19 173 #define VIRTCHNL_RX_BASE_DESC_QW1_ERROR_M \ 174 MAKEMASK(0xFFUL, VIRTCHNL_RX_BASE_DESC_QW1_ERROR_S) 175 #define VIRTCHNL_RX_BASE_DESC_QW1_STATUS_S 0 176 #define VIRTCHNL_RX_BASE_DESC_QW1_STATUS_M \ 177 MAKEMASK(0x7FFFFUL, VIRTCHNL_RX_BASE_DESC_QW1_STATUS_S) 178 179 enum virtchnl_rx_base_desc_status_bits { 180 /* Note: These are predefined bit offsets */ 181 VIRTCHNL_RX_BASE_DESC_STATUS_DD_S = 0, 182 VIRTCHNL_RX_BASE_DESC_STATUS_EOF_S = 1, 183 VIRTCHNL_RX_BASE_DESC_STATUS_L2TAG1P_S = 2, 184 VIRTCHNL_RX_BASE_DESC_STATUS_L3L4P_S = 3, 185 VIRTCHNL_RX_BASE_DESC_STATUS_CRCP_S = 4, 186 VIRTCHNL_RX_BASE_DESC_STATUS_RSVD_S = 5, /* 3 BITS */ 187 VIRTCHNL_RX_BASE_DESC_STATUS_EXT_UDP_0_S = 8, 188 VIRTCHNL_RX_BASE_DESC_STATUS_UMBCAST_S = 9, /* 2 BITS */ 189 VIRTCHNL_RX_BASE_DESC_STATUS_FLM_S = 11, 190 VIRTCHNL_RX_BASE_DESC_STATUS_FLTSTAT_S = 12, /* 2 BITS */ 191 VIRTCHNL_RX_BASE_DESC_STATUS_LPBK_S = 14, 192 VIRTCHNL_RX_BASE_DESC_STATUS_IPV6EXADD_S = 15, 193 VIRTCHNL_RX_BASE_DESC_STATUS_RSVD1_S = 16, /* 2 BITS */ 194 VIRTCHNL_RX_BASE_DESC_STATUS_INT_UDP_0_S = 18, 195 VIRTCHNL_RX_BASE_DESC_STATUS_LAST /* this entry must be last!!! */ 196 }; 197 198 enum virtchnl_rx_base_desc_ext_status_bits { 199 /* Note: These are predefined bit offsets */ 200 VIRTCHNL_RX_BASE_DESC_EXT_STATUS_L2TAG2P_S = 0 201 }; 202 203 enum virtchnl_rx_base_desc_error_bits { 204 /* Note: These are predefined bit offsets */ 205 VIRTCHNL_RX_BASE_DESC_ERROR_RXE_S = 0, 206 VIRTCHNL_RX_BASE_DESC_ERROR_ATRAEFAIL_S = 1, 207 VIRTCHNL_RX_BASE_DESC_ERROR_HBO_S = 2, 208 VIRTCHNL_RX_BASE_DESC_ERROR_L3L4E_S = 3, /* 3 BITS */ 209 VIRTCHNL_RX_BASE_DESC_ERROR_IPE_S = 3, 210 VIRTCHNL_RX_BASE_DESC_ERROR_L4E_S = 4, 211 VIRTCHNL_RX_BASE_DESC_ERROR_EIPE_S = 5, 212 VIRTCHNL_RX_BASE_DESC_ERROR_OVERSIZE_S = 6, 213 VIRTCHNL_RX_BASE_DESC_ERROR_PPRS_S = 7 214 }; 215 216 enum virtchnl_rx_base_desc_fltstat_values { 217 VIRTCHNL_RX_BASE_DESC_FLTSTAT_NO_DATA = 0, 218 VIRTCHNL_RX_BASE_DESC_FLTSTAT_FD_ID = 1, 219 VIRTCHNL_RX_BASE_DESC_FLTSTAT_RSV = 2, 220 VIRTCHNL_RX_BASE_DESC_FLTSTAT_RSS_HASH = 3, 221 }; 222 223 /* Receive Descriptors */ 224 /* splitq buf 225 | 16| 0| 226 ---------------------------------------------------------------- 227 | RSV | Buffer ID | 228 ---------------------------------------------------------------- 229 | Rx packet buffer adresss | 230 ---------------------------------------------------------------- 231 | Rx header buffer adresss | 232 ---------------------------------------------------------------- 233 | RSV | 234 ---------------------------------------------------------------- 235 | 0| 236 */ 237 struct virtchnl_splitq_rx_buf_desc { 238 struct { 239 __le16 buf_id; /* Buffer Identifier */ 240 __le16 rsvd0; 241 __le32 rsvd1; 242 } qword0; 243 __le64 pkt_addr; /* Packet buffer address */ 244 __le64 hdr_addr; /* Header buffer address */ 245 __le64 rsvd2; 246 }; /* read used with buffer queues*/ 247 248 /* singleq buf 249 | 0| 250 ---------------------------------------------------------------- 251 | Rx packet buffer adresss | 252 ---------------------------------------------------------------- 253 | Rx header buffer adresss | 254 ---------------------------------------------------------------- 255 | RSV | 256 ---------------------------------------------------------------- 257 | RSV | 258 ---------------------------------------------------------------- 259 | 0| 260 */ 261 struct virtchnl_singleq_rx_buf_desc { 262 __le64 pkt_addr; /* Packet buffer address */ 263 __le64 hdr_addr; /* Header buffer address */ 264 __le64 rsvd1; 265 __le64 rsvd2; 266 }; /* read used with buffer queues*/ 267 268 union virtchnl_rx_buf_desc { 269 struct virtchnl_singleq_rx_buf_desc read; 270 struct virtchnl_splitq_rx_buf_desc split_rd; 271 }; 272 273 /* (0x00) singleq wb(compl) */ 274 struct virtchnl_singleq_base_rx_desc { 275 struct { 276 struct { 277 __le16 mirroring_status; 278 __le16 l2tag1; 279 } lo_dword; 280 union { 281 __le32 rss; /* RSS Hash */ 282 __le32 fd_id; /* Flow Director filter id */ 283 } hi_dword; 284 } qword0; 285 struct { 286 /* status/error/PTYPE/length */ 287 __le64 status_error_ptype_len; 288 } qword1; 289 struct { 290 __le16 ext_status; /* extended status */ 291 __le16 rsvd; 292 __le16 l2tag2_1; 293 __le16 l2tag2_2; 294 } qword2; 295 struct { 296 __le32 reserved; 297 __le32 fd_id; 298 } qword3; 299 }; /* writeback */ 300 301 /* (0x01) singleq flex compl */ 302 struct virtchnl_rx_flex_desc { 303 /* Qword 0 */ 304 u8 rxdid; /* descriptor builder profile id */ 305 u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */ 306 __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */ 307 __le16 pkt_len; /* [15:14] are reserved */ 308 __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */ 309 /* sph=[11:11] */ 310 /* ff1/ext=[15:12] */ 311 312 /* Qword 1 */ 313 __le16 status_error0; 314 __le16 l2tag1; 315 __le16 flex_meta0; 316 __le16 flex_meta1; 317 318 /* Qword 2 */ 319 __le16 status_error1; 320 u8 flex_flags2; 321 u8 time_stamp_low; 322 __le16 l2tag2_1st; 323 __le16 l2tag2_2nd; 324 325 /* Qword 3 */ 326 __le16 flex_meta2; 327 __le16 flex_meta3; 328 union { 329 struct { 330 __le16 flex_meta4; 331 __le16 flex_meta5; 332 } flex; 333 __le32 ts_high; 334 } flex_ts; 335 }; 336 337 /* (0x02) */ 338 struct virtchnl_rx_flex_desc_nic { 339 /* Qword 0 */ 340 u8 rxdid; 341 u8 mir_id_umb_cast; 342 __le16 ptype_flex_flags0; 343 __le16 pkt_len; 344 __le16 hdr_len_sph_flex_flags1; 345 346 /* Qword 1 */ 347 __le16 status_error0; 348 __le16 l2tag1; 349 __le32 rss_hash; 350 351 /* Qword 2 */ 352 __le16 status_error1; 353 u8 flexi_flags2; 354 u8 ts_low; 355 __le16 l2tag2_1st; 356 __le16 l2tag2_2nd; 357 358 /* Qword 3 */ 359 __le32 flow_id; 360 union { 361 struct { 362 __le16 rsvd; 363 __le16 flow_id_ipv6; 364 } flex; 365 __le32 ts_high; 366 } flex_ts; 367 }; 368 369 /* Rx Flex Descriptor Switch Profile 370 * RxDID Profile Id 3 371 * Flex-field 0: Source Vsi 372 */ 373 struct virtchnl_rx_flex_desc_sw { 374 /* Qword 0 */ 375 u8 rxdid; 376 u8 mir_id_umb_cast; 377 __le16 ptype_flex_flags0; 378 __le16 pkt_len; 379 __le16 hdr_len_sph_flex_flags1; 380 381 /* Qword 1 */ 382 __le16 status_error0; 383 __le16 l2tag1; 384 __le16 src_vsi; /* [10:15] are reserved */ 385 __le16 flex_md1_rsvd; 386 387 /* Qword 2 */ 388 __le16 status_error1; 389 u8 flex_flags2; 390 u8 ts_low; 391 __le16 l2tag2_1st; 392 __le16 l2tag2_2nd; 393 394 /* Qword 3 */ 395 __le32 rsvd; /* flex words 2-3 are reserved */ 396 __le32 ts_high; 397 }; 398 399 /* Rx Flex Descriptor NIC Profile 400 * RxDID Profile Id 6 401 * Flex-field 0: RSS hash lower 16-bits 402 * Flex-field 1: RSS hash upper 16-bits 403 * Flex-field 2: Flow Id lower 16-bits 404 * Flex-field 3: Source Vsi 405 * Flex-field 4: reserved, Vlan id taken from L2Tag 406 */ 407 struct virtchnl_rx_flex_desc_nic_2 { 408 /* Qword 0 */ 409 u8 rxdid; 410 u8 mir_id_umb_cast; 411 __le16 ptype_flex_flags0; 412 __le16 pkt_len; 413 __le16 hdr_len_sph_flex_flags1; 414 415 /* Qword 1 */ 416 __le16 status_error0; 417 __le16 l2tag1; 418 __le32 rss_hash; 419 420 /* Qword 2 */ 421 __le16 status_error1; 422 u8 flexi_flags2; 423 u8 ts_low; 424 __le16 l2tag2_1st; 425 __le16 l2tag2_2nd; 426 427 /* Qword 3 */ 428 __le16 flow_id; 429 __le16 src_vsi; 430 union { 431 struct { 432 __le16 rsvd; 433 __le16 flow_id_ipv6; 434 } flex; 435 __le32 ts_high; 436 } flex_ts; 437 }; 438 439 /* Rx Flex Descriptor Advanced (Split Queue Model) 440 * RxDID Profile Id 7 441 */ 442 struct virtchnl_rx_flex_desc_adv { 443 /* Qword 0 */ 444 u8 rxdid_ucast; /* profile_id=[3:0] */ 445 /* rsvd=[5:4] */ 446 /* ucast=[7:6] */ 447 u8 status_err0_qw0; 448 __le16 ptype_err_fflags0; /* ptype=[9:0] */ 449 /* ip_hdr_err=[10:10] */ 450 /* udp_len_err=[11:11] */ 451 /* ff0=[15:12] */ 452 __le16 pktlen_gen_bufq_id; /* plen=[13:0] */ 453 /* gen=[14:14] only in splitq */ 454 /* bufq_id=[15:15] only in splitq */ 455 __le16 hdrlen_flags; /* header=[9:0] */ 456 /* rsc=[10:10] only in splitq */ 457 /* sph=[11:11] only in splitq */ 458 /* ext_udp_0=[12:12] */ 459 /* int_udp_0=[13:13] */ 460 /* trunc_mirr=[14:14] */ 461 /* miss_prepend=[15:15] */ 462 /* Qword 1 */ 463 u8 status_err0_qw1; 464 u8 status_err1; 465 u8 fflags1; 466 u8 ts_low; 467 __le16 fmd0; 468 __le16 fmd1; 469 /* Qword 2 */ 470 __le16 fmd2; 471 u8 fflags2; 472 u8 hash3; 473 __le16 fmd3; 474 __le16 fmd4; 475 /* Qword 3 */ 476 __le16 fmd5; 477 __le16 fmd6; 478 __le16 fmd7_0; 479 __le16 fmd7_1; 480 }; /* writeback */ 481 482 /* Rx Flex Descriptor Advanced (Split Queue Model) NIC Profile 483 * RxDID Profile Id 8 484 * Flex-field 0: BufferID 485 * Flex-field 1: Raw checksum/L2TAG1/RSC Seg Len (determined by HW) 486 * Flex-field 2: Hash[15:0] 487 * Flex-flags 2: Hash[23:16] 488 * Flex-field 3: L2TAG2 489 * Flex-field 5: L2TAG1 490 * Flex-field 7: Timestamp (upper 32 bits) 491 */ 492 struct virtchnl_rx_flex_desc_adv_nic_3 { 493 /* Qword 0 */ 494 u8 rxdid_ucast; /* profile_id=[3:0] */ 495 /* rsvd=[5:4] */ 496 /* ucast=[7:6] */ 497 u8 status_err0_qw0; 498 __le16 ptype_err_fflags0; /* ptype=[9:0] */ 499 /* ip_hdr_err=[10:10] */ 500 /* udp_len_err=[11:11] */ 501 /* ff0=[15:12] */ 502 __le16 pktlen_gen_bufq_id; /* plen=[13:0] */ 503 /* gen=[14:14] only in splitq */ 504 /* bufq_id=[15:15] only in splitq */ 505 __le16 hdrlen_flags; /* header=[9:0] */ 506 /* rsc=[10:10] only in splitq */ 507 /* sph=[11:11] only in splitq */ 508 /* ext_udp_0=[12:12] */ 509 /* int_udp_0=[13:13] */ 510 /* trunc_mirr=[14:14] */ 511 /* miss_prepend=[15:15] */ 512 /* Qword 1 */ 513 u8 status_err0_qw1; 514 u8 status_err1; 515 u8 fflags1; 516 u8 ts_low; 517 __le16 buf_id; /* only in splitq */ 518 union { 519 __le16 raw_cs; 520 __le16 l2tag1; 521 __le16 rscseglen; 522 } misc; 523 /* Qword 2 */ 524 __le16 hash1; 525 union { 526 u8 fflags2; 527 u8 mirrorid; 528 u8 hash2; 529 } ff2_mirrid_hash2; 530 u8 hash3; 531 __le16 l2tag2; 532 __le16 fmd4; 533 /* Qword 3 */ 534 __le16 l2tag1; 535 __le16 fmd6; 536 __le32 ts_high; 537 }; /* writeback */ 538 539 union virtchnl_rx_desc { 540 struct virtchnl_singleq_rx_buf_desc read; 541 struct virtchnl_singleq_base_rx_desc base_wb; 542 struct virtchnl_rx_flex_desc flex_wb; 543 struct virtchnl_rx_flex_desc_nic flex_nic_wb; 544 struct virtchnl_rx_flex_desc_sw flex_sw_wb; 545 struct virtchnl_rx_flex_desc_nic_2 flex_nic_2_wb; 546 struct virtchnl_rx_flex_desc_adv flex_adv_wb; 547 struct virtchnl_rx_flex_desc_adv_nic_3 flex_adv_nic_3_wb; 548 }; 549 550 #endif /* _VIRTCHNL_LAN_DESC_H_ */
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