1 /*
2 * Copyright (c) 2014 The DragonFly Project. All rights reserved.
3 *
4 * This code is derived from software contributed to The DragonFly Project
5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported
6 * to FreeBSD by Michael Gmelin <freebsd@grem.de>
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in
16 * the documentation and/or other materials provided with the
17 * distribution.
18 * 3. Neither the name of The DragonFly Project nor the names of its
19 * contributors may be used to endorse or promote products derived
20 * from this software without specific, prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38
39 /*
40 * Intel fourth generation mobile cpus integrated I2C device.
41 *
42 * See ig4_reg.h for datasheet reference and notes.
43 * See ig4_var.h for locking semantics.
44 */
45
46 #include "opt_acpi.h"
47
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/kernel.h>
51 #include <sys/module.h>
52 #include <sys/errno.h>
53 #include <sys/kdb.h>
54 #include <sys/lock.h>
55 #include <sys/mutex.h>
56 #include <sys/proc.h>
57 #include <sys/sx.h>
58 #include <sys/syslog.h>
59 #include <sys/bus.h>
60 #include <sys/sysctl.h>
61
62 #include <machine/bus.h>
63 #include <sys/rman.h>
64
65 #ifdef DEV_ACPI
66 #include <contrib/dev/acpica/include/acpi.h>
67 #include <contrib/dev/acpica/include/accommon.h>
68 #include <dev/acpica/acpivar.h>
69 #endif
70
71 #include <dev/iicbus/iicbus.h>
72 #include <dev/iicbus/iiconf.h>
73
74 #include <dev/ichiic/ig4_reg.h>
75 #include <dev/ichiic/ig4_var.h>
76
77 #define DO_POLL(sc) (cold || kdb_active || SCHEDULER_STOPPED() || sc->poll)
78
79 /*
80 * tLOW, tHIGH periods of the SCL clock and maximal falling time of both
81 * lines are taken from I2C specifications.
82 */
83 #define IG4_SPEED_STD_THIGH 4000 /* nsec */
84 #define IG4_SPEED_STD_TLOW 4700 /* nsec */
85 #define IG4_SPEED_STD_TF_MAX 300 /* nsec */
86 #define IG4_SPEED_FAST_THIGH 600 /* nsec */
87 #define IG4_SPEED_FAST_TLOW 1300 /* nsec */
88 #define IG4_SPEED_FAST_TF_MAX 300 /* nsec */
89
90 /*
91 * Ig4 hardware parameters except Haswell are taken from intel_lpss driver
92 */
93 static const struct ig4_hw ig4iic_hw[] = {
94 [IG4_HASWELL] = {
95 .ic_clock_rate = 100, /* MHz */
96 .sda_hold_time = 90, /* nsec */
97 .txfifo_depth = 32,
98 .rxfifo_depth = 32,
99 },
100 [IG4_ATOM] = {
101 .ic_clock_rate = 100,
102 .sda_fall_time = 280,
103 .scl_fall_time = 240,
104 .sda_hold_time = 60,
105 .txfifo_depth = 32,
106 .rxfifo_depth = 32,
107 },
108 [IG4_SKYLAKE] = {
109 .ic_clock_rate = 120,
110 .sda_hold_time = 230,
111 },
112 [IG4_APL] = {
113 .ic_clock_rate = 133,
114 .sda_fall_time = 171,
115 .scl_fall_time = 208,
116 .sda_hold_time = 207,
117 },
118 [IG4_CANNONLAKE] = {
119 .ic_clock_rate = 216,
120 .sda_hold_time = 230,
121 },
122 [IG4_TIGERLAKE] = {
123 .ic_clock_rate = 133,
124 .sda_fall_time = 171,
125 .scl_fall_time = 208,
126 .sda_hold_time = 42,
127 },
128 [IG4_GEMINILAKE] = {
129 .ic_clock_rate = 133,
130 .sda_fall_time = 171,
131 .scl_fall_time = 290,
132 .sda_hold_time = 313,
133 },
134 };
135
136 static int ig4iic_set_config(ig4iic_softc_t *sc, bool reset);
137 static driver_filter_t ig4iic_intr;
138 static void ig4iic_dump(ig4iic_softc_t *sc);
139
140 static int ig4_dump;
141 SYSCTL_INT(_debug, OID_AUTO, ig4_dump, CTLFLAG_RW,
142 &ig4_dump, 0, "Dump controller registers");
143
144 /*
145 * Clock registers initialization control
146 * 0 - Try read clock registers from ACPI and fallback to p.1.
147 * 1 - Calculate values based on controller type (IC clock rate).
148 * 2 - Use values inherited from DragonflyBSD driver (old behavior).
149 * 3 - Keep clock registers intact.
150 */
151 static int ig4_timings;
152 SYSCTL_INT(_debug, OID_AUTO, ig4_timings, CTLFLAG_RDTUN, &ig4_timings, 0,
153 "Controller timings 0=ACPI, 1=predefined, 2=legacy, 3=do not change");
154
155 /*
156 * Low-level inline support functions
157 */
158 static __inline void
159 reg_write(ig4iic_softc_t *sc, uint32_t reg, uint32_t value)
160 {
161 bus_write_4(sc->regs_res, reg, value);
162 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_WRITE);
163 }
164
165 static __inline uint32_t
166 reg_read(ig4iic_softc_t *sc, uint32_t reg)
167 {
168 uint32_t value;
169
170 bus_barrier(sc->regs_res, reg, 4, BUS_SPACE_BARRIER_READ);
171 value = bus_read_4(sc->regs_res, reg);
172 return (value);
173 }
174
175 static void
176 ig4iic_set_intr_mask(ig4iic_softc_t *sc, uint32_t val)
177 {
178 if (sc->intr_mask != val) {
179 reg_write(sc, IG4_REG_INTR_MASK, val);
180 sc->intr_mask = val;
181 }
182 }
183
184 static int
185 intrstat2iic(ig4iic_softc_t *sc, uint32_t val)
186 {
187 uint32_t src;
188
189 if (val & IG4_INTR_RX_UNDER)
190 reg_read(sc, IG4_REG_CLR_RX_UNDER);
191 if (val & IG4_INTR_RX_OVER)
192 reg_read(sc, IG4_REG_CLR_RX_OVER);
193 if (val & IG4_INTR_TX_OVER)
194 reg_read(sc, IG4_REG_CLR_TX_OVER);
195
196 if (val & IG4_INTR_TX_ABRT) {
197 src = reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
198 reg_read(sc, IG4_REG_CLR_TX_ABORT);
199 /* User-requested abort. Not really a error */
200 if (src & IG4_ABRTSRC_TRANSFER)
201 return (IIC_ESTATUS);
202 /* Master has lost arbitration */
203 if (src & IG4_ABRTSRC_ARBLOST)
204 return (IIC_EBUSBSY);
205 /* Did not receive an acknowledge from the remote slave */
206 if (src & (IG4_ABRTSRC_TXNOACK_ADDR7 |
207 IG4_ABRTSRC_TXNOACK_ADDR10_1 |
208 IG4_ABRTSRC_TXNOACK_ADDR10_2 |
209 IG4_ABRTSRC_TXNOACK_DATA |
210 IG4_ABRTSRC_GENCALL_NOACK))
211 return (IIC_ENOACK);
212 /* Programming errors */
213 if (src & (IG4_ABRTSRC_GENCALL_READ |
214 IG4_ABRTSRC_NORESTART_START |
215 IG4_ABRTSRC_NORESTART_10))
216 return (IIC_ENOTSUPP);
217 /* Other errors */
218 if (src & IG4_ABRTSRC_ACKED_START)
219 return (IIC_EBUSERR);
220 }
221 /*
222 * TX_OVER, RX_OVER and RX_UNDER are caused by wrong RX/TX FIFO depth
223 * detection or driver's read/write pipelining errors.
224 */
225 if (val & (IG4_INTR_TX_OVER | IG4_INTR_RX_OVER))
226 return (IIC_EOVERFLOW);
227 if (val & IG4_INTR_RX_UNDER)
228 return (IIC_EUNDERFLOW);
229
230 return (IIC_NOERR);
231 }
232
233 /*
234 * Enable or disable the controller and wait for the controller to acknowledge
235 * the state change.
236 */
237 static int
238 set_controller(ig4iic_softc_t *sc, uint32_t ctl)
239 {
240 int retry;
241 int error;
242 uint32_t v;
243
244 /*
245 * When the controller is enabled, interrupt on STOP detect
246 * or receive character ready and clear pending interrupts.
247 */
248 ig4iic_set_intr_mask(sc, 0);
249 if (ctl & IG4_I2C_ENABLE)
250 reg_read(sc, IG4_REG_CLR_INTR);
251
252 reg_write(sc, IG4_REG_I2C_EN, ctl);
253 error = IIC_ETIMEOUT;
254
255 for (retry = 100; retry > 0; --retry) {
256 v = reg_read(sc, IG4_REG_ENABLE_STATUS);
257 if (((v ^ ctl) & IG4_I2C_ENABLE) == 0) {
258 error = 0;
259 break;
260 }
261 pause("i2cslv", 1);
262 }
263 return (error);
264 }
265
266 /*
267 * Wait up to 25ms for the requested interrupt using a 25uS polling loop.
268 */
269 static int
270 wait_intr(ig4iic_softc_t *sc, uint32_t intr)
271 {
272 uint32_t v;
273 int error;
274 int txlvl = -1;
275 u_int count_us = 0;
276 u_int limit_us = 1000000; /* 1sec */
277
278 for (;;) {
279 /*
280 * Check requested status
281 */
282 v = reg_read(sc, IG4_REG_RAW_INTR_STAT);
283 error = intrstat2iic(sc, v & IG4_INTR_ERR_MASK);
284 if (error || (v & intr))
285 break;
286
287 /*
288 * When waiting for the transmit FIFO to become empty,
289 * reset the timeout if we see a change in the transmit
290 * FIFO level as progress is being made.
291 */
292 if (intr & (IG4_INTR_TX_EMPTY | IG4_INTR_STOP_DET)) {
293 v = reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK;
294 if (txlvl != v) {
295 txlvl = v;
296 count_us = 0;
297 }
298 }
299
300 /*
301 * Stop if we've run out of time.
302 */
303 if (count_us >= limit_us) {
304 error = IIC_ETIMEOUT;
305 break;
306 }
307
308 /*
309 * When polling is not requested let the interrupt do its work.
310 */
311 if (!DO_POLL(sc)) {
312 mtx_lock_spin(&sc->io_lock);
313 ig4iic_set_intr_mask(sc, intr | IG4_INTR_ERR_MASK);
314 msleep_spin(sc, &sc->io_lock, "i2cwait",
315 (hz + 99) / 100); /* sleep up to 10ms */
316 ig4iic_set_intr_mask(sc, 0);
317 mtx_unlock_spin(&sc->io_lock);
318 count_us += 10000;
319 } else {
320 DELAY(25);
321 count_us += 25;
322 }
323 }
324
325 return (error);
326 }
327
328 /*
329 * Set the slave address. The controller must be disabled when
330 * changing the address.
331 *
332 * This operation does not issue anything to the I2C bus but sets
333 * the target address for when the controller later issues a START.
334 */
335 static void
336 set_slave_addr(ig4iic_softc_t *sc, uint8_t slave)
337 {
338 uint32_t tar;
339 uint32_t ctl;
340 int use_10bit;
341
342 use_10bit = 0;
343 if (sc->slave_valid && sc->last_slave == slave &&
344 sc->use_10bit == use_10bit) {
345 return;
346 }
347 sc->use_10bit = use_10bit;
348
349 /*
350 * Wait for TXFIFO to drain before disabling the controller.
351 */
352 wait_intr(sc, IG4_INTR_TX_EMPTY);
353
354 set_controller(sc, 0);
355 ctl = reg_read(sc, IG4_REG_CTL);
356 ctl &= ~IG4_CTL_10BIT;
357 ctl |= IG4_CTL_RESTARTEN;
358
359 tar = slave;
360 if (sc->use_10bit) {
361 tar |= IG4_TAR_10BIT;
362 ctl |= IG4_CTL_10BIT;
363 }
364 reg_write(sc, IG4_REG_CTL, ctl);
365 reg_write(sc, IG4_REG_TAR_ADD, tar);
366 set_controller(sc, IG4_I2C_ENABLE);
367 sc->slave_valid = 1;
368 sc->last_slave = slave;
369 }
370
371 /*
372 * IICBUS API FUNCTIONS
373 */
374 static int
375 ig4iic_xfer_start(ig4iic_softc_t *sc, uint16_t slave, bool repeated_start)
376 {
377 set_slave_addr(sc, slave >> 1);
378
379 if (!repeated_start) {
380 /*
381 * Clear any previous TX/RX FIFOs overflow/underflow bits
382 * and I2C bus STOP condition.
383 */
384 reg_read(sc, IG4_REG_CLR_INTR);
385 }
386
387 return (0);
388 }
389
390 static bool
391 ig4iic_xfer_is_started(ig4iic_softc_t *sc)
392 {
393 /*
394 * It requires that no IG4_REG_CLR_INTR or IG4_REG_CLR_START/STOP_DET
395 * register reads is issued after START condition.
396 */
397 return ((reg_read(sc, IG4_REG_RAW_INTR_STAT) &
398 (IG4_INTR_START_DET | IG4_INTR_STOP_DET)) == IG4_INTR_START_DET);
399 }
400
401 static int
402 ig4iic_xfer_abort(ig4iic_softc_t *sc)
403 {
404 int error;
405
406 /* Request send of STOP condition and flush of TX FIFO */
407 set_controller(sc, IG4_I2C_ABORT | IG4_I2C_ENABLE);
408 /*
409 * Wait for the TX_ABRT interrupt with ABRTSRC_TRANSFER
410 * bit set in TX_ABRT_SOURCE register.
411 */
412 error = wait_intr(sc, IG4_INTR_STOP_DET);
413 set_controller(sc, IG4_I2C_ENABLE);
414
415 return (error == IIC_ESTATUS ? 0 : error);
416 }
417
418 /*
419 * Amount of unread data before next burst to get better I2C bus utilization.
420 * 2 bytes is enough in FAST mode. 8 bytes is better in FAST+ and HIGH modes.
421 * Intel-recommended value is 16 for DMA transfers with 64-byte depth FIFOs.
422 */
423 #define IG4_FIFO_LOWAT 2
424
425 static int
426 ig4iic_read(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len,
427 bool repeated_start, bool stop)
428 {
429 uint32_t cmd;
430 int requested = 0;
431 int received = 0;
432 int burst, target, lowat = 0;
433 int error;
434
435 if (len == 0)
436 return (0);
437
438 while (received < len) {
439 burst = sc->cfg.txfifo_depth -
440 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
441 if (burst <= 0) {
442 error = wait_intr(sc, IG4_INTR_TX_EMPTY);
443 if (error)
444 break;
445 burst = sc->cfg.txfifo_depth;
446 }
447 /* Ensure we have enough free space in RXFIFO */
448 burst = MIN(burst, sc->cfg.rxfifo_depth - lowat);
449 target = MIN(requested + burst, (int)len);
450 while (requested < target) {
451 cmd = IG4_DATA_COMMAND_RD;
452 if (repeated_start && requested == 0)
453 cmd |= IG4_DATA_RESTART;
454 if (stop && requested == len - 1)
455 cmd |= IG4_DATA_STOP;
456 reg_write(sc, IG4_REG_DATA_CMD, cmd);
457 requested++;
458 }
459 /* Leave some data queued to maintain the hardware pipeline */
460 lowat = 0;
461 if (requested != len && requested - received > IG4_FIFO_LOWAT)
462 lowat = IG4_FIFO_LOWAT;
463 /* After TXFLR fills up, clear it by reading available data */
464 while (received < requested - lowat) {
465 burst = MIN((int)len - received,
466 reg_read(sc, IG4_REG_RXFLR) & IG4_FIFOLVL_MASK);
467 if (burst > 0) {
468 while (burst--)
469 buf[received++] = 0xFF &
470 reg_read(sc, IG4_REG_DATA_CMD);
471 } else {
472 error = wait_intr(sc, IG4_INTR_RX_FULL);
473 if (error)
474 goto out;
475 }
476 }
477 }
478 out:
479 return (error);
480 }
481
482 static int
483 ig4iic_write(ig4iic_softc_t *sc, uint8_t *buf, uint16_t len,
484 bool repeated_start, bool stop)
485 {
486 uint32_t cmd;
487 int sent = 0;
488 int burst, target;
489 int error;
490 bool lowat_set = false;
491
492 if (len == 0)
493 return (0);
494
495 while (sent < len) {
496 burst = sc->cfg.txfifo_depth -
497 (reg_read(sc, IG4_REG_TXFLR) & IG4_FIFOLVL_MASK);
498 target = MIN(sent + burst, (int)len);
499 /* Leave some data queued to maintain the hardware pipeline */
500 if (!lowat_set && target != len) {
501 lowat_set = true;
502 reg_write(sc, IG4_REG_TX_TL, IG4_FIFO_LOWAT);
503 }
504 while(sent < target) {
505 cmd = buf[sent];
506 if (repeated_start && sent == 0)
507 cmd |= IG4_DATA_RESTART;
508 if (stop && sent == len - 1)
509 cmd |= IG4_DATA_STOP;
510 reg_write(sc, IG4_REG_DATA_CMD, cmd);
511 sent++;
512 }
513 if (sent < len) {
514 error = wait_intr(sc, IG4_INTR_TX_EMPTY);
515 if (error)
516 break;
517 }
518 }
519 if (lowat_set)
520 reg_write(sc, IG4_REG_TX_TL, 0);
521
522 return (error);
523 }
524
525 int
526 ig4iic_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
527 {
528 ig4iic_softc_t *sc = device_get_softc(dev);
529 const char *reason = NULL;
530 uint32_t i;
531 int error;
532 int unit;
533 bool rpstart;
534 bool stop;
535 bool allocated;
536
537 /*
538 * The hardware interface imposes limits on allowed I2C messages.
539 * It is not possible to explicitly send a start or stop.
540 * They are automatically sent (or not sent, depending on the
541 * configuration) when a data byte is transferred.
542 * For this reason it's impossible to send a message with no data
543 * at all (like an SMBus quick message).
544 * The start condition is automatically generated after the stop
545 * condition, so it's impossible to not have a start after a stop.
546 * The repeated start condition is automatically sent if a change
547 * of the transfer direction happens, so it's impossible to have
548 * a change of direction without a (repeated) start.
549 * The repeated start can be forced even without the change of
550 * direction.
551 * Changing the target slave address requires resetting the hardware
552 * state, so it's impossible to do that without the stop followed
553 * by the start.
554 */
555 for (i = 0; i < nmsgs; i++) {
556 #if 0
557 if (i == 0 && (msgs[i].flags & IIC_M_NOSTART) != 0) {
558 reason = "first message without start";
559 break;
560 }
561 if (i == nmsgs - 1 && (msgs[i].flags & IIC_M_NOSTOP) != 0) {
562 reason = "last message without stop";
563 break;
564 }
565 #endif
566 if (msgs[i].len == 0) {
567 reason = "message with no data";
568 break;
569 }
570 if (i > 0) {
571 if ((msgs[i].flags & IIC_M_NOSTART) != 0 &&
572 (msgs[i - 1].flags & IIC_M_NOSTOP) == 0) {
573 reason = "stop not followed by start";
574 break;
575 }
576 if ((msgs[i - 1].flags & IIC_M_NOSTOP) != 0 &&
577 msgs[i].slave != msgs[i - 1].slave) {
578 reason = "change of slave without stop";
579 break;
580 }
581 if ((msgs[i].flags & IIC_M_NOSTART) != 0 &&
582 (msgs[i].flags & IIC_M_RD) !=
583 (msgs[i - 1].flags & IIC_M_RD)) {
584 reason = "change of direction without repeated"
585 " start";
586 break;
587 }
588 }
589 }
590 if (reason != NULL) {
591 if (bootverbose)
592 device_printf(dev, "%s\n", reason);
593 return (IIC_ENOTSUPP);
594 }
595
596 /* Check if device is already allocated with iicbus_request_bus() */
597 allocated = sx_xlocked(&sc->call_lock) != 0;
598 if (!allocated)
599 sx_xlock(&sc->call_lock);
600
601 /* Debugging - dump registers. */
602 if (ig4_dump) {
603 unit = device_get_unit(dev);
604 if (ig4_dump & (1 << unit)) {
605 ig4_dump &= ~(1 << unit);
606 ig4iic_dump(sc);
607 }
608 }
609
610 /*
611 * Clear any previous abort condition that may have been holding
612 * the txfifo in reset.
613 */
614 reg_read(sc, IG4_REG_CLR_TX_ABORT);
615
616 rpstart = false;
617 error = 0;
618 for (i = 0; i < nmsgs; i++) {
619 if ((msgs[i].flags & IIC_M_NOSTART) == 0) {
620 error = ig4iic_xfer_start(sc, msgs[i].slave, rpstart);
621 } else {
622 if (!sc->slave_valid ||
623 (msgs[i].slave >> 1) != sc->last_slave) {
624 device_printf(dev, "start condition suppressed"
625 "but slave address is not set up");
626 error = EINVAL;
627 break;
628 }
629 rpstart = false;
630 }
631 if (error != 0)
632 break;
633
634 stop = (msgs[i].flags & IIC_M_NOSTOP) == 0;
635 if (msgs[i].flags & IIC_M_RD)
636 error = ig4iic_read(sc, msgs[i].buf, msgs[i].len,
637 rpstart, stop);
638 else
639 error = ig4iic_write(sc, msgs[i].buf, msgs[i].len,
640 rpstart, stop);
641
642 /* Wait for error or stop condition occurred on the I2C bus */
643 if (stop && error == 0) {
644 error = wait_intr(sc, IG4_INTR_STOP_DET);
645 if (error == 0)
646 reg_read(sc, IG4_REG_CLR_INTR);
647 }
648
649 if (error != 0) {
650 /*
651 * Send STOP condition if it's not done yet and flush
652 * both FIFOs. Do a controller soft reset if transfer
653 * abort is failed.
654 */
655 if (ig4iic_xfer_is_started(sc) &&
656 ig4iic_xfer_abort(sc) != 0) {
657 device_printf(sc->dev, "Failed to abort "
658 "transfer. Do the controller reset.\n");
659 ig4iic_set_config(sc, true);
660 } else {
661 while (reg_read(sc, IG4_REG_I2C_STA) &
662 IG4_STATUS_RX_NOTEMPTY)
663 reg_read(sc, IG4_REG_DATA_CMD);
664 reg_read(sc, IG4_REG_TX_ABRT_SOURCE);
665 reg_read(sc, IG4_REG_CLR_INTR);
666 }
667 break;
668 }
669
670 rpstart = !stop;
671 }
672
673 if (!allocated)
674 sx_unlock(&sc->call_lock);
675 return (error);
676 }
677
678 int
679 ig4iic_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
680 {
681 ig4iic_softc_t *sc = device_get_softc(dev);
682 bool allocated;
683
684 allocated = sx_xlocked(&sc->call_lock) != 0;
685 if (!allocated)
686 sx_xlock(&sc->call_lock);
687
688 /* TODO handle speed configuration? */
689 if (oldaddr != NULL)
690 *oldaddr = sc->last_slave << 1;
691 set_slave_addr(sc, addr >> 1);
692 if (addr == IIC_UNKNOWN)
693 sc->slave_valid = false;
694
695 if (!allocated)
696 sx_unlock(&sc->call_lock);
697 return (0);
698 }
699
700 int
701 ig4iic_callback(device_t dev, int index, caddr_t data)
702 {
703 ig4iic_softc_t *sc = device_get_softc(dev);
704 int error = 0;
705 int how;
706
707 switch (index) {
708 case IIC_REQUEST_BUS:
709 /* force polling if ig4iic is requested with IIC_DONTWAIT */
710 how = *(int *)data;
711 if ((how & IIC_WAIT) == 0) {
712 if (sx_try_xlock(&sc->call_lock) == 0)
713 error = IIC_EBUSBSY;
714 else
715 sc->poll = true;
716 } else
717 sx_xlock(&sc->call_lock);
718 break;
719
720 case IIC_RELEASE_BUS:
721 sc->poll = false;
722 sx_unlock(&sc->call_lock);
723 break;
724
725 default:
726 error = errno2iic(EINVAL);
727 }
728
729 return (error);
730 }
731
732 /*
733 * Clock register values can be calculated with following rough equations:
734 * SCL_HCNT = ceil(IC clock rate * tHIGH)
735 * SCL_LCNT = ceil(IC clock rate * tLOW)
736 * SDA_HOLD = ceil(IC clock rate * SDA hold time)
737 * Precise equations take signal's falling, rising and spike suppression
738 * times in to account. They can be found in Synopsys or Intel documentation.
739 *
740 * Here we snarf formulas and defaults from Linux driver to be able to use
741 * timing values provided by Intel LPSS driver "as is".
742 */
743 static int
744 ig4iic_clk_params(const struct ig4_hw *hw, int speed,
745 uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold)
746 {
747 uint32_t thigh, tlow, tf_max; /* nsec */
748 uint32_t sda_fall_time; /* nsec */
749 uint32_t scl_fall_time; /* nsec */
750
751 switch (speed) {
752 case IG4_CTL_SPEED_STD:
753 thigh = IG4_SPEED_STD_THIGH;
754 tlow = IG4_SPEED_STD_TLOW;
755 tf_max = IG4_SPEED_STD_TF_MAX;
756 break;
757
758 case IG4_CTL_SPEED_FAST:
759 thigh = IG4_SPEED_FAST_THIGH;
760 tlow = IG4_SPEED_FAST_TLOW;
761 tf_max = IG4_SPEED_FAST_TF_MAX;
762 break;
763
764 default:
765 return (EINVAL);
766 }
767
768 /* Use slowest falling time defaults to be on the safe side */
769 sda_fall_time = hw->sda_fall_time == 0 ? tf_max : hw->sda_fall_time;
770 *scl_hcnt = (uint16_t)
771 ((hw->ic_clock_rate * (thigh + sda_fall_time) + 500) / 1000 - 3);
772
773 scl_fall_time = hw->scl_fall_time == 0 ? tf_max : hw->scl_fall_time;
774 *scl_lcnt = (uint16_t)
775 ((hw->ic_clock_rate * (tlow + scl_fall_time) + 500) / 1000 - 1);
776
777 /*
778 * There is no "known good" default value for tHD;DAT so keep SDA_HOLD
779 * intact if sda_hold_time value is not provided.
780 */
781 if (hw->sda_hold_time != 0)
782 *sda_hold = (uint16_t)
783 ((hw->ic_clock_rate * hw->sda_hold_time + 500) / 1000);
784
785 return (0);
786 }
787
788 #ifdef DEV_ACPI
789 static ACPI_STATUS
790 ig4iic_acpi_params(ACPI_HANDLE handle, char *method,
791 uint16_t *scl_hcnt, uint16_t *scl_lcnt, uint16_t *sda_hold)
792 {
793 ACPI_BUFFER buf;
794 ACPI_OBJECT *obj, *elems;
795 ACPI_STATUS status;
796
797 buf.Pointer = NULL;
798 buf.Length = ACPI_ALLOCATE_BUFFER;
799
800 status = AcpiEvaluateObject(handle, method, NULL, &buf);
801 if (ACPI_FAILURE(status))
802 return (status);
803
804 status = AE_TYPE;
805 obj = (ACPI_OBJECT *)buf.Pointer;
806 if (obj->Type == ACPI_TYPE_PACKAGE && obj->Package.Count == 3) {
807 elems = obj->Package.Elements;
808 *scl_hcnt = elems[0].Integer.Value & IG4_SCL_CLOCK_MASK;
809 *scl_lcnt = elems[1].Integer.Value & IG4_SCL_CLOCK_MASK;
810 *sda_hold = elems[2].Integer.Value & IG4_SDA_TX_HOLD_MASK;
811 status = AE_OK;
812 }
813
814 AcpiOsFree(obj);
815
816 return (status);
817 }
818 #endif /* DEV_ACPI */
819
820 static void
821 ig4iic_get_config(ig4iic_softc_t *sc)
822 {
823 const struct ig4_hw *hw;
824 uint32_t v;
825 #ifdef DEV_ACPI
826 ACPI_HANDLE handle;
827 #endif
828 /* Fetch default hardware config from controller */
829 sc->cfg.version = reg_read(sc, IG4_REG_COMP_VER);
830 sc->cfg.bus_speed = reg_read(sc, IG4_REG_CTL) & IG4_CTL_SPEED_MASK;
831 sc->cfg.ss_scl_hcnt =
832 reg_read(sc, IG4_REG_SS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
833 sc->cfg.ss_scl_lcnt =
834 reg_read(sc, IG4_REG_SS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
835 sc->cfg.fs_scl_hcnt =
836 reg_read(sc, IG4_REG_FS_SCL_HCNT) & IG4_SCL_CLOCK_MASK;
837 sc->cfg.fs_scl_lcnt =
838 reg_read(sc, IG4_REG_FS_SCL_LCNT) & IG4_SCL_CLOCK_MASK;
839 sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold =
840 reg_read(sc, IG4_REG_SDA_HOLD) & IG4_SDA_TX_HOLD_MASK;
841
842 if (sc->cfg.bus_speed != IG4_CTL_SPEED_STD)
843 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST;
844
845 /* REG_COMP_PARAM1 is not documented in latest Intel specs */
846 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
847 v = reg_read(sc, IG4_REG_COMP_PARAM1);
848 if (IG4_PARAM1_TXFIFO_DEPTH(v) != 0)
849 sc->cfg.txfifo_depth = IG4_PARAM1_TXFIFO_DEPTH(v);
850 if (IG4_PARAM1_RXFIFO_DEPTH(v) != 0)
851 sc->cfg.rxfifo_depth = IG4_PARAM1_RXFIFO_DEPTH(v);
852 } else {
853 /*
854 * Hardware does not allow FIFO Threshold Levels value to be
855 * set larger than the depth of the buffer. If an attempt is
856 * made to do that, the actual value set will be the maximum
857 * depth of the buffer.
858 */
859 v = reg_read(sc, IG4_REG_TX_TL);
860 reg_write(sc, IG4_REG_TX_TL, v | IG4_FIFO_MASK);
861 sc->cfg.txfifo_depth =
862 (reg_read(sc, IG4_REG_TX_TL) & IG4_FIFO_MASK) + 1;
863 reg_write(sc, IG4_REG_TX_TL, v);
864 v = reg_read(sc, IG4_REG_RX_TL);
865 reg_write(sc, IG4_REG_RX_TL, v | IG4_FIFO_MASK);
866 sc->cfg.rxfifo_depth =
867 (reg_read(sc, IG4_REG_RX_TL) & IG4_FIFO_MASK) + 1;
868 reg_write(sc, IG4_REG_RX_TL, v);
869 }
870
871 /* Override hardware config with IC_clock-based counter values */
872 if (ig4_timings < 2 && sc->version < nitems(ig4iic_hw)) {
873 hw = &ig4iic_hw[sc->version];
874 sc->cfg.bus_speed = IG4_CTL_SPEED_FAST;
875 ig4iic_clk_params(hw, IG4_CTL_SPEED_STD, &sc->cfg.ss_scl_hcnt,
876 &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold);
877 ig4iic_clk_params(hw, IG4_CTL_SPEED_FAST, &sc->cfg.fs_scl_hcnt,
878 &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold);
879 if (hw->txfifo_depth != 0)
880 sc->cfg.txfifo_depth = hw->txfifo_depth;
881 if (hw->rxfifo_depth != 0)
882 sc->cfg.rxfifo_depth = hw->rxfifo_depth;
883 } else if (ig4_timings == 2) {
884 /*
885 * Timings of original ig4 driver:
886 * Program based on a 25000 Hz clock. This is a bit of a
887 * hack (obviously). The defaults are 400 and 470 for standard
888 * and 60 and 130 for fast. The defaults for standard fail
889 * utterly (presumably cause an abort) because the clock time
890 * is ~18.8ms by default. This brings it down to ~4ms.
891 */
892 sc->cfg.bus_speed = IG4_CTL_SPEED_STD;
893 sc->cfg.ss_scl_hcnt = sc->cfg.fs_scl_hcnt = 100;
894 sc->cfg.ss_scl_lcnt = sc->cfg.fs_scl_lcnt = 125;
895 if (sc->version == IG4_SKYLAKE)
896 sc->cfg.ss_sda_hold = sc->cfg.fs_sda_hold = 28;
897 }
898
899 #ifdef DEV_ACPI
900 /* Evaluate SSCN and FMCN ACPI methods to fetch timings */
901 if (ig4_timings == 0 && (handle = acpi_get_handle(sc->dev)) != NULL) {
902 ig4iic_acpi_params(handle, "SSCN", &sc->cfg.ss_scl_hcnt,
903 &sc->cfg.ss_scl_lcnt, &sc->cfg.ss_sda_hold);
904 ig4iic_acpi_params(handle, "FMCN", &sc->cfg.fs_scl_hcnt,
905 &sc->cfg.fs_scl_lcnt, &sc->cfg.fs_sda_hold);
906 }
907 #endif
908
909 if (bootverbose) {
910 device_printf(sc->dev, "Controller parameters:\n");
911 printf(" Speed: %s\n",
912 sc->cfg.bus_speed == IG4_CTL_SPEED_STD ? "Std" : "Fast");
913 printf(" Regs: HCNT :LCNT :SDAHLD\n");
914 printf(" Std: 0x%04hx:0x%04hx:0x%04hx\n",
915 sc->cfg.ss_scl_hcnt, sc->cfg.ss_scl_lcnt,
916 sc->cfg.ss_sda_hold);
917 printf(" Fast: 0x%04hx:0x%04hx:0x%04hx\n",
918 sc->cfg.fs_scl_hcnt, sc->cfg.fs_scl_lcnt,
919 sc->cfg.fs_sda_hold);
920 printf(" FIFO: RX:0x%04x: TX:0x%04x\n",
921 sc->cfg.rxfifo_depth, sc->cfg.txfifo_depth);
922 }
923 }
924
925 static int
926 ig4iic_set_config(ig4iic_softc_t *sc, bool reset)
927 {
928 uint32_t v;
929
930 v = reg_read(sc, IG4_REG_DEVIDLE_CTRL);
931 if (IG4_HAS_ADDREGS(sc->version) && (v & IG4_RESTORE_REQUIRED)) {
932 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE | IG4_RESTORE_REQUIRED);
933 reg_write(sc, IG4_REG_DEVIDLE_CTRL, 0);
934 pause("i2crst", 1);
935 reset = true;
936 }
937
938 if ((sc->version == IG4_HASWELL || sc->version == IG4_ATOM) && reset) {
939 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_ASSERT_HSW);
940 reg_write(sc, IG4_REG_RESETS_HSW, IG4_RESETS_DEASSERT_HSW);
941 } else if (IG4_HAS_ADDREGS(sc->version) && reset) {
942 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
943 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_DEASSERT_SKL);
944 }
945
946 if (sc->version == IG4_ATOM)
947 v = reg_read(sc, IG4_REG_COMP_TYPE);
948
949 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
950 v = reg_read(sc, IG4_REG_COMP_PARAM1);
951 v = reg_read(sc, IG4_REG_GENERAL);
952 /*
953 * The content of IG4_REG_GENERAL is different for each
954 * controller version.
955 */
956 if (sc->version == IG4_HASWELL &&
957 (v & IG4_GENERAL_SWMODE) == 0) {
958 v |= IG4_GENERAL_SWMODE;
959 reg_write(sc, IG4_REG_GENERAL, v);
960 v = reg_read(sc, IG4_REG_GENERAL);
961 }
962 }
963
964 if (sc->version == IG4_HASWELL) {
965 v = reg_read(sc, IG4_REG_SW_LTR_VALUE);
966 v = reg_read(sc, IG4_REG_AUTO_LTR_VALUE);
967 } else if (IG4_HAS_ADDREGS(sc->version)) {
968 v = reg_read(sc, IG4_REG_ACTIVE_LTR_VALUE);
969 v = reg_read(sc, IG4_REG_IDLE_LTR_VALUE);
970 }
971
972 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
973 v = reg_read(sc, IG4_REG_COMP_VER);
974 if (v < IG4_COMP_MIN_VER)
975 return(ENXIO);
976 }
977
978 if (set_controller(sc, 0)) {
979 device_printf(sc->dev, "controller error during attach-1\n");
980 return (ENXIO);
981 }
982
983 reg_read(sc, IG4_REG_CLR_INTR);
984 reg_write(sc, IG4_REG_INTR_MASK, 0);
985 sc->intr_mask = 0;
986
987 reg_write(sc, IG4_REG_SS_SCL_HCNT, sc->cfg.ss_scl_hcnt);
988 reg_write(sc, IG4_REG_SS_SCL_LCNT, sc->cfg.ss_scl_lcnt);
989 reg_write(sc, IG4_REG_FS_SCL_HCNT, sc->cfg.fs_scl_hcnt);
990 reg_write(sc, IG4_REG_FS_SCL_LCNT, sc->cfg.fs_scl_lcnt);
991 reg_write(sc, IG4_REG_SDA_HOLD,
992 (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK) == IG4_CTL_SPEED_STD ?
993 sc->cfg.ss_sda_hold : sc->cfg.fs_sda_hold);
994
995 /*
996 * Use a threshold of 1 so we get interrupted on each character,
997 * allowing us to use mtx_sleep() in our poll code. Not perfect
998 * but this is better than using DELAY() for receiving data.
999 *
1000 * See ig4_var.h for details on interrupt handler synchronization.
1001 */
1002 reg_write(sc, IG4_REG_RX_TL, 0);
1003 reg_write(sc, IG4_REG_TX_TL, 0);
1004
1005 reg_write(sc, IG4_REG_CTL,
1006 IG4_CTL_MASTER |
1007 IG4_CTL_SLAVE_DISABLE |
1008 IG4_CTL_RESTARTEN |
1009 (sc->cfg.bus_speed & IG4_CTL_SPEED_MASK));
1010
1011 /* Force setting of the target address on the next transfer */
1012 sc->slave_valid = 0;
1013
1014 return (0);
1015 }
1016
1017 /*
1018 * Called from ig4iic_pci_attach/detach()
1019 */
1020 int
1021 ig4iic_attach(ig4iic_softc_t *sc)
1022 {
1023 int error;
1024
1025 mtx_init(&sc->io_lock, "IG4 I/O lock", NULL, MTX_SPIN);
1026 sx_init(&sc->call_lock, "IG4 call lock");
1027
1028 ig4iic_get_config(sc);
1029
1030 error = ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version));
1031 if (error)
1032 goto done;
1033
1034 sc->iicbus = device_add_child(sc->dev, "iicbus", -1);
1035 if (sc->iicbus == NULL) {
1036 device_printf(sc->dev, "iicbus driver not found\n");
1037 error = ENXIO;
1038 goto done;
1039 }
1040
1041 if (set_controller(sc, IG4_I2C_ENABLE)) {
1042 device_printf(sc->dev, "controller error during attach-2\n");
1043 error = ENXIO;
1044 goto done;
1045 }
1046 if (set_controller(sc, 0)) {
1047 device_printf(sc->dev, "controller error during attach-3\n");
1048 error = ENXIO;
1049 goto done;
1050 }
1051 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_TYPE_MISC | INTR_MPSAFE,
1052 ig4iic_intr, NULL, sc, &sc->intr_handle);
1053 if (error) {
1054 device_printf(sc->dev,
1055 "Unable to setup irq: error %d\n", error);
1056 }
1057
1058 error = bus_generic_attach(sc->dev);
1059 if (error) {
1060 device_printf(sc->dev,
1061 "failed to attach child: error %d\n", error);
1062 }
1063
1064 done:
1065 return (error);
1066 }
1067
1068 int
1069 ig4iic_detach(ig4iic_softc_t *sc)
1070 {
1071 int error;
1072
1073 if (device_is_attached(sc->dev)) {
1074 error = bus_generic_detach(sc->dev);
1075 if (error)
1076 return (error);
1077 }
1078 if (sc->iicbus)
1079 device_delete_child(sc->dev, sc->iicbus);
1080 if (sc->intr_handle)
1081 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_handle);
1082
1083 sx_xlock(&sc->call_lock);
1084
1085 sc->iicbus = NULL;
1086 sc->intr_handle = NULL;
1087 reg_write(sc, IG4_REG_INTR_MASK, 0);
1088 set_controller(sc, 0);
1089
1090 sx_xunlock(&sc->call_lock);
1091
1092 mtx_destroy(&sc->io_lock);
1093 sx_destroy(&sc->call_lock);
1094
1095 return (0);
1096 }
1097
1098 int
1099 ig4iic_suspend(ig4iic_softc_t *sc)
1100 {
1101 int error;
1102
1103 /* suspend all children */
1104 error = bus_generic_suspend(sc->dev);
1105
1106 sx_xlock(&sc->call_lock);
1107 set_controller(sc, 0);
1108 if (IG4_HAS_ADDREGS(sc->version)) {
1109 /*
1110 * Place the device in the idle state, just to be safe
1111 */
1112 reg_write(sc, IG4_REG_DEVIDLE_CTRL, IG4_DEVICE_IDLE);
1113 /*
1114 * Controller can become dysfunctional if I2C lines are pulled
1115 * down when suspend procedure turns off power to I2C device.
1116 * Place device in the reset state to avoid this.
1117 */
1118 reg_write(sc, IG4_REG_RESETS_SKL, IG4_RESETS_ASSERT_SKL);
1119 }
1120 sx_xunlock(&sc->call_lock);
1121
1122 return (error);
1123 }
1124
1125 int ig4iic_resume(ig4iic_softc_t *sc)
1126 {
1127 int error;
1128
1129 sx_xlock(&sc->call_lock);
1130 if (ig4iic_set_config(sc, IG4_HAS_ADDREGS(sc->version)))
1131 device_printf(sc->dev, "controller error during resume\n");
1132 sx_xunlock(&sc->call_lock);
1133
1134 error = bus_generic_resume(sc->dev);
1135
1136 return (error);
1137 }
1138
1139 /*
1140 * Interrupt Operation, see ig4_var.h for locking semantics.
1141 */
1142 static int
1143 ig4iic_intr(void *cookie)
1144 {
1145 ig4iic_softc_t *sc = cookie;
1146 int retval = FILTER_STRAY;
1147
1148 mtx_lock_spin(&sc->io_lock);
1149 /* Ignore stray interrupts */
1150 if (sc->intr_mask != 0 && reg_read(sc, IG4_REG_INTR_STAT) != 0) {
1151 /* Interrupt bits are cleared in wait_intr() loop */
1152 ig4iic_set_intr_mask(sc, 0);
1153 wakeup(sc);
1154 retval = FILTER_HANDLED;
1155 }
1156 mtx_unlock_spin(&sc->io_lock);
1157
1158 return (retval);
1159 }
1160
1161 #define REGDUMP(sc, reg) \
1162 device_printf(sc->dev, " %-23s %08x\n", #reg, reg_read(sc, reg))
1163
1164 static void
1165 ig4iic_dump(ig4iic_softc_t *sc)
1166 {
1167 device_printf(sc->dev, "ig4iic register dump:\n");
1168 REGDUMP(sc, IG4_REG_CTL);
1169 REGDUMP(sc, IG4_REG_TAR_ADD);
1170 REGDUMP(sc, IG4_REG_SS_SCL_HCNT);
1171 REGDUMP(sc, IG4_REG_SS_SCL_LCNT);
1172 REGDUMP(sc, IG4_REG_FS_SCL_HCNT);
1173 REGDUMP(sc, IG4_REG_FS_SCL_LCNT);
1174 REGDUMP(sc, IG4_REG_INTR_STAT);
1175 REGDUMP(sc, IG4_REG_INTR_MASK);
1176 REGDUMP(sc, IG4_REG_RAW_INTR_STAT);
1177 REGDUMP(sc, IG4_REG_RX_TL);
1178 REGDUMP(sc, IG4_REG_TX_TL);
1179 REGDUMP(sc, IG4_REG_I2C_EN);
1180 REGDUMP(sc, IG4_REG_I2C_STA);
1181 REGDUMP(sc, IG4_REG_TXFLR);
1182 REGDUMP(sc, IG4_REG_RXFLR);
1183 REGDUMP(sc, IG4_REG_SDA_HOLD);
1184 REGDUMP(sc, IG4_REG_TX_ABRT_SOURCE);
1185 REGDUMP(sc, IG4_REG_SLV_DATA_NACK);
1186 REGDUMP(sc, IG4_REG_DMA_CTRL);
1187 REGDUMP(sc, IG4_REG_DMA_TDLR);
1188 REGDUMP(sc, IG4_REG_DMA_RDLR);
1189 REGDUMP(sc, IG4_REG_SDA_SETUP);
1190 REGDUMP(sc, IG4_REG_ENABLE_STATUS);
1191 REGDUMP(sc, IG4_REG_COMP_PARAM1);
1192 REGDUMP(sc, IG4_REG_COMP_VER);
1193 if (sc->version == IG4_ATOM) {
1194 REGDUMP(sc, IG4_REG_COMP_TYPE);
1195 REGDUMP(sc, IG4_REG_CLK_PARMS);
1196 }
1197 if (sc->version == IG4_HASWELL || sc->version == IG4_ATOM) {
1198 REGDUMP(sc, IG4_REG_RESETS_HSW);
1199 REGDUMP(sc, IG4_REG_GENERAL);
1200 } else if (sc->version == IG4_SKYLAKE) {
1201 REGDUMP(sc, IG4_REG_RESETS_SKL);
1202 }
1203 if (sc->version == IG4_HASWELL) {
1204 REGDUMP(sc, IG4_REG_SW_LTR_VALUE);
1205 REGDUMP(sc, IG4_REG_AUTO_LTR_VALUE);
1206 } else if (IG4_HAS_ADDREGS(sc->version)) {
1207 REGDUMP(sc, IG4_REG_ACTIVE_LTR_VALUE);
1208 REGDUMP(sc, IG4_REG_IDLE_LTR_VALUE);
1209 }
1210 }
1211 #undef REGDUMP
1212
1213 DRIVER_MODULE(iicbus, ig4iic, iicbus_driver, NULL, NULL);
1214 #ifdef DEV_ACPI
1215 DRIVER_MODULE(acpi_iicbus, ig4iic, acpi_iicbus_driver, NULL, NULL);
1216 #endif
1217 MODULE_DEPEND(ig4iic, iicbus, IICBUS_MINVER, IICBUS_PREFVER, IICBUS_MAXVER);
1218 MODULE_VERSION(ig4iic, 1);
Cache object: 56e484bce267b0b56b0b57e343c6ab51
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