Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ichsmb/ichsmb_pci.c
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1 /*- 2 * ichsmb_pci.c 3 * 4 * Author: Archie Cobbs <archie@freebsd.org> 5 * Copyright (c) 2000 Whistle Communications, Inc. 6 * All rights reserved. 7 * Author: Archie Cobbs <archie@freebsd.org> 8 * 9 * Subject to the following obligations and disclaimer of warranty, use and 10 * redistribution of this software, in source or object code forms, with or 11 * without modifications are expressly permitted by Whistle Communications; 12 * provided, however, that: 13 * 1. Any and all reproductions of the source or object code must include the 14 * copyright notice above and the following disclaimer of warranties; and 15 * 2. No rights are granted, in any manner or form, to use Whistle 16 * Communications, Inc. trademarks, including the mark "WHISTLE 17 * COMMUNICATIONS" on advertising, endorsements, or otherwise except as 18 * such appears in the above copyright notice or in the software. 19 * 20 * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND 21 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO 22 * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE, 23 * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. 25 * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY 26 * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS 27 * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE. 28 * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES 29 * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING 30 * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 31 * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 35 * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY 36 * OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 /* 43 * Support for the SMBus controller logical device which is part of the 44 * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips. 45 */ 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/module.h> 51 #include <sys/errno.h> 52 #include <sys/lock.h> 53 #include <sys/mutex.h> 54 #include <sys/syslog.h> 55 #include <sys/bus.h> 56 57 #include <machine/bus.h> 58 #include <sys/rman.h> 59 #include <machine/resource.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <dev/pci/pcireg.h> 63 64 #include <dev/smbus/smbconf.h> 65 66 #include <dev/ichsmb/ichsmb_var.h> 67 #include <dev/ichsmb/ichsmb_reg.h> 68 69 /* PCI unique identifiers */ 70 #define PCI_VENDOR_INTEL 0x8086 71 #define ID_82801AA 0x2413 72 #define ID_82801AB 0x2423 73 #define ID_82801BA 0x2443 74 #define ID_82801CA 0x2483 75 #define ID_82801DC 0x24C3 76 #define ID_82801EB 0x24D3 77 #define ID_82801FB 0x266A 78 #define ID_82801GB 0x27da 79 #define ID_82801H 0x283e 80 #define ID_82801I 0x2930 81 #define ID_EP80579 0x5032 82 #define ID_82801JI 0x3a30 83 #define ID_82801JD 0x3a60 84 #define ID_PCH 0x3b30 85 #define ID_6300ESB 0x25a4 86 #define ID_631xESB 0x269b 87 #define ID_DH89XXCC 0x2330 88 #define ID_PATSBURG 0x1d22 89 #define ID_CPT 0x1c22 90 #define ID_PPT 0x1e22 91 #define ID_AVOTON 0x1f3c 92 #define ID_COLETOCRK 0x23B0 93 #define ID_LPT 0x8c22 94 #define ID_LPTLP 0x9c22 95 #define ID_WCPT 0x8ca2 96 #define ID_WCPTLP 0x9ca2 97 #define ID_BAYTRAIL 0x0f12 98 #define ID_BRASWELL 0x2292 99 #define ID_WELLSBURG 0x8d22 100 #define ID_SRPT 0xa123 101 #define ID_SRPTLP 0x9d23 102 #define ID_DENVERTON 0x19df 103 #define ID_BROXTON 0x5ad4 104 #define ID_LEWISBURG 0xa1a3 105 #define ID_LEWISBURG2 0xa223 106 #define ID_KABYLAKE 0xa2a3 107 #define ID_CANNONLAKE 0xa323 108 #define ID_COMETLAKE 0x02a3 109 #define ID_COMETLAKE2 0x06a3 110 #define ID_TIGERLAKE 0xa0a3 111 #define ID_TIGERLAKE2 0x43a3 112 #define ID_GEMINILAKE 0x31d4 113 #define ID_ALDERLAKE 0x7aa3 114 #define ID_ALDERLAKE2 0x51a3 115 #define ID_ALDERLAKE3 0x54a3 116 117 static const struct pci_device_table ichsmb_devices[] = { 118 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801AA), 119 PCI_DESCR("Intel 82801AA (ICH) SMBus controller") }, 120 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801AB), 121 PCI_DESCR("Intel 82801AB (ICH0) SMBus controller") }, 122 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801BA), 123 PCI_DESCR("Intel 82801BA (ICH2) SMBus controller") }, 124 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801CA), 125 PCI_DESCR("Intel 82801CA (ICH3) SMBus controller") }, 126 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801DC), 127 PCI_DESCR("Intel 82801DC (ICH4) SMBus controller") }, 128 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801EB), 129 PCI_DESCR("Intel 82801EB (ICH5) SMBus controller") }, 130 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801FB), 131 PCI_DESCR("Intel 82801FB (ICH6) SMBus controller") }, 132 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801GB), 133 PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") }, 134 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801H), 135 PCI_DESCR("Intel 82801H (ICH8) SMBus controller") }, 136 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801I), 137 PCI_DESCR("Intel 82801I (ICH9) SMBus controller") }, 138 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801GB), 139 PCI_DESCR("Intel 82801GB (ICH7) SMBus controller") }, 140 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801H), 141 PCI_DESCR("Intel 82801H (ICH8) SMBus controller") }, 142 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801I), 143 PCI_DESCR("Intel 82801I (ICH9) SMBus controller") }, 144 { PCI_DEV(PCI_VENDOR_INTEL, ID_EP80579), 145 PCI_DESCR("Intel EP80579 SMBus controller") }, 146 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801JI), 147 PCI_DESCR("Intel 82801JI (ICH10) SMBus controller") }, 148 { PCI_DEV(PCI_VENDOR_INTEL, ID_82801JD), 149 PCI_DESCR("Intel 82801JD (ICH10) SMBus controller") }, 150 { PCI_DEV(PCI_VENDOR_INTEL, ID_PCH), 151 PCI_DESCR("Intel PCH SMBus controller") }, 152 { PCI_DEV(PCI_VENDOR_INTEL, ID_6300ESB), 153 PCI_DESCR("Intel 6300ESB (ICH) SMBus controller") }, 154 { PCI_DEV(PCI_VENDOR_INTEL, ID_631xESB), 155 PCI_DESCR("Intel 631xESB/6321ESB (ESB2) SMBus controller") }, 156 { PCI_DEV(PCI_VENDOR_INTEL, ID_DH89XXCC), 157 PCI_DESCR("Intel DH89xxCC SMBus controller") }, 158 { PCI_DEV(PCI_VENDOR_INTEL, ID_PATSBURG), 159 PCI_DESCR("Intel Patsburg SMBus controller") }, 160 { PCI_DEV(PCI_VENDOR_INTEL, ID_CPT), 161 PCI_DESCR("Intel Cougar Point SMBus controller") }, 162 { PCI_DEV(PCI_VENDOR_INTEL, ID_PPT), 163 PCI_DESCR("Intel Panther Point SMBus controller") }, 164 { PCI_DEV(PCI_VENDOR_INTEL, ID_AVOTON), 165 PCI_DESCR("Intel Avoton SMBus controller") }, 166 { PCI_DEV(PCI_VENDOR_INTEL, ID_LPT), 167 PCI_DESCR("Intel Lynx Point SMBus controller") }, 168 { PCI_DEV(PCI_VENDOR_INTEL, ID_LPTLP), 169 PCI_DESCR("Intel Lynx Point-LP SMBus controller") }, 170 { PCI_DEV(PCI_VENDOR_INTEL, ID_WCPT), 171 PCI_DESCR("Intel Wildcat Point SMBus controller") }, 172 { PCI_DEV(PCI_VENDOR_INTEL, ID_WCPTLP), 173 PCI_DESCR("Intel Wildcat Point-LP SMBus controller") }, 174 { PCI_DEV(PCI_VENDOR_INTEL, ID_BAYTRAIL), 175 PCI_DESCR("Intel Baytrail SMBus controller") }, 176 { PCI_DEV(PCI_VENDOR_INTEL, ID_BRASWELL), 177 PCI_DESCR("Intel Braswell SMBus controller") }, 178 { PCI_DEV(PCI_VENDOR_INTEL, ID_COLETOCRK), 179 PCI_DESCR("Intel Coleto Creek SMBus controller") }, 180 { PCI_DEV(PCI_VENDOR_INTEL, ID_WELLSBURG), 181 PCI_DESCR("Intel Wellsburg SMBus controller") }, 182 { PCI_DEV(PCI_VENDOR_INTEL, ID_SRPT), 183 PCI_DESCR("Intel Sunrise Point-H SMBus controller") }, 184 { PCI_DEV(PCI_VENDOR_INTEL, ID_SRPTLP), 185 PCI_DESCR("Intel Sunrise Point-LP SMBus controller") }, 186 { PCI_DEV(PCI_VENDOR_INTEL, ID_DENVERTON), 187 PCI_DESCR("Intel Denverton SMBus controller") }, 188 { PCI_DEV(PCI_VENDOR_INTEL, ID_BROXTON), 189 PCI_DESCR("Intel Broxton SMBus controller") }, 190 { PCI_DEV(PCI_VENDOR_INTEL, ID_LEWISBURG), 191 PCI_DESCR("Intel Lewisburg SMBus controller") }, 192 { PCI_DEV(PCI_VENDOR_INTEL, ID_LEWISBURG2), 193 PCI_DESCR("Intel Lewisburg SMBus controller") }, 194 { PCI_DEV(PCI_VENDOR_INTEL, ID_KABYLAKE), 195 PCI_DESCR("Intel Kaby Lake SMBus controller") }, 196 { PCI_DEV(PCI_VENDOR_INTEL, ID_CANNONLAKE), 197 PCI_DESCR("Intel Cannon Lake SMBus controller") }, 198 { PCI_DEV(PCI_VENDOR_INTEL, ID_COMETLAKE), 199 PCI_DESCR("Intel Comet Lake SMBus controller") }, 200 { PCI_DEV(PCI_VENDOR_INTEL, ID_COMETLAKE2), 201 PCI_DESCR("Intel Comet Lake SMBus controller") }, 202 { PCI_DEV(PCI_VENDOR_INTEL, ID_TIGERLAKE), 203 PCI_DESCR("Intel Tiger Lake SMBus controller") }, 204 { PCI_DEV(PCI_VENDOR_INTEL, ID_TIGERLAKE2), 205 PCI_DESCR("Intel Tiger Lake SMBus controller") }, 206 { PCI_DEV(PCI_VENDOR_INTEL, ID_GEMINILAKE), 207 PCI_DESCR("Intel Gemini Lake SMBus controller") }, 208 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE), 209 PCI_DESCR("Intel Alder Lake SMBus controller") }, 210 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE2), 211 PCI_DESCR("Intel Alder Lake SMBus controller") }, 212 { PCI_DEV(PCI_VENDOR_INTEL, ID_ALDERLAKE3), 213 PCI_DESCR("Intel Alder Lake SMBus controller") }, 214 }; 215 216 /* Internal functions */ 217 static int ichsmb_pci_probe(device_t dev); 218 static int ichsmb_pci_attach(device_t dev); 219 /*Use generic one for now*/ 220 #if 0 221 static int ichsmb_pci_detach(device_t dev); 222 #endif 223 224 /* Device methods */ 225 static device_method_t ichsmb_pci_methods[] = { 226 /* Device interface */ 227 DEVMETHOD(device_probe, ichsmb_pci_probe), 228 DEVMETHOD(device_attach, ichsmb_pci_attach), 229 DEVMETHOD(device_detach, ichsmb_detach), 230 231 /* SMBus methods */ 232 DEVMETHOD(smbus_callback, ichsmb_callback), 233 DEVMETHOD(smbus_quick, ichsmb_quick), 234 DEVMETHOD(smbus_sendb, ichsmb_sendb), 235 DEVMETHOD(smbus_recvb, ichsmb_recvb), 236 DEVMETHOD(smbus_writeb, ichsmb_writeb), 237 DEVMETHOD(smbus_writew, ichsmb_writew), 238 DEVMETHOD(smbus_readb, ichsmb_readb), 239 DEVMETHOD(smbus_readw, ichsmb_readw), 240 DEVMETHOD(smbus_pcall, ichsmb_pcall), 241 DEVMETHOD(smbus_bwrite, ichsmb_bwrite), 242 DEVMETHOD(smbus_bread, ichsmb_bread), 243 244 DEVMETHOD_END 245 }; 246 247 static driver_t ichsmb_pci_driver = { 248 "ichsmb", 249 ichsmb_pci_methods, 250 sizeof(struct ichsmb_softc) 251 }; 252 253 DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, 0, 0); 254 255 static int 256 ichsmb_pci_probe(device_t dev) 257 { 258 const struct pci_device_table *tbl; 259 260 tbl = PCI_MATCH(dev, ichsmb_devices); 261 if (tbl == NULL) 262 return (ENXIO); 263 264 device_set_desc(dev, tbl->descr); 265 return (ichsmb_probe(dev)); 266 } 267 268 static int 269 ichsmb_pci_attach(device_t dev) 270 { 271 const sc_p sc = device_get_softc(dev); 272 int error; 273 274 /* Initialize private state */ 275 bzero(sc, sizeof(*sc)); 276 sc->ich_cmd = -1; 277 sc->dev = dev; 278 279 /* Allocate an I/O range */ 280 sc->io_rid = ICH_SMB_BASE; 281 sc->io_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, 282 &sc->io_rid, 16, RF_ACTIVE); 283 if (sc->io_res == NULL) 284 sc->io_res = bus_alloc_resource_anywhere(dev, SYS_RES_IOPORT, 285 &sc->io_rid, 32, RF_ACTIVE); 286 if (sc->io_res == NULL) { 287 device_printf(dev, "can't map I/O\n"); 288 error = ENXIO; 289 goto fail; 290 } 291 292 /* Allocate interrupt */ 293 sc->irq_rid = 0; 294 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, 295 &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE); 296 if (sc->irq_res == NULL) { 297 device_printf(dev, "can't get IRQ\n"); 298 error = ENXIO; 299 goto fail; 300 } 301 302 /* Enable device */ 303 pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1); 304 305 /* Done */ 306 error = ichsmb_attach(dev); 307 if (error) 308 goto fail; 309 return (0); 310 311 fail: 312 /* Attach failed, release resources */ 313 ichsmb_release_resources(sc); 314 return (error); 315 } 316 317 318 MODULE_DEPEND(ichsmb, pci, 1, 1, 1); 319 MODULE_DEPEND(ichsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER); 320 MODULE_VERSION(ichsmb, 1); 321 PCI_PNP_INFO(ichsmb_devices);
Cache object: 31e8aee21164c05c89cc1d1347855a25
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