The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/dev/ichsmb/ichsmb_pci.c

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    1 /*-
    2  * ichsmb_pci.c
    3  *
    4  * Author: Archie Cobbs <archie@freebsd.org>
    5  * Copyright (c) 2000 Whistle Communications, Inc.
    6  * All rights reserved.
    7  * Author: Archie Cobbs <archie@freebsd.org>
    8  * 
    9  * Subject to the following obligations and disclaimer of warranty, use and
   10  * redistribution of this software, in source or object code forms, with or
   11  * without modifications are expressly permitted by Whistle Communications;
   12  * provided, however, that:
   13  * 1. Any and all reproductions of the source or object code must include the
   14  *    copyright notice above and the following disclaimer of warranties; and
   15  * 2. No rights are granted, in any manner or form, to use Whistle
   16  *    Communications, Inc. trademarks, including the mark "WHISTLE
   17  *    COMMUNICATIONS" on advertising, endorsements, or otherwise except as
   18  *    such appears in the above copyright notice or in the software.
   19  * 
   20  * THIS SOFTWARE IS BEING PROVIDED BY WHISTLE COMMUNICATIONS "AS IS", AND
   21  * TO THE MAXIMUM EXTENT PERMITTED BY LAW, WHISTLE COMMUNICATIONS MAKES NO
   22  * REPRESENTATIONS OR WARRANTIES, EXPRESS OR IMPLIED, REGARDING THIS SOFTWARE,
   23  * INCLUDING WITHOUT LIMITATION, ANY AND ALL IMPLIED WARRANTIES OF
   24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
   25  * WHISTLE COMMUNICATIONS DOES NOT WARRANT, GUARANTEE, OR MAKE ANY
   26  * REPRESENTATIONS REGARDING THE USE OF, OR THE RESULTS OF THE USE OF THIS
   27  * SOFTWARE IN TERMS OF ITS CORRECTNESS, ACCURACY, RELIABILITY OR OTHERWISE.
   28  * IN NO EVENT SHALL WHISTLE COMMUNICATIONS BE LIABLE FOR ANY DAMAGES
   29  * RESULTING FROM OR ARISING OUT OF ANY USE OF THIS SOFTWARE, INCLUDING
   30  * WITHOUT LIMITATION, ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
   31  * PUNITIVE, OR CONSEQUENTIAL DAMAGES, PROCUREMENT OF SUBSTITUTE GOODS OR
   32  * SERVICES, LOSS OF USE, DATA OR PROFITS, HOWEVER CAUSED AND UNDER ANY
   33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   35  * THIS SOFTWARE, EVEN IF WHISTLE COMMUNICATIONS IS ADVISED OF THE POSSIBILITY
   36  * OF SUCH DAMAGE.
   37  */
   38 
   39 #include <sys/cdefs.h>
   40 __FBSDID("$FreeBSD$");
   41 
   42 /*
   43  * Support for the SMBus controller logical device which is part of the
   44  * Intel 81801AA/AB/BA/CA/DC/EB (ICH/ICH[02345]) I/O controller hub chips.
   45  */
   46 
   47 #include <sys/param.h>
   48 #include <sys/systm.h>
   49 #include <sys/kernel.h>
   50 #include <sys/module.h>
   51 #include <sys/errno.h>
   52 #include <sys/lock.h>
   53 #include <sys/mutex.h>
   54 #include <sys/syslog.h>
   55 #include <sys/bus.h>
   56 
   57 #include <machine/bus.h>
   58 #include <sys/rman.h>
   59 #include <machine/resource.h>
   60 
   61 #include <dev/pci/pcivar.h>
   62 #include <dev/pci/pcireg.h>
   63 
   64 #include <dev/smbus/smbconf.h>
   65 
   66 #include <dev/ichsmb/ichsmb_var.h>
   67 #include <dev/ichsmb/ichsmb_reg.h>
   68 
   69 /* PCI unique identifiers */
   70 #define ID_82801AA                      0x24138086
   71 #define ID_82801AB                      0x24238086
   72 #define ID_82801BA                      0x24438086
   73 #define ID_82801CA                      0x24838086
   74 #define ID_82801DC                      0x24C38086
   75 #define ID_82801EB                      0x24D38086
   76 #define ID_6300ESB                      0x25a48086
   77 
   78 #define PCIS_SERIALBUS_SMBUS_PROGIF     0x00
   79 
   80 /* Internal functions */
   81 static int      ichsmb_pci_probe(device_t dev);
   82 static int      ichsmb_pci_attach(device_t dev);
   83 /*Use generic one for now*/
   84 #if 0
   85 static int      ichsmb_pci_detach(device_t dev);
   86 #endif
   87 
   88 /* Device methods */
   89 static device_method_t ichsmb_pci_methods[] = {
   90         /* Device interface */
   91         DEVMETHOD(device_probe, ichsmb_pci_probe),
   92         DEVMETHOD(device_attach, ichsmb_pci_attach),
   93         DEVMETHOD(device_detach, ichsmb_detach),
   94 
   95         /* Bus methods */
   96         DEVMETHOD(bus_print_child, bus_generic_print_child),
   97 
   98         /* SMBus methods */
   99         DEVMETHOD(smbus_callback, ichsmb_callback),
  100         DEVMETHOD(smbus_quick, ichsmb_quick),
  101         DEVMETHOD(smbus_sendb, ichsmb_sendb),
  102         DEVMETHOD(smbus_recvb, ichsmb_recvb),
  103         DEVMETHOD(smbus_writeb, ichsmb_writeb),
  104         DEVMETHOD(smbus_writew, ichsmb_writew),
  105         DEVMETHOD(smbus_readb, ichsmb_readb),
  106         DEVMETHOD(smbus_readw, ichsmb_readw),
  107         DEVMETHOD(smbus_pcall, ichsmb_pcall),
  108         DEVMETHOD(smbus_bwrite, ichsmb_bwrite),
  109         DEVMETHOD(smbus_bread, ichsmb_bread),
  110         { 0, 0 }
  111 };
  112 
  113 static driver_t ichsmb_pci_driver = {
  114         "ichsmb",
  115         ichsmb_pci_methods,
  116         sizeof(struct ichsmb_softc)
  117 };
  118 
  119 static devclass_t ichsmb_pci_devclass;
  120 
  121 DRIVER_MODULE(ichsmb, pci, ichsmb_pci_driver, ichsmb_pci_devclass, 0, 0);
  122 
  123 static int
  124 ichsmb_pci_probe(device_t dev)
  125 {
  126         /* Check PCI identifier */
  127         switch (pci_get_devid(dev)) {
  128         case ID_82801AA:
  129                 device_set_desc(dev, "Intel 82801AA (ICH) SMBus controller");
  130                 break;
  131         case ID_82801AB:
  132                 device_set_desc(dev, "Intel 82801AB (ICH0) SMBus controller");
  133                 break;
  134         case ID_82801BA:
  135                 device_set_desc(dev, "Intel 82801BA (ICH2) SMBus controller");
  136                 break;
  137         case ID_82801CA:
  138                 device_set_desc(dev, "Intel 82801CA (ICH3) SMBus controller");
  139                 break;
  140         case ID_82801DC:
  141                 device_set_desc(dev, "Intel 82801DC (ICH4) SMBus controller");
  142                 break;
  143         case ID_82801EB:
  144                 device_set_desc(dev, "Intel 82801EB (ICH5) SMBus controller");
  145                 break;
  146         case ID_6300ESB:
  147                 device_set_desc(dev, "Intel 6300ESB (ICH) SMBus controller");
  148                 break;
  149         default:
  150                 if (pci_get_class(dev) == PCIC_SERIALBUS
  151                     && pci_get_subclass(dev) == PCIS_SERIALBUS_SMBUS
  152                     && pci_get_progif(dev) == PCIS_SERIALBUS_SMBUS_PROGIF) {
  153                         device_set_desc(dev, "SMBus controller");
  154                         return (BUS_PROBE_DEFAULT); /* XXX */
  155                 }
  156                 return (ENXIO);
  157         }
  158 
  159         /* Done */
  160         return (ichsmb_probe(dev));
  161 }
  162 
  163 static int
  164 ichsmb_pci_attach(device_t dev)
  165 {
  166         const sc_p sc = device_get_softc(dev);
  167         u_int32_t cmd;
  168         int error;
  169 
  170         /* Initialize private state */
  171         bzero(sc, sizeof(*sc));
  172         sc->ich_cmd = -1;
  173         sc->dev = dev;
  174 
  175         /* Allocate an I/O range */
  176         sc->io_rid = ICH_SMB_BASE;
  177         sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
  178             &sc->io_rid, 0, ~0, 16, RF_ACTIVE);
  179         if (sc->io_res == NULL)
  180                 sc->io_res = bus_alloc_resource(dev, SYS_RES_IOPORT,
  181                     &sc->io_rid, 0, ~0, 32, RF_ACTIVE);
  182         if (sc->io_res == NULL) {
  183                 log(LOG_ERR, "%s: can't map I/O\n", device_get_nameunit(dev));
  184                 error = ENXIO;
  185                 goto fail;
  186         }
  187         sc->io_bst = rman_get_bustag(sc->io_res);
  188         sc->io_bsh = rman_get_bushandle(sc->io_res);
  189 
  190         /* Allocate interrupt */
  191         sc->irq_rid = 0;
  192         sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
  193             &sc->irq_rid, RF_ACTIVE | RF_SHAREABLE);
  194         if (sc->irq_res == NULL) {
  195                 log(LOG_ERR, "%s: can't get IRQ\n", device_get_nameunit(dev));
  196                 error = ENXIO;
  197                 goto fail;
  198         }
  199 
  200         /* Set up interrupt handler */
  201         error = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC,
  202             ichsmb_device_intr, sc, &sc->irq_handle);
  203         if (error != 0) {
  204                 log(LOG_ERR, "%s: can't setup irq\n", device_get_nameunit(dev));
  205                 goto fail;
  206         }
  207 
  208         /* Enable I/O mapping */
  209         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
  210         cmd |= PCIM_CMD_PORTEN;
  211         pci_write_config(dev, PCIR_COMMAND, cmd, 4);
  212         cmd = pci_read_config(dev, PCIR_COMMAND, 4);
  213         if ((cmd & PCIM_CMD_PORTEN) == 0) {
  214                 log(LOG_ERR, "%s: can't enable memory map\n",
  215                     device_get_nameunit(dev));
  216                 error = ENXIO;
  217                 goto fail;
  218         }
  219 
  220         /* Enable device */
  221         pci_write_config(dev, ICH_HOSTC, ICH_HOSTC_HST_EN, 1);
  222 
  223         /* Done */
  224         return (ichsmb_attach(dev));
  225 
  226 fail:
  227         /* Attach failed, release resources */
  228         ichsmb_release_resources(sc);
  229         return (error);
  230 }
  231 
  232 
  233 MODULE_DEPEND(ichsmb, pci, 1, 1, 1);
  234 MODULE_DEPEND(ichsmb, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
  235 MODULE_VERSION(ichsmb, 1);

Cache object: a7f32b032f551b1e93daaf9792faaedf


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