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FreeBSD/Linux Kernel Cross Reference
sys/dev/ichwd/ichwd.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004 Texas A&M University 5 * All rights reserved. 6 * 7 * Developer: Wm. Daryl Hawkins 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 /* 32 * Intel ICH Watchdog Timer (WDT) driver 33 * 34 * Originally developed by Wm. Daryl Hawkins of Texas A&M 35 * Heavily modified by <des@FreeBSD.org> 36 * 37 * This is a tricky one. The ICH WDT can't be treated as a regular PCI 38 * device as it's actually an integrated function of the ICH LPC interface 39 * bridge. Detection is also awkward, because we can only infer the 40 * presence of the watchdog timer from the fact that the machine has an 41 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT' 42 * ACPI table (although this driver does not support the ACPI detection 43 * method). 44 * 45 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no 46 * way of knowing if the WDT is permanently disabled (either by the BIOS 47 * or in hardware). 48 * 49 * The WDT is programmed through I/O registers in the ACPI I/O space. 50 * Intel swears it's always at offset 0x60, so we use that. 51 * 52 * For details about the ICH WDT, see Intel Application Note AP-725 53 * (document no. 292273-001). The WDT is also described in the individual 54 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet 55 * (document no. 252516-001) sections 9.10 and 9.11. 56 * 57 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp> 58 * SoC PMC support by Denir Li <denir.li@cas-well.com> 59 */ 60 61 #include <sys/cdefs.h> 62 __FBSDID("$FreeBSD$"); 63 64 #include <sys/param.h> 65 #include <sys/eventhandler.h> 66 #include <sys/kernel.h> 67 #include <sys/module.h> 68 #include <sys/systm.h> 69 #include <sys/bus.h> 70 #include <machine/bus.h> 71 #include <sys/rman.h> 72 #include <machine/resource.h> 73 #include <sys/watchdog.h> 74 75 #include <isa/isavar.h> 76 #include <dev/pci/pcivar.h> 77 78 #include <dev/ichwd/ichwd.h> 79 80 #include <x86/pci_cfgreg.h> 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pci_private.h> 83 84 static struct ichwd_device ichwd_devices[] = { 85 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1, 1 }, 86 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1, 1 }, 87 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2, 1 }, 88 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2, 1 }, 89 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3, 1 }, 90 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3, 1 }, 91 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4, 1 }, 92 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4, 1 }, 93 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5, 1 }, 94 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5, 1 }, 95 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5, 1 }, 96 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5, 1 }, 97 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6, 2 }, 98 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6, 2 }, 99 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6, 2 }, 100 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7, 2 }, 101 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7, 2 }, 102 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7, 2 }, 103 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7, 2 }, 104 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7, 2 }, 105 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8, 2 }, 106 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8, 2 }, 107 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8, 2 }, 108 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8, 2 }, 109 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8, 2 }, 110 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8, 2 }, 111 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9, 2 }, 112 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9, 2 }, 113 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9, 2 }, 114 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9, 2 }, 115 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9, 2 }, 116 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9, 2 }, 117 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10, 2 }, 118 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10, 2 }, 119 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10, 2 }, 120 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10, 2 }, 121 { DEVICEID_PCH, "Intel PCH watchdog timer", 10, 2 }, 122 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10, 2 }, 123 { DEVICEID_P55, "Intel P55 watchdog timer", 10, 2 }, 124 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10, 2 }, 125 { DEVICEID_H55, "Intel H55 watchdog timer", 10, 2 }, 126 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10, 2 }, 127 { DEVICEID_H57, "Intel H57 watchdog timer", 10, 2 }, 128 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10, 2 }, 129 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10, 2 }, 130 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10, 2 }, 131 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10, 2 }, 132 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10, 2 }, 133 { DEVICEID_3400, "Intel 3400 watchdog timer", 10, 2 }, 134 { DEVICEID_3420, "Intel 3420 watchdog timer", 10, 2 }, 135 { DEVICEID_3450, "Intel 3450 watchdog timer", 10, 2 }, 136 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10, 2 }, 137 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10, 2 }, 138 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10, 2 }, 139 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10, 2 }, 140 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10, 2 }, 141 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10, 2 }, 142 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10, 2 }, 143 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10, 2 }, 144 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10, 2 }, 145 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10, 2 }, 146 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10, 2 }, 147 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10, 2 }, 148 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10, 2 }, 149 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10, 2 }, 150 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10, 2 }, 151 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10, 2 }, 152 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10, 2 }, 153 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10, 2 }, 154 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10, 2 }, 155 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10, 2 }, 156 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10, 2 }, 157 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10, 2 }, 158 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10, 2 }, 159 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10, 2 }, 160 { DEVICEID_CPT24, "Intel Cougar Point watchdog timer", 10, 2 }, 161 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10, 2 }, 162 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10, 2 }, 163 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10, 2 }, 164 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10, 2 }, 165 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10, 2 }, 166 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10, 2 }, 167 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10, 2 }, 168 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10, 2 }, 169 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10, 2 }, 170 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10, 2 }, 171 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10, 2 }, 172 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10, 2 }, 173 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10, 2 }, 174 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10, 2 }, 175 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10, 2 }, 176 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10, 2 }, 177 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10, 2 }, 178 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10, 2 }, 179 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10, 2 }, 180 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10, 2 }, 181 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10, 2 }, 182 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10, 2 }, 183 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10, 2 }, 184 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10, 2 }, 185 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10, 2 }, 186 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10, 2 }, 187 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10, 2 }, 188 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10, 2 }, 189 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10, 2 }, 190 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10, 2 }, 191 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10, 2 }, 192 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10, 2 }, 193 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10, 2 }, 194 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10, 2 }, 195 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10, 2 }, 196 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10, 2 }, 197 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10, 2 }, 198 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10, 2 }, 199 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10, 2 }, 200 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10, 2 }, 201 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10, 2 }, 202 { DEVICEID_LPT0, "Intel Lynx Point watchdog timer", 10, 2 }, 203 { DEVICEID_LPT1, "Intel Lynx Point watchdog timer", 10, 2 }, 204 { DEVICEID_LPT2, "Intel Lynx Point watchdog timer", 10, 2 }, 205 { DEVICEID_LPT3, "Intel Lynx Point watchdog timer", 10, 2 }, 206 { DEVICEID_LPT4, "Intel Lynx Point watchdog timer", 10, 2 }, 207 { DEVICEID_LPT5, "Intel Lynx Point watchdog timer", 10, 2 }, 208 { DEVICEID_LPT6, "Intel Lynx Point watchdog timer", 10, 2 }, 209 { DEVICEID_LPT7, "Intel Lynx Point watchdog timer", 10, 2 }, 210 { DEVICEID_LPT8, "Intel Lynx Point watchdog timer", 10, 2 }, 211 { DEVICEID_LPT9, "Intel Lynx Point watchdog timer", 10, 2 }, 212 { DEVICEID_LPT10, "Intel Lynx Point watchdog timer", 10, 2 }, 213 { DEVICEID_LPT11, "Intel Lynx Point watchdog timer", 10, 2 }, 214 { DEVICEID_LPT12, "Intel Lynx Point watchdog timer", 10, 2 }, 215 { DEVICEID_LPT13, "Intel Lynx Point watchdog timer", 10, 2 }, 216 { DEVICEID_LPT14, "Intel Lynx Point watchdog timer", 10, 2 }, 217 { DEVICEID_LPT15, "Intel Lynx Point watchdog timer", 10, 2 }, 218 { DEVICEID_LPT16, "Intel Lynx Point watchdog timer", 10, 2 }, 219 { DEVICEID_LPT17, "Intel Lynx Point watchdog timer", 10, 2 }, 220 { DEVICEID_LPT18, "Intel Lynx Point watchdog timer", 10, 2 }, 221 { DEVICEID_LPT19, "Intel Lynx Point watchdog timer", 10, 2 }, 222 { DEVICEID_LPT20, "Intel Lynx Point watchdog timer", 10, 2 }, 223 { DEVICEID_LPT21, "Intel Lynx Point watchdog timer", 10, 2 }, 224 { DEVICEID_LPT22, "Intel Lynx Point watchdog timer", 10, 2 }, 225 { DEVICEID_LPT23, "Intel Lynx Point watchdog timer", 10, 2 }, 226 { DEVICEID_LPT24, "Intel Lynx Point watchdog timer", 10, 2 }, 227 { DEVICEID_LPT25, "Intel Lynx Point watchdog timer", 10, 2 }, 228 { DEVICEID_LPT26, "Intel Lynx Point watchdog timer", 10, 2 }, 229 { DEVICEID_LPT27, "Intel Lynx Point watchdog timer", 10, 2 }, 230 { DEVICEID_LPT28, "Intel Lynx Point watchdog timer", 10, 2 }, 231 { DEVICEID_LPT29, "Intel Lynx Point watchdog timer", 10, 2 }, 232 { DEVICEID_LPT30, "Intel Lynx Point watchdog timer", 10, 2 }, 233 { DEVICEID_LPT31, "Intel Lynx Point watchdog timer", 10, 2 }, 234 { DEVICEID_WCPT1, "Intel Wildcat Point watchdog timer", 10, 2 }, 235 { DEVICEID_WCPT2, "Intel Wildcat Point watchdog timer", 10, 2 }, 236 { DEVICEID_WCPT3, "Intel Wildcat Point watchdog timer", 10, 2 }, 237 { DEVICEID_WCPT4, "Intel Wildcat Point watchdog timer", 10, 2 }, 238 { DEVICEID_WCPT6, "Intel Wildcat Point watchdog timer", 10, 2 }, 239 { DEVICEID_WBG0, "Intel Wellsburg watchdog timer", 10, 2 }, 240 { DEVICEID_WBG1, "Intel Wellsburg watchdog timer", 10, 2 }, 241 { DEVICEID_WBG2, "Intel Wellsburg watchdog timer", 10, 2 }, 242 { DEVICEID_WBG3, "Intel Wellsburg watchdog timer", 10, 2 }, 243 { DEVICEID_WBG4, "Intel Wellsburg watchdog timer", 10, 2 }, 244 { DEVICEID_WBG5, "Intel Wellsburg watchdog timer", 10, 2 }, 245 { DEVICEID_WBG6, "Intel Wellsburg watchdog timer", 10, 2 }, 246 { DEVICEID_WBG7, "Intel Wellsburg watchdog timer", 10, 2 }, 247 { DEVICEID_WBG8, "Intel Wellsburg watchdog timer", 10, 2 }, 248 { DEVICEID_WBG9, "Intel Wellsburg watchdog timer", 10, 2 }, 249 { DEVICEID_WBG10, "Intel Wellsburg watchdog timer", 10, 2 }, 250 { DEVICEID_WBG11, "Intel Wellsburg watchdog timer", 10, 2 }, 251 { DEVICEID_WBG12, "Intel Wellsburg watchdog timer", 10, 2 }, 252 { DEVICEID_WBG13, "Intel Wellsburg watchdog timer", 10, 2 }, 253 { DEVICEID_WBG14, "Intel Wellsburg watchdog timer", 10, 2 }, 254 { DEVICEID_WBG15, "Intel Wellsburg watchdog timer", 10, 2 }, 255 { DEVICEID_WBG16, "Intel Wellsburg watchdog timer", 10, 2 }, 256 { DEVICEID_WBG17, "Intel Wellsburg watchdog timer", 10, 2 }, 257 { DEVICEID_WBG18, "Intel Wellsburg watchdog timer", 10, 2 }, 258 { DEVICEID_WBG19, "Intel Wellsburg watchdog timer", 10, 2 }, 259 { DEVICEID_WBG20, "Intel Wellsburg watchdog timer", 10, 2 }, 260 { DEVICEID_WBG21, "Intel Wellsburg watchdog timer", 10, 2 }, 261 { DEVICEID_WBG22, "Intel Wellsburg watchdog timer", 10, 2 }, 262 { DEVICEID_WBG23, "Intel Wellsburg watchdog timer", 10, 2 }, 263 { DEVICEID_WBG24, "Intel Wellsburg watchdog timer", 10, 2 }, 264 { DEVICEID_WBG25, "Intel Wellsburg watchdog timer", 10, 2 }, 265 { DEVICEID_WBG26, "Intel Wellsburg watchdog timer", 10, 2 }, 266 { DEVICEID_WBG27, "Intel Wellsburg watchdog timer", 10, 2 }, 267 { DEVICEID_WBG28, "Intel Wellsburg watchdog timer", 10, 2 }, 268 { DEVICEID_WBG29, "Intel Wellsburg watchdog timer", 10, 2 }, 269 { DEVICEID_WBG30, "Intel Wellsburg watchdog timer", 10, 2 }, 270 { DEVICEID_WBG31, "Intel Wellsburg watchdog timer", 10, 2 }, 271 { DEVICEID_LPT_LP0, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 272 { DEVICEID_LPT_LP1, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 273 { DEVICEID_LPT_LP2, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 274 { DEVICEID_LPT_LP3, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 275 { DEVICEID_LPT_LP4, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 276 { DEVICEID_LPT_LP5, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 277 { DEVICEID_LPT_LP6, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 278 { DEVICEID_LPT_LP7, "Intel Lynx Point-LP watchdog timer", 10, 2 }, 279 { DEVICEID_WCPT_LP1, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 280 { DEVICEID_WCPT_LP2, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 281 { DEVICEID_WCPT_LP3, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 282 { DEVICEID_WCPT_LP5, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 283 { DEVICEID_WCPT_LP6, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 284 { DEVICEID_WCPT_LP7, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 285 { DEVICEID_WCPT_LP9, "Intel Wildcat Point-LP watchdog timer", 10, 2 }, 286 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10, 2 }, 287 { DEVICEID_COLETOCRK_LPC, "Intel Coleto Creek watchdog timer", 10, 2 }, 288 { DEVICEID_AVN0, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 289 { DEVICEID_AVN1, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 290 { DEVICEID_AVN2, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 291 { DEVICEID_AVN3, "Intel Avoton/Rangeley SoC watchdog timer",10, 3 }, 292 { DEVICEID_BAYTRAIL, "Intel Bay Trail SoC watchdog timer", 10, 3 }, 293 { DEVICEID_BRASWELL, "Intel Braswell SoC watchdog timer", 10, 3 }, 294 { 0, NULL, 0, 0 }, 295 }; 296 297 static struct ichwd_device ichwd_smb_devices[] = { 298 { DEVICEID_LEWISBURG_SMB, "Lewisburg watchdog timer", 10, 4 }, 299 { DEVICEID_LEWISBURG_SMB_SSKU, "Lewisburg watchdog timer", 10, 4 }, 300 { DEVICEID_CANNON_SMB, "Cannon Lake watchdog timer", 10, 4, PMC_HIDDEN}, 301 { DEVICEID_COMET_SMB, "Comet Lake watchdog timer", 10, 4, PMC_HIDDEN}, 302 { DEVICEID_SRPTLP_SMB, "Sunrise Point-LP watchdog timer", 10, 4 }, 303 { DEVICEID_C3000, "Intel Atom C3000 watchdog timer", 10, 4 }, 304 { 0, NULL, 0, 0 }, 305 }; 306 307 #define ichwd_read_tco_1(sc, off) \ 308 bus_read_1((sc)->tco_res, (off)) 309 #define ichwd_read_tco_2(sc, off) \ 310 bus_read_2((sc)->tco_res, (off)) 311 #define ichwd_read_tco_4(sc, off) \ 312 bus_read_4((sc)->tco_res, (off)) 313 #define ichwd_read_smi_4(sc, off) \ 314 bus_read_4((sc)->smi_res, (off)) 315 #define ichwd_read_gcs_4(sc, off) \ 316 bus_read_4((sc)->gcs_res, (off)) 317 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 318 #define ichwd_read_pmc_4(sc, off) \ 319 bus_read_4((sc)->gcs_res, (off)) 320 #define ichwd_read_gc_4(sc, off) \ 321 bus_read_4((sc)->gc_res, (off)) 322 323 #define ichwd_write_tco_1(sc, off, val) \ 324 bus_write_1((sc)->tco_res, (off), (val)) 325 #define ichwd_write_tco_2(sc, off, val) \ 326 bus_write_2((sc)->tco_res, (off), (val)) 327 #define ichwd_write_tco_4(sc, off, val) \ 328 bus_write_4((sc)->tco_res, (off), (val)) 329 #define ichwd_write_smi_4(sc, off, val) \ 330 bus_write_4((sc)->smi_res, (off), (val)) 331 #define ichwd_write_gcs_4(sc, off, val) \ 332 bus_write_4((sc)->gcs_res, (off), (val)) 333 /* NB: TCO version 3 devices use the gcs_res resource for the PMC register. */ 334 #define ichwd_write_pmc_4(sc, off, val) \ 335 bus_write_4((sc)->gcs_res, (off), (val)) 336 #define ichwd_write_gc_4(sc, off, val) \ 337 bus_write_4((sc)->gc_res, (off), (val)) 338 339 #define ichwd_verbose_printf(dev, ...) \ 340 do { \ 341 if (bootverbose) \ 342 device_printf(dev, __VA_ARGS__);\ 343 } while (0) 344 345 /* 346 * Disable the watchdog timeout SMI handler. 347 * 348 * Apparently, some BIOSes install handlers that reset or disable the 349 * watchdog timer instead of resetting the system, so we disable the SMI 350 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this 351 * from happening. 352 */ 353 static __inline void 354 ichwd_smi_disable(struct ichwd_softc *sc) 355 { 356 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN); 357 } 358 359 /* 360 * Enable the watchdog timeout SMI handler. See above for details. 361 */ 362 static __inline void 363 ichwd_smi_enable(struct ichwd_softc *sc) 364 { 365 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN); 366 } 367 368 /* 369 * Check if the watchdog SMI triggering is enabled. 370 */ 371 static __inline int 372 ichwd_smi_is_enabled(struct ichwd_softc *sc) 373 { 374 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0); 375 } 376 377 /* 378 * Reset the watchdog status bits. 379 */ 380 static __inline void 381 ichwd_sts_reset(struct ichwd_softc *sc) 382 { 383 /* 384 * The watchdog status bits are set to 1 by the hardware to 385 * indicate various conditions. They can be cleared by software 386 * by writing a 1, not a 0. 387 */ 388 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT); 389 /* 390 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must 391 * be done in two separate operations. 392 */ 393 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS); 394 if (sc->tco_version < 4) 395 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS); 396 } 397 398 /* 399 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the 400 * TCO1_CNT register. This is complicated by the need to preserve bit 9 401 * of that same register, and the requirement that all other bits must be 402 * written back as zero. 403 */ 404 static __inline void 405 ichwd_tmr_enable(struct ichwd_softc *sc) 406 { 407 uint16_t cnt; 408 409 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 410 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT); 411 sc->active = 1; 412 ichwd_verbose_printf(sc->device, "timer enabled\n"); 413 } 414 415 /* 416 * Disable the watchdog timer. See above for details. 417 */ 418 static __inline void 419 ichwd_tmr_disable(struct ichwd_softc *sc) 420 { 421 uint16_t cnt; 422 423 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE; 424 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT); 425 sc->active = 0; 426 ichwd_verbose_printf(sc->device, "timer disabled\n"); 427 } 428 429 /* 430 * Reload the watchdog timer: writing anything to any of the lower five 431 * bits of the TCO_RLD register reloads the timer from the last value 432 * written to TCO_TMR. 433 */ 434 static __inline void 435 ichwd_tmr_reload(struct ichwd_softc *sc) 436 { 437 if (sc->tco_version == 1) 438 ichwd_write_tco_1(sc, TCO_RLD, 1); 439 else 440 ichwd_write_tco_2(sc, TCO_RLD, 1); 441 } 442 443 /* 444 * Set the initial timeout value. Note that this must always be followed 445 * by a reload. 446 */ 447 static __inline void 448 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout) 449 { 450 451 if (timeout < TCO_RLD_TMR_MIN) 452 timeout = TCO_RLD_TMR_MIN; 453 454 if (sc->tco_version == 1) { 455 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1); 456 457 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff); 458 if (timeout > TCO_RLD1_TMR_MAX) 459 timeout = TCO_RLD1_TMR_MAX; 460 tmr_val8 |= timeout; 461 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8); 462 } else { 463 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2); 464 465 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff); 466 if (timeout > TCO_RLD2_TMR_MAX) 467 timeout = TCO_RLD2_TMR_MAX; 468 tmr_val16 |= timeout; 469 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16); 470 } 471 472 sc->timeout = timeout; 473 474 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout); 475 } 476 477 static __inline int 478 ichwd_clear_noreboot(struct ichwd_softc *sc) 479 { 480 uint32_t status; 481 int rc = 0; 482 483 /* try to clear the NO_REBOOT bit */ 484 switch (sc->tco_version) { 485 case 1: 486 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 487 status &= ~ICH_GEN_STA_NO_REBOOT; 488 pci_write_config(sc->ich, ICH_GEN_STA, status, 1); 489 status = pci_read_config(sc->ich, ICH_GEN_STA, 1); 490 if (status & ICH_GEN_STA_NO_REBOOT) 491 rc = EIO; 492 break; 493 case 2: 494 status = ichwd_read_gcs_4(sc, 0); 495 status &= ~ICH_GCS_NO_REBOOT; 496 ichwd_write_gcs_4(sc, 0, status); 497 status = ichwd_read_gcs_4(sc, 0); 498 if (status & ICH_GCS_NO_REBOOT) 499 rc = EIO; 500 break; 501 case 3: 502 status = ichwd_read_pmc_4(sc, 0); 503 status &= ~ICH_PMC_NO_REBOOT; 504 ichwd_write_pmc_4(sc, 0, status); 505 status = ichwd_read_pmc_4(sc, 0); 506 if (status & ICH_PMC_NO_REBOOT) 507 rc = EIO; 508 break; 509 case 4: 510 status = ichwd_read_gc_4(sc, 0); 511 status &= ~SMB_GC_NO_REBOOT; 512 ichwd_write_gc_4(sc, 0, status); 513 status = ichwd_read_gc_4(sc, 0); 514 if (status & SMB_GC_NO_REBOOT) 515 rc = EIO; 516 break; 517 default: 518 ichwd_verbose_printf(sc->device, 519 "Unknown TCO Version: %d, can't set NO_REBOOT.\n", 520 sc->tco_version); 521 break; 522 } 523 524 if (rc) 525 device_printf(sc->device, 526 "ICH WDT present but disabled in BIOS or hardware\n"); 527 528 return (rc); 529 } 530 531 /* 532 * Watchdog event handler - called by the framework to enable or disable 533 * the watchdog or change the initial timeout value. 534 */ 535 static void 536 ichwd_event(void *arg, unsigned int cmd, int *error) 537 { 538 struct ichwd_softc *sc = arg; 539 unsigned int timeout; 540 541 /* convert from power-of-two-ns to WDT ticks */ 542 cmd &= WD_INTERVAL; 543 544 if (sc->tco_version == 3) { 545 timeout = ((uint64_t)1 << cmd) / ICHWD_TCO_V3_TICK; 546 } else { 547 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK; 548 } 549 550 if (cmd) { 551 if (!sc->active) 552 ichwd_tmr_enable(sc); 553 if (timeout != sc->timeout) 554 ichwd_tmr_set(sc, timeout); 555 ichwd_tmr_reload(sc); 556 *error = 0; 557 } else { 558 if (sc->active) 559 ichwd_tmr_disable(sc); 560 } 561 } 562 563 static device_t 564 ichwd_find_ich_lpc_bridge(device_t isa, struct ichwd_device **id_p) 565 { 566 struct ichwd_device *id; 567 device_t isab, pci; 568 uint16_t devid; 569 570 /* Check whether parent ISA bridge looks familiar. */ 571 isab = device_get_parent(isa); 572 pci = device_get_parent(isab); 573 if (pci == NULL || device_get_devclass(pci) != devclass_find("pci")) 574 return (NULL); 575 if (pci_get_vendor(isab) != VENDORID_INTEL) 576 return (NULL); 577 devid = pci_get_device(isab); 578 for (id = ichwd_devices; id->desc != NULL; ++id) { 579 if (devid == id->device) { 580 if (id_p != NULL) 581 *id_p = id; 582 return (isab); 583 } 584 } 585 586 return (NULL); 587 } 588 589 static device_t 590 ichwd_find_smb_dev(device_t isa, struct ichwd_device **id_p) 591 { 592 struct ichwd_device *id; 593 device_t isab, smb; 594 uint16_t devid; 595 596 /* 597 * Check if SMBus controller provides TCO configuration. 598 * The controller's device and function are fixed and we expect 599 * it to be on the same bus as ISA bridge. 600 */ 601 isab = device_get_parent(isa); 602 smb = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 4); 603 if (smb == NULL) 604 return (NULL); 605 if (pci_get_vendor(smb) != VENDORID_INTEL) 606 return (NULL); 607 devid = pci_get_device(smb); 608 for (id = ichwd_smb_devices; id->desc != NULL; ++id) { 609 if (devid == id->device) { 610 if (id_p != NULL) 611 *id_p = id; 612 return (smb); 613 } 614 } 615 616 return (NULL); 617 } 618 619 /* 620 * Look for an ICH LPC interface bridge. If one is found, register an 621 * ichwd device. There can be only one. 622 */ 623 static void 624 ichwd_identify(driver_t *driver, device_t parent) 625 { 626 struct ichwd_device *id_p; 627 device_t ich, smb; 628 device_t dev; 629 uint64_t base_address64; 630 uint32_t base_address; 631 uint32_t ctl; 632 int rc; 633 634 ich = ichwd_find_ich_lpc_bridge(parent, &id_p); 635 if (ich == NULL) { 636 smb = ichwd_find_smb_dev(parent, &id_p); 637 if (smb == NULL) 638 return; 639 } 640 641 KASSERT(id_p->tco_version >= 1, 642 ("unexpected TCO version %d", id_p->tco_version)); 643 KASSERT(id_p->tco_version != 4 || smb != NULL, 644 ("could not find PCI SMBus device for TCOv4")); 645 KASSERT(id_p->tco_version >= 4 || ich != NULL, 646 ("could not find PCI LPC bridge device for TCOv1-3")); 647 648 /* good, add child to bus */ 649 if ((dev = device_find_child(parent, driver->name, 0)) == NULL) 650 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0); 651 652 if (dev == NULL) 653 return; 654 655 switch (id_p->tco_version) { 656 case 1: 657 break; 658 case 2: 659 /* get RCBA (root complex base address) */ 660 base_address = pci_read_config(ich, ICH_RCBA, 4); 661 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 662 (base_address & 0xffffc000) + ICH_GCS_OFFSET, 663 ICH_GCS_SIZE); 664 if (rc) 665 ichwd_verbose_printf(dev, 666 "Can not set TCO v%d memory resource for RCBA\n", 667 id_p->tco_version); 668 break; 669 case 3: 670 /* get PBASE (Power Management Controller base address) */ 671 base_address = pci_read_config(ich, ICH_PBASE, 4); 672 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0, 673 (base_address & 0xfffffe00) + ICH_PMC_OFFSET, 674 ICH_PMC_SIZE); 675 if (rc) 676 ichwd_verbose_printf(dev, 677 "Can not set TCO v%d memory resource for PBASE\n", 678 id_p->tco_version); 679 break; 680 case 4: 681 /* Get TCO base address. */ 682 ctl = pci_read_config(smb, ICH_TCOCTL, 4); 683 if ((ctl & ICH_TCOCTL_TCO_BASE_EN) == 0) { 684 ichwd_verbose_printf(dev, 685 "TCO v%d decoding is not enabled\n", 686 id_p->tco_version); 687 break; 688 } 689 base_address = pci_read_config(smb, ICH_TCOBASE, 4); 690 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, 691 base_address & ICH_TCOBASE_ADDRMASK, ICH_TCOBASE_SIZE); 692 if (rc != 0) { 693 ichwd_verbose_printf(dev, 694 "Can not set TCO v%d I/O resource (err = %d)\n", 695 id_p->tco_version, rc); 696 } 697 698 /* 699 * Unhide Primary to Sideband Bridge (P2SB) PCI device, so that 700 * we can discover the base address of Private Configuration 701 * Space via the bridge's BAR. 702 * Then hide back the bridge. 703 */ 704 pci_cfgregwrite(0, 31, 1, 0xe1, 0, 1); 705 base_address64 = pci_cfgregread(0, 31, 1, SBREG_BAR + 4, 4); 706 base_address64 <<= 32; 707 base_address64 |= pci_cfgregread(0, 31, 1, SBREG_BAR, 4); 708 base_address64 &= ~0xfull; 709 pci_cfgregwrite(0, 31, 1, 0xe1, 1, 1); 710 711 /* 712 * No Reboot bit is in General Control register, offset 0xc, 713 * within the SMBus target port, ID 0xc6. 714 */ 715 base_address64 += PCR_REG_OFF(SMB_PORT_ID, SMB_GC_REG); 716 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, base_address64, 717 SMB_GC_SIZE); 718 if (rc != 0) { 719 ichwd_verbose_printf(dev, 720 "Can not set TCO v%d PCR I/O resource (err = %d)\n", 721 id_p->tco_version, rc); 722 } 723 724 break; 725 default: 726 ichwd_verbose_printf(dev, 727 "Can not set unknown TCO v%d memory resource for unknown base address\n", 728 id_p->tco_version); 729 break; 730 } 731 } 732 733 static int 734 ichwd_probe(device_t dev) 735 { 736 struct ichwd_device *id_p; 737 738 /* Do not claim some ISA PnP device by accident. */ 739 if (isa_get_logicalid(dev) != 0) 740 return (ENXIO); 741 742 if (ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p) == NULL && 743 ichwd_find_smb_dev(device_get_parent(dev), &id_p) == NULL) 744 return (ENXIO); 745 746 device_set_desc_copy(dev, id_p->desc); 747 return (0); 748 } 749 750 static int 751 ichwd_smb_attach(device_t dev) 752 { 753 struct ichwd_softc *sc; 754 struct ichwd_device *id_p; 755 device_t isab, pmdev; 756 device_t smb; 757 uint32_t acpi_base; 758 759 sc = device_get_softc(dev); 760 smb = ichwd_find_smb_dev(device_get_parent(dev), &id_p); 761 if (smb == NULL) 762 return (ENXIO); 763 764 sc->ich_version = id_p->ich_version; 765 sc->tco_version = id_p->tco_version; 766 767 /* Allocate TCO control I/O register space. */ 768 sc->tco_rid = 0; 769 sc->tco_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->tco_rid, 770 RF_ACTIVE | RF_SHAREABLE); 771 if (sc->tco_res == NULL) { 772 device_printf(dev, "unable to reserve TCO registers\n"); 773 return (ENXIO); 774 } 775 776 /* 777 * Allocate General Control I/O register in PCH 778 * Private Configuration Space (PCR). 779 */ 780 sc->gc_rid = 1; 781 sc->gc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->gc_rid, 782 RF_ACTIVE | RF_SHAREABLE); 783 if (sc->gc_res == NULL) { 784 device_printf(dev, "unable to reserve hidden P2SB registers\n"); 785 return (ENXIO); 786 } 787 788 /* Get ACPI base address. */ 789 isab = device_get_parent(device_get_parent(dev)); 790 pmdev = pci_find_dbsf(pci_get_domain(isab), pci_get_bus(isab), 31, 2); 791 if (pmdev == NULL) { 792 if (id_p->quirks & PMC_HIDDEN) { 793 /* 794 * Since the PMC is hidden, we take the default value for the 795 * given device, which happens to be the same for the ones we 796 * support. 797 */ 798 acpi_base = ACPI_DEFAULT_CANNON; 799 } else { 800 device_printf(dev, "unable to find Power Management device\n"); 801 return (ENXIO); 802 } 803 } else { 804 acpi_base = pci_read_config(pmdev, ICH_PMBASE, 4) & 0xffffff00; 805 if (acpi_base == 0) { 806 device_printf(dev, "ACPI base address is not set\n"); 807 return (ENXIO); 808 } 809 } 810 811 /* Allocate SMI control I/O register space. */ 812 sc->smi_rid = 2; 813 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 814 acpi_base + SMI_BASE, acpi_base + SMI_BASE + SMI_LEN - 1, SMI_LEN, 815 RF_ACTIVE | RF_SHAREABLE); 816 if (sc->smi_res == NULL) { 817 device_printf(dev, "unable to reserve SMI registers\n"); 818 return (ENXIO); 819 } 820 821 return (0); 822 } 823 824 static int 825 ichwd_lpc_attach(device_t dev) 826 { 827 struct ichwd_softc *sc; 828 struct ichwd_device *id_p; 829 device_t ich; 830 unsigned int pmbase = 0; 831 832 sc = device_get_softc(dev); 833 834 ich = ichwd_find_ich_lpc_bridge(device_get_parent(dev), &id_p); 835 if (ich == NULL) 836 return (ENXIO); 837 838 sc->ich = ich; 839 sc->ich_version = id_p->ich_version; 840 sc->tco_version = id_p->tco_version; 841 842 /* get ACPI base address */ 843 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK; 844 if (pmbase == 0) { 845 device_printf(dev, "ICH PMBASE register is empty\n"); 846 return (ENXIO); 847 } 848 849 /* allocate I/O register space */ 850 sc->smi_rid = 0; 851 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid, 852 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN, 853 RF_ACTIVE | RF_SHAREABLE); 854 if (sc->smi_res == NULL) { 855 device_printf(dev, "unable to reserve SMI registers\n"); 856 return (ENXIO); 857 } 858 859 sc->tco_rid = 1; 860 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid, 861 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN, 862 RF_ACTIVE | RF_SHAREABLE); 863 if (sc->tco_res == NULL) { 864 device_printf(dev, "unable to reserve TCO registers\n"); 865 return (ENXIO); 866 } 867 868 sc->gcs_rid = 0; 869 if (sc->tco_version >= 2) { 870 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY, 871 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE); 872 if (sc->gcs_res == NULL) { 873 device_printf(dev, "unable to reserve GCS registers\n"); 874 return (ENXIO); 875 } 876 } 877 878 return (0); 879 } 880 881 static int 882 ichwd_attach(device_t dev) 883 { 884 struct ichwd_softc *sc; 885 886 sc = device_get_softc(dev); 887 sc->device = dev; 888 889 if (ichwd_lpc_attach(dev) != 0 && ichwd_smb_attach(dev) != 0) 890 goto fail; 891 892 if (ichwd_clear_noreboot(sc) != 0) 893 goto fail; 894 895 /* 896 * Determine if we are coming up after a watchdog-induced reset. Some 897 * BIOSes may clear this bit at bootup, preventing us from reporting 898 * this case on such systems. We clear this bit in ichwd_sts_reset(). 899 */ 900 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0) 901 device_printf(dev, 902 "resuming after hardware watchdog timeout\n"); 903 904 /* reset the watchdog status registers */ 905 ichwd_sts_reset(sc); 906 907 /* make sure the WDT starts out inactive */ 908 ichwd_tmr_disable(sc); 909 910 /* register the watchdog event handler */ 911 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0); 912 913 /* disable the SMI handler */ 914 sc->smi_enabled = ichwd_smi_is_enabled(sc); 915 ichwd_smi_disable(sc); 916 917 return (0); 918 fail: 919 sc = device_get_softc(dev); 920 if (sc->tco_res != NULL) 921 bus_release_resource(dev, SYS_RES_IOPORT, 922 sc->tco_rid, sc->tco_res); 923 if (sc->smi_res != NULL) 924 bus_release_resource(dev, SYS_RES_IOPORT, 925 sc->smi_rid, sc->smi_res); 926 if (sc->gcs_res != NULL) 927 bus_release_resource(sc->ich, SYS_RES_MEMORY, 928 sc->gcs_rid, sc->gcs_res); 929 if (sc->gc_res != NULL) 930 bus_release_resource(dev, SYS_RES_MEMORY, 931 sc->gc_rid, sc->gc_res); 932 933 return (ENXIO); 934 } 935 936 static int 937 ichwd_detach(device_t dev) 938 { 939 struct ichwd_softc *sc; 940 941 sc = device_get_softc(dev); 942 943 /* halt the watchdog timer */ 944 if (sc->active) 945 ichwd_tmr_disable(sc); 946 947 /* enable the SMI handler */ 948 if (sc->smi_enabled != 0) 949 ichwd_smi_enable(sc); 950 951 /* deregister event handler */ 952 if (sc->ev_tag != NULL) 953 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 954 sc->ev_tag = NULL; 955 956 /* reset the watchdog status registers */ 957 ichwd_sts_reset(sc); 958 959 /* deallocate I/O register space */ 960 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res); 961 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res); 962 963 /* deallocate memory resource */ 964 if (sc->gcs_res) 965 bus_release_resource(sc->ich, SYS_RES_MEMORY, sc->gcs_rid, 966 sc->gcs_res); 967 if (sc->gc_res) 968 bus_release_resource(dev, SYS_RES_MEMORY, sc->gc_rid, 969 sc->gc_res); 970 971 return (0); 972 } 973 974 static device_method_t ichwd_methods[] = { 975 DEVMETHOD(device_identify, ichwd_identify), 976 DEVMETHOD(device_probe, ichwd_probe), 977 DEVMETHOD(device_attach, ichwd_attach), 978 DEVMETHOD(device_detach, ichwd_detach), 979 DEVMETHOD(device_shutdown, ichwd_detach), 980 {0,0} 981 }; 982 983 static driver_t ichwd_driver = { 984 "ichwd", 985 ichwd_methods, 986 sizeof(struct ichwd_softc), 987 }; 988 989 DRIVER_MODULE(ichwd, isa, ichwd_driver, NULL, NULL);
Cache object: a9f92d44b304faceb3edadcd8be79e20
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