FreeBSD/Linux Kernel Cross Reference
sys/dev/ichwd/ichwd.c
1 /*-
2 * Copyright (c) 2004 Texas A&M University
3 * All rights reserved.
4 *
5 * Developer: Wm. Daryl Hawkins
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29 /*
30 * Intel ICH Watchdog Timer (WDT) driver
31 *
32 * Originally developed by Wm. Daryl Hawkins of Texas A&M
33 * Heavily modified by <des@FreeBSD.org>
34 *
35 * This is a tricky one. The ICH WDT can't be treated as a regular PCI
36 * device as it's actually an integrated function of the ICH LPC interface
37 * bridge. Detection is also awkward, because we can only infer the
38 * presence of the watchdog timer from the fact that the machine has an
39 * ICH chipset, or, on ACPI 2.x systems, by the presence of the 'WDDT'
40 * ACPI table (although this driver does not support the ACPI detection
41 * method).
42 *
43 * There is one slight problem on non-ACPI or ACPI 1.x systems: we have no
44 * way of knowing if the WDT is permanently disabled (either by the BIOS
45 * or in hardware).
46 *
47 * The WDT is programmed through I/O registers in the ACPI I/O space.
48 * Intel swears it's always at offset 0x60, so we use that.
49 *
50 * For details about the ICH WDT, see Intel Application Note AP-725
51 * (document no. 292273-001). The WDT is also described in the individual
52 * chipset datasheets, e.g. Intel82801EB ICH5 / 82801ER ICH5R Datasheet
53 * (document no. 252516-001) sections 9.10 and 9.11.
54 *
55 * ICH6/7/8 support by Takeharu KATO <takeharu1219@ybb.ne.jp>
56 */
57
58 #include <sys/cdefs.h>
59 __FBSDID("$FreeBSD: releng/8.4/sys/dev/ichwd/ichwd.c 231154 2012-02-07 19:41:21Z jhb $");
60
61 #include <sys/param.h>
62 #include <sys/kernel.h>
63 #include <sys/module.h>
64 #include <sys/systm.h>
65 #include <sys/bus.h>
66 #include <machine/bus.h>
67 #include <sys/rman.h>
68 #include <machine/resource.h>
69 #include <sys/watchdog.h>
70
71 #include <isa/isavar.h>
72 #include <dev/pci/pcivar.h>
73
74 #include <dev/ichwd/ichwd.h>
75
76 static struct ichwd_device ichwd_devices[] = {
77 { DEVICEID_82801AA, "Intel 82801AA watchdog timer", 1 },
78 { DEVICEID_82801AB, "Intel 82801AB watchdog timer", 1 },
79 { DEVICEID_82801BA, "Intel 82801BA watchdog timer", 2 },
80 { DEVICEID_82801BAM, "Intel 82801BAM watchdog timer", 2 },
81 { DEVICEID_82801CA, "Intel 82801CA watchdog timer", 3 },
82 { DEVICEID_82801CAM, "Intel 82801CAM watchdog timer", 3 },
83 { DEVICEID_82801DB, "Intel 82801DB watchdog timer", 4 },
84 { DEVICEID_82801DBM, "Intel 82801DBM watchdog timer", 4 },
85 { DEVICEID_82801E, "Intel 82801E watchdog timer", 5 },
86 { DEVICEID_82801EB, "Intel 82801EB watchdog timer", 5 },
87 { DEVICEID_82801EBR, "Intel 82801EB/ER watchdog timer", 5 },
88 { DEVICEID_6300ESB, "Intel 6300ESB watchdog timer", 5 },
89 { DEVICEID_82801FBR, "Intel 82801FB/FR watchdog timer", 6 },
90 { DEVICEID_ICH6M, "Intel ICH6M watchdog timer", 6 },
91 { DEVICEID_ICH6W, "Intel ICH6W watchdog timer", 6 },
92 { DEVICEID_ICH7, "Intel ICH7 watchdog timer", 7 },
93 { DEVICEID_ICH7DH, "Intel ICH7DH watchdog timer", 7 },
94 { DEVICEID_ICH7M, "Intel ICH7M watchdog timer", 7 },
95 { DEVICEID_ICH7MDH, "Intel ICH7MDH watchdog timer", 7 },
96 { DEVICEID_NM10, "Intel NM10 watchdog timer", 7 },
97 { DEVICEID_ICH8, "Intel ICH8 watchdog timer", 8 },
98 { DEVICEID_ICH8DH, "Intel ICH8DH watchdog timer", 8 },
99 { DEVICEID_ICH8DO, "Intel ICH8DO watchdog timer", 8 },
100 { DEVICEID_ICH8M, "Intel ICH8M watchdog timer", 8 },
101 { DEVICEID_ICH8ME, "Intel ICH8M-E watchdog timer", 8 },
102 { DEVICEID_63XXESB, "Intel 63XXESB watchdog timer", 8 },
103 { DEVICEID_ICH9, "Intel ICH9 watchdog timer", 9 },
104 { DEVICEID_ICH9DH, "Intel ICH9DH watchdog timer", 9 },
105 { DEVICEID_ICH9DO, "Intel ICH9DO watchdog timer", 9 },
106 { DEVICEID_ICH9M, "Intel ICH9M watchdog timer", 9 },
107 { DEVICEID_ICH9ME, "Intel ICH9M-E watchdog timer", 9 },
108 { DEVICEID_ICH9R, "Intel ICH9R watchdog timer", 9 },
109 { DEVICEID_ICH10, "Intel ICH10 watchdog timer", 10 },
110 { DEVICEID_ICH10D, "Intel ICH10D watchdog timer", 10 },
111 { DEVICEID_ICH10DO, "Intel ICH10DO watchdog timer", 10 },
112 { DEVICEID_ICH10R, "Intel ICH10R watchdog timer", 10 },
113 { DEVICEID_PCH, "Intel PCH watchdog timer", 10 },
114 { DEVICEID_PCHM, "Intel PCH watchdog timer", 10 },
115 { DEVICEID_P55, "Intel P55 watchdog timer", 10 },
116 { DEVICEID_PM55, "Intel PM55 watchdog timer", 10 },
117 { DEVICEID_H55, "Intel H55 watchdog timer", 10 },
118 { DEVICEID_QM57, "Intel QM57 watchdog timer", 10 },
119 { DEVICEID_H57, "Intel H57 watchdog timer", 10 },
120 { DEVICEID_HM55, "Intel HM55 watchdog timer", 10 },
121 { DEVICEID_Q57, "Intel Q57 watchdog timer", 10 },
122 { DEVICEID_HM57, "Intel HM57 watchdog timer", 10 },
123 { DEVICEID_PCHMSFF, "Intel PCHMSFF watchdog timer", 10 },
124 { DEVICEID_QS57, "Intel QS57 watchdog timer", 10 },
125 { DEVICEID_3400, "Intel 3400 watchdog timer", 10 },
126 { DEVICEID_3420, "Intel 3420 watchdog timer", 10 },
127 { DEVICEID_3450, "Intel 3450 watchdog timer", 10 },
128 { DEVICEID_CPT0, "Intel Cougar Point watchdog timer", 10 },
129 { DEVICEID_CPT1, "Intel Cougar Point watchdog timer", 10 },
130 { DEVICEID_CPT2, "Intel Cougar Point watchdog timer", 10 },
131 { DEVICEID_CPT3, "Intel Cougar Point watchdog timer", 10 },
132 { DEVICEID_CPT4, "Intel Cougar Point watchdog timer", 10 },
133 { DEVICEID_CPT5, "Intel Cougar Point watchdog timer", 10 },
134 { DEVICEID_CPT6, "Intel Cougar Point watchdog timer", 10 },
135 { DEVICEID_CPT7, "Intel Cougar Point watchdog timer", 10 },
136 { DEVICEID_CPT8, "Intel Cougar Point watchdog timer", 10 },
137 { DEVICEID_CPT9, "Intel Cougar Point watchdog timer", 10 },
138 { DEVICEID_CPT10, "Intel Cougar Point watchdog timer", 10 },
139 { DEVICEID_CPT11, "Intel Cougar Point watchdog timer", 10 },
140 { DEVICEID_CPT12, "Intel Cougar Point watchdog timer", 10 },
141 { DEVICEID_CPT13, "Intel Cougar Point watchdog timer", 10 },
142 { DEVICEID_CPT14, "Intel Cougar Point watchdog timer", 10 },
143 { DEVICEID_CPT15, "Intel Cougar Point watchdog timer", 10 },
144 { DEVICEID_CPT16, "Intel Cougar Point watchdog timer", 10 },
145 { DEVICEID_CPT17, "Intel Cougar Point watchdog timer", 10 },
146 { DEVICEID_CPT18, "Intel Cougar Point watchdog timer", 10 },
147 { DEVICEID_CPT19, "Intel Cougar Point watchdog timer", 10 },
148 { DEVICEID_CPT20, "Intel Cougar Point watchdog timer", 10 },
149 { DEVICEID_CPT21, "Intel Cougar Point watchdog timer", 10 },
150 { DEVICEID_CPT22, "Intel Cougar Point watchdog timer", 10 },
151 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 },
152 { DEVICEID_CPT23, "Intel Cougar Point watchdog timer", 10 },
153 { DEVICEID_CPT25, "Intel Cougar Point watchdog timer", 10 },
154 { DEVICEID_CPT26, "Intel Cougar Point watchdog timer", 10 },
155 { DEVICEID_CPT27, "Intel Cougar Point watchdog timer", 10 },
156 { DEVICEID_CPT28, "Intel Cougar Point watchdog timer", 10 },
157 { DEVICEID_CPT29, "Intel Cougar Point watchdog timer", 10 },
158 { DEVICEID_CPT30, "Intel Cougar Point watchdog timer", 10 },
159 { DEVICEID_CPT31, "Intel Cougar Point watchdog timer", 10 },
160 { DEVICEID_PATSBURG_LPC1, "Intel Patsburg watchdog timer", 10 },
161 { DEVICEID_PATSBURG_LPC2, "Intel Patsburg watchdog timer", 10 },
162 { DEVICEID_PPT0, "Intel Panther Point watchdog timer", 10 },
163 { DEVICEID_PPT1, "Intel Panther Point watchdog timer", 10 },
164 { DEVICEID_PPT2, "Intel Panther Point watchdog timer", 10 },
165 { DEVICEID_PPT3, "Intel Panther Point watchdog timer", 10 },
166 { DEVICEID_PPT4, "Intel Panther Point watchdog timer", 10 },
167 { DEVICEID_PPT5, "Intel Panther Point watchdog timer", 10 },
168 { DEVICEID_PPT6, "Intel Panther Point watchdog timer", 10 },
169 { DEVICEID_PPT7, "Intel Panther Point watchdog timer", 10 },
170 { DEVICEID_PPT8, "Intel Panther Point watchdog timer", 10 },
171 { DEVICEID_PPT9, "Intel Panther Point watchdog timer", 10 },
172 { DEVICEID_PPT10, "Intel Panther Point watchdog timer", 10 },
173 { DEVICEID_PPT11, "Intel Panther Point watchdog timer", 10 },
174 { DEVICEID_PPT12, "Intel Panther Point watchdog timer", 10 },
175 { DEVICEID_PPT13, "Intel Panther Point watchdog timer", 10 },
176 { DEVICEID_PPT14, "Intel Panther Point watchdog timer", 10 },
177 { DEVICEID_PPT15, "Intel Panther Point watchdog timer", 10 },
178 { DEVICEID_PPT16, "Intel Panther Point watchdog timer", 10 },
179 { DEVICEID_PPT17, "Intel Panther Point watchdog timer", 10 },
180 { DEVICEID_PPT18, "Intel Panther Point watchdog timer", 10 },
181 { DEVICEID_PPT19, "Intel Panther Point watchdog timer", 10 },
182 { DEVICEID_PPT20, "Intel Panther Point watchdog timer", 10 },
183 { DEVICEID_PPT21, "Intel Panther Point watchdog timer", 10 },
184 { DEVICEID_PPT22, "Intel Panther Point watchdog timer", 10 },
185 { DEVICEID_PPT23, "Intel Panther Point watchdog timer", 10 },
186 { DEVICEID_PPT24, "Intel Panther Point watchdog timer", 10 },
187 { DEVICEID_PPT25, "Intel Panther Point watchdog timer", 10 },
188 { DEVICEID_PPT26, "Intel Panther Point watchdog timer", 10 },
189 { DEVICEID_PPT27, "Intel Panther Point watchdog timer", 10 },
190 { DEVICEID_PPT28, "Intel Panther Point watchdog timer", 10 },
191 { DEVICEID_PPT29, "Intel Panther Point watchdog timer", 10 },
192 { DEVICEID_PPT30, "Intel Panther Point watchdog timer", 10 },
193 { DEVICEID_PPT31, "Intel Panther Point watchdog timer", 10 },
194 { DEVICEID_DH89XXCC_LPC, "Intel DH89xxCC watchdog timer", 10 },
195 { 0, NULL, 0 },
196 };
197
198 static devclass_t ichwd_devclass;
199
200 #define ichwd_read_tco_1(sc, off) \
201 bus_read_1((sc)->tco_res, (off))
202 #define ichwd_read_tco_2(sc, off) \
203 bus_read_2((sc)->tco_res, (off))
204 #define ichwd_read_tco_4(sc, off) \
205 bus_read_4((sc)->tco_res, (off))
206 #define ichwd_read_smi_4(sc, off) \
207 bus_read_4((sc)->smi_res, (off))
208 #define ichwd_read_gcs_4(sc, off) \
209 bus_read_4((sc)->gcs_res, (off))
210
211 #define ichwd_write_tco_1(sc, off, val) \
212 bus_write_1((sc)->tco_res, (off), (val))
213 #define ichwd_write_tco_2(sc, off, val) \
214 bus_write_2((sc)->tco_res, (off), (val))
215 #define ichwd_write_tco_4(sc, off, val) \
216 bus_write_4((sc)->tco_res, (off), (val))
217 #define ichwd_write_smi_4(sc, off, val) \
218 bus_write_4((sc)->smi_res, (off), (val))
219 #define ichwd_write_gcs_4(sc, off, val) \
220 bus_write_4((sc)->gcs_res, (off), (val))
221
222 #define ichwd_verbose_printf(dev, ...) \
223 do { \
224 if (bootverbose) \
225 device_printf(dev, __VA_ARGS__);\
226 } while (0)
227
228 /*
229 * Disable the watchdog timeout SMI handler.
230 *
231 * Apparently, some BIOSes install handlers that reset or disable the
232 * watchdog timer instead of resetting the system, so we disable the SMI
233 * (by clearing the SMI_TCO_EN bit of the SMI_EN register) to prevent this
234 * from happening.
235 */
236 static __inline void
237 ichwd_smi_disable(struct ichwd_softc *sc)
238 {
239 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) & ~SMI_TCO_EN);
240 }
241
242 /*
243 * Enable the watchdog timeout SMI handler. See above for details.
244 */
245 static __inline void
246 ichwd_smi_enable(struct ichwd_softc *sc)
247 {
248 ichwd_write_smi_4(sc, SMI_EN, ichwd_read_smi_4(sc, SMI_EN) | SMI_TCO_EN);
249 }
250
251 /*
252 * Check if the watchdog SMI triggering is enabled.
253 */
254 static __inline int
255 ichwd_smi_is_enabled(struct ichwd_softc *sc)
256 {
257 return ((ichwd_read_smi_4(sc, SMI_EN) & SMI_TCO_EN) != 0);
258 }
259
260 /*
261 * Reset the watchdog status bits.
262 */
263 static __inline void
264 ichwd_sts_reset(struct ichwd_softc *sc)
265 {
266 /*
267 * The watchdog status bits are set to 1 by the hardware to
268 * indicate various conditions. They can be cleared by software
269 * by writing a 1, not a 0.
270 */
271 ichwd_write_tco_2(sc, TCO1_STS, TCO_TIMEOUT);
272 /*
273 * According to Intel's docs, clearing SECOND_TO_STS and BOOT_STS must
274 * be done in two separate operations.
275 */
276 ichwd_write_tco_2(sc, TCO2_STS, TCO_SECOND_TO_STS);
277 ichwd_write_tco_2(sc, TCO2_STS, TCO_BOOT_STS);
278 }
279
280 /*
281 * Enable the watchdog timer by clearing the TCO_TMR_HALT bit in the
282 * TCO1_CNT register. This is complicated by the need to preserve bit 9
283 * of that same register, and the requirement that all other bits must be
284 * written back as zero.
285 */
286 static __inline void
287 ichwd_tmr_enable(struct ichwd_softc *sc)
288 {
289 uint16_t cnt;
290
291 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
292 ichwd_write_tco_2(sc, TCO1_CNT, cnt & ~TCO_TMR_HALT);
293 sc->active = 1;
294 ichwd_verbose_printf(sc->device, "timer enabled\n");
295 }
296
297 /*
298 * Disable the watchdog timer. See above for details.
299 */
300 static __inline void
301 ichwd_tmr_disable(struct ichwd_softc *sc)
302 {
303 uint16_t cnt;
304
305 cnt = ichwd_read_tco_2(sc, TCO1_CNT) & TCO_CNT_PRESERVE;
306 ichwd_write_tco_2(sc, TCO1_CNT, cnt | TCO_TMR_HALT);
307 sc->active = 0;
308 ichwd_verbose_printf(sc->device, "timer disabled\n");
309 }
310
311 /*
312 * Reload the watchdog timer: writing anything to any of the lower five
313 * bits of the TCO_RLD register reloads the timer from the last value
314 * written to TCO_TMR.
315 */
316 static __inline void
317 ichwd_tmr_reload(struct ichwd_softc *sc)
318 {
319 if (sc->ich_version <= 5)
320 ichwd_write_tco_1(sc, TCO_RLD, 1);
321 else
322 ichwd_write_tco_2(sc, TCO_RLD, 1);
323
324 ichwd_verbose_printf(sc->device, "timer reloaded\n");
325 }
326
327 /*
328 * Set the initial timeout value. Note that this must always be followed
329 * by a reload.
330 */
331 static __inline void
332 ichwd_tmr_set(struct ichwd_softc *sc, unsigned int timeout)
333 {
334
335 if (timeout < TCO_RLD_TMR_MIN)
336 timeout = TCO_RLD_TMR_MIN;
337
338 if (sc->ich_version <= 5) {
339 uint8_t tmr_val8 = ichwd_read_tco_1(sc, TCO_TMR1);
340
341 tmr_val8 &= (~TCO_RLD1_TMR_MAX & 0xff);
342 if (timeout > TCO_RLD1_TMR_MAX)
343 timeout = TCO_RLD1_TMR_MAX;
344 tmr_val8 |= timeout;
345 ichwd_write_tco_1(sc, TCO_TMR1, tmr_val8);
346 } else {
347 uint16_t tmr_val16 = ichwd_read_tco_2(sc, TCO_TMR2);
348
349 tmr_val16 &= (~TCO_RLD2_TMR_MAX & 0xffff);
350 if (timeout > TCO_RLD2_TMR_MAX)
351 timeout = TCO_RLD2_TMR_MAX;
352 tmr_val16 |= timeout;
353 ichwd_write_tco_2(sc, TCO_TMR2, tmr_val16);
354 }
355
356 sc->timeout = timeout;
357
358 ichwd_verbose_printf(sc->device, "timeout set to %u ticks\n", timeout);
359 }
360
361 static __inline int
362 ichwd_clear_noreboot(struct ichwd_softc *sc)
363 {
364 uint32_t status;
365 int rc = 0;
366
367 /* try to clear the NO_REBOOT bit */
368 if (sc->ich_version <= 5) {
369 status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
370 status &= ~ICH_GEN_STA_NO_REBOOT;
371 pci_write_config(sc->ich, ICH_GEN_STA, status, 1);
372 status = pci_read_config(sc->ich, ICH_GEN_STA, 1);
373 if (status & ICH_GEN_STA_NO_REBOOT)
374 rc = EIO;
375 } else {
376 status = ichwd_read_gcs_4(sc, 0);
377 status &= ~ICH_GCS_NO_REBOOT;
378 ichwd_write_gcs_4(sc, 0, status);
379 status = ichwd_read_gcs_4(sc, 0);
380 if (status & ICH_GCS_NO_REBOOT)
381 rc = EIO;
382 }
383
384 if (rc)
385 device_printf(sc->device,
386 "ICH WDT present but disabled in BIOS or hardware\n");
387
388 return (rc);
389 }
390
391 /*
392 * Watchdog event handler - called by the framework to enable or disable
393 * the watchdog or change the initial timeout value.
394 */
395 static void
396 ichwd_event(void *arg, unsigned int cmd, int *error)
397 {
398 struct ichwd_softc *sc = arg;
399 unsigned int timeout;
400
401 /* convert from power-of-two-ns to WDT ticks */
402 cmd &= WD_INTERVAL;
403 timeout = ((uint64_t)1 << cmd) / ICHWD_TICK;
404 if (cmd) {
405 if (!sc->active)
406 ichwd_tmr_enable(sc);
407 if (timeout != sc->timeout)
408 ichwd_tmr_set(sc, timeout);
409 ichwd_tmr_reload(sc);
410 *error = 0;
411 } else {
412 if (sc->active)
413 ichwd_tmr_disable(sc);
414 }
415 }
416
417 static device_t
418 ichwd_find_ich_lpc_bridge(struct ichwd_device **id_p)
419 {
420 struct ichwd_device *id;
421 device_t ich = NULL;
422
423 /* look for an ICH LPC interface bridge */
424 for (id = ichwd_devices; id->desc != NULL; ++id)
425 if ((ich = pci_find_device(VENDORID_INTEL, id->device)) != NULL)
426 break;
427
428 if (ich == NULL)
429 return (NULL);
430
431 ichwd_verbose_printf(ich, "found ICH%d or equivalent chipset: %s\n",
432 id->version, id->desc);
433
434 if (id_p)
435 *id_p = id;
436
437 return (ich);
438 }
439
440 /*
441 * Look for an ICH LPC interface bridge. If one is found, register an
442 * ichwd device. There can be only one.
443 */
444 static void
445 ichwd_identify(driver_t *driver, device_t parent)
446 {
447 struct ichwd_device *id_p;
448 device_t ich = NULL;
449 device_t dev;
450 uint32_t rcba;
451 int rc;
452
453 ich = ichwd_find_ich_lpc_bridge(&id_p);
454 if (ich == NULL)
455 return;
456
457 /* good, add child to bus */
458 if ((dev = device_find_child(parent, driver->name, 0)) == NULL)
459 dev = BUS_ADD_CHILD(parent, 0, driver->name, 0);
460
461 if (dev == NULL)
462 return;
463
464 device_set_desc_copy(dev, id_p->desc);
465
466 if (id_p->version >= 6) {
467 /* get RCBA (root complex base address) */
468 rcba = pci_read_config(ich, ICH_RCBA, 4);
469 rc = bus_set_resource(ich, SYS_RES_MEMORY, 0,
470 (rcba & 0xffffc000) + ICH_GCS_OFFSET, ICH_GCS_SIZE);
471 if (rc)
472 ichwd_verbose_printf(dev,
473 "Can not set memory resource for RCBA\n");
474 }
475 }
476
477 static int
478 ichwd_probe(device_t dev)
479 {
480
481 /* Do not claim some ISA PnP device by accident. */
482 if (isa_get_logicalid(dev) != 0)
483 return (ENXIO);
484 return (0);
485 }
486
487 static int
488 ichwd_attach(device_t dev)
489 {
490 struct ichwd_softc *sc;
491 struct ichwd_device *id_p;
492 device_t ich;
493 unsigned int pmbase = 0;
494
495 sc = device_get_softc(dev);
496 sc->device = dev;
497
498 ich = ichwd_find_ich_lpc_bridge(&id_p);
499 if (ich == NULL) {
500 device_printf(sc->device, "Can not find ICH device.\n");
501 goto fail;
502 }
503 sc->ich = ich;
504 sc->ich_version = id_p->version;
505
506 /* get ACPI base address */
507 pmbase = pci_read_config(ich, ICH_PMBASE, 2) & ICH_PMBASE_MASK;
508 if (pmbase == 0) {
509 device_printf(dev, "ICH PMBASE register is empty\n");
510 goto fail;
511 }
512
513 /* allocate I/O register space */
514 sc->smi_rid = 0;
515 sc->smi_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->smi_rid,
516 pmbase + SMI_BASE, pmbase + SMI_BASE + SMI_LEN - 1, SMI_LEN,
517 RF_ACTIVE | RF_SHAREABLE);
518 if (sc->smi_res == NULL) {
519 device_printf(dev, "unable to reserve SMI registers\n");
520 goto fail;
521 }
522
523 sc->tco_rid = 1;
524 sc->tco_res = bus_alloc_resource(dev, SYS_RES_IOPORT, &sc->tco_rid,
525 pmbase + TCO_BASE, pmbase + TCO_BASE + TCO_LEN - 1, TCO_LEN,
526 RF_ACTIVE | RF_SHAREABLE);
527 if (sc->tco_res == NULL) {
528 device_printf(dev, "unable to reserve TCO registers\n");
529 goto fail;
530 }
531
532 sc->gcs_rid = 0;
533 if (sc->ich_version >= 6) {
534 sc->gcs_res = bus_alloc_resource_any(ich, SYS_RES_MEMORY,
535 &sc->gcs_rid, RF_ACTIVE|RF_SHAREABLE);
536 if (sc->gcs_res == NULL) {
537 device_printf(dev, "unable to reserve GCS registers\n");
538 goto fail;
539 }
540 }
541
542 if (ichwd_clear_noreboot(sc) != 0)
543 goto fail;
544
545 device_printf(dev, "%s (ICH%d or equivalent)\n",
546 device_get_desc(dev), sc->ich_version);
547
548 /*
549 * Determine if we are coming up after a watchdog-induced reset. Some
550 * BIOSes may clear this bit at bootup, preventing us from reporting
551 * this case on such systems. We clear this bit in ichwd_sts_reset().
552 */
553 if ((ichwd_read_tco_2(sc, TCO2_STS) & TCO_SECOND_TO_STS) != 0)
554 device_printf(dev,
555 "resuming after hardware watchdog timeout\n");
556
557 /* reset the watchdog status registers */
558 ichwd_sts_reset(sc);
559
560 /* make sure the WDT starts out inactive */
561 ichwd_tmr_disable(sc);
562
563 /* register the watchdog event handler */
564 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, ichwd_event, sc, 0);
565
566 /* disable the SMI handler */
567 sc->smi_enabled = ichwd_smi_is_enabled(sc);
568 ichwd_smi_disable(sc);
569
570 return (0);
571 fail:
572 sc = device_get_softc(dev);
573 if (sc->tco_res != NULL)
574 bus_release_resource(dev, SYS_RES_IOPORT,
575 sc->tco_rid, sc->tco_res);
576 if (sc->smi_res != NULL)
577 bus_release_resource(dev, SYS_RES_IOPORT,
578 sc->smi_rid, sc->smi_res);
579 if (sc->gcs_res != NULL)
580 bus_release_resource(ich, SYS_RES_MEMORY,
581 sc->gcs_rid, sc->gcs_res);
582
583 return (ENXIO);
584 }
585
586 static int
587 ichwd_detach(device_t dev)
588 {
589 struct ichwd_softc *sc;
590 device_t ich = NULL;
591
592 sc = device_get_softc(dev);
593
594 /* halt the watchdog timer */
595 if (sc->active)
596 ichwd_tmr_disable(sc);
597
598 /* enable the SMI handler */
599 if (sc->smi_enabled != 0)
600 ichwd_smi_enable(sc);
601
602 /* deregister event handler */
603 if (sc->ev_tag != NULL)
604 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag);
605 sc->ev_tag = NULL;
606
607 /* reset the watchdog status registers */
608 ichwd_sts_reset(sc);
609
610 /* deallocate I/O register space */
611 bus_release_resource(dev, SYS_RES_IOPORT, sc->tco_rid, sc->tco_res);
612 bus_release_resource(dev, SYS_RES_IOPORT, sc->smi_rid, sc->smi_res);
613
614 /* deallocate memory resource */
615 ich = ichwd_find_ich_lpc_bridge(NULL);
616 if (sc->gcs_res && ich)
617 bus_release_resource(ich, SYS_RES_MEMORY, sc->gcs_rid, sc->gcs_res);
618
619 return (0);
620 }
621
622 static device_method_t ichwd_methods[] = {
623 DEVMETHOD(device_identify, ichwd_identify),
624 DEVMETHOD(device_probe, ichwd_probe),
625 DEVMETHOD(device_attach, ichwd_attach),
626 DEVMETHOD(device_detach, ichwd_detach),
627 DEVMETHOD(device_shutdown, ichwd_detach),
628 {0,0}
629 };
630
631 static driver_t ichwd_driver = {
632 "ichwd",
633 ichwd_methods,
634 sizeof(struct ichwd_softc),
635 };
636
637 static int
638 ichwd_modevent(module_t mode, int type, void *data)
639 {
640 int error = 0;
641
642 switch (type) {
643 case MOD_LOAD:
644 printf("ichwd module loaded\n");
645 break;
646 case MOD_UNLOAD:
647 printf("ichwd module unloaded\n");
648 break;
649 case MOD_SHUTDOWN:
650 printf("ichwd module shutting down\n");
651 break;
652 }
653 return (error);
654 }
655
656 DRIVER_MODULE(ichwd, isa, ichwd_driver, ichwd_devclass, ichwd_modevent, NULL);
Cache object: 3fc2f7e772e1f3830b43e413e78d4987
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