Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/dev/ichwd/ichwd.h
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004 Texas A&M University 5 * All rights reserved. 6 * 7 * Developer: Wm. Daryl Hawkins 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _ICHWD_H_ 34 #define _ICHWD_H_ 35 36 struct ichwd_device { 37 uint16_t device; 38 char *desc; 39 unsigned int ich_version; 40 unsigned int tco_version; 41 uint32_t quirks; 42 }; 43 44 struct ichwd_softc { 45 device_t device; 46 device_t ich; 47 int ich_version; 48 int tco_version; 49 50 int active; 51 unsigned int timeout; 52 53 int smi_enabled; 54 int smi_rid; 55 struct resource *smi_res; 56 57 int tco_rid; 58 struct resource *tco_res; 59 60 int gcs_rid; 61 struct resource *gcs_res; 62 63 int gc_rid; 64 struct resource *gc_res; 65 66 eventhandler_tag ev_tag; 67 }; 68 69 #define VENDORID_INTEL 0x8086 70 #define DEVICEID_BAYTRAIL 0x0f1c 71 #define DEVICEID_C3000 0x19df 72 #define DEVICEID_CPT0 0x1c40 73 #define DEVICEID_CPT1 0x1c41 74 #define DEVICEID_CPT2 0x1c42 75 #define DEVICEID_CPT3 0x1c43 76 #define DEVICEID_CPT4 0x1c44 77 #define DEVICEID_CPT5 0x1c45 78 #define DEVICEID_CPT6 0x1c46 79 #define DEVICEID_CPT7 0x1c47 80 #define DEVICEID_CPT8 0x1c48 81 #define DEVICEID_CPT9 0x1c49 82 #define DEVICEID_CPT10 0x1c4a 83 #define DEVICEID_CPT11 0x1c4b 84 #define DEVICEID_CPT12 0x1c4c 85 #define DEVICEID_CPT13 0x1c4d 86 #define DEVICEID_CPT14 0x1c4e 87 #define DEVICEID_CPT15 0x1c4f 88 #define DEVICEID_CPT16 0x1c50 89 #define DEVICEID_CPT17 0x1c51 90 #define DEVICEID_CPT18 0x1c52 91 #define DEVICEID_CPT19 0x1c53 92 #define DEVICEID_CPT20 0x1c54 93 #define DEVICEID_CPT21 0x1c55 94 #define DEVICEID_CPT22 0x1c56 95 #define DEVICEID_CPT23 0x1c57 96 #define DEVICEID_CPT24 0x1c58 97 #define DEVICEID_CPT25 0x1c59 98 #define DEVICEID_CPT26 0x1c5a 99 #define DEVICEID_CPT27 0x1c5b 100 #define DEVICEID_CPT28 0x1c5c 101 #define DEVICEID_CPT29 0x1c5d 102 #define DEVICEID_CPT30 0x1c5e 103 #define DEVICEID_CPT31 0x1c5f 104 #define DEVICEID_PATSBURG_LPC1 0x1d40 105 #define DEVICEID_PATSBURG_LPC2 0x1d41 106 #define DEVICEID_PPT0 0x1e40 107 #define DEVICEID_PPT1 0x1e41 108 #define DEVICEID_PPT2 0x1e42 109 #define DEVICEID_PPT3 0x1e43 110 #define DEVICEID_PPT4 0x1e44 111 #define DEVICEID_PPT5 0x1e45 112 #define DEVICEID_PPT6 0x1e46 113 #define DEVICEID_PPT7 0x1e47 114 #define DEVICEID_PPT8 0x1e48 115 #define DEVICEID_PPT9 0x1e49 116 #define DEVICEID_PPT10 0x1e4a 117 #define DEVICEID_PPT11 0x1e4b 118 #define DEVICEID_PPT12 0x1e4c 119 #define DEVICEID_PPT13 0x1e4d 120 #define DEVICEID_PPT14 0x1e4e 121 #define DEVICEID_PPT15 0x1e4f 122 #define DEVICEID_PPT16 0x1e50 123 #define DEVICEID_PPT17 0x1e51 124 #define DEVICEID_PPT18 0x1e52 125 #define DEVICEID_PPT19 0x1e53 126 #define DEVICEID_PPT20 0x1e54 127 #define DEVICEID_PPT21 0x1e55 128 #define DEVICEID_PPT22 0x1e56 129 #define DEVICEID_PPT23 0x1e57 130 #define DEVICEID_PPT24 0x1e58 131 #define DEVICEID_PPT25 0x1e59 132 #define DEVICEID_PPT26 0x1e5a 133 #define DEVICEID_PPT27 0x1e5b 134 #define DEVICEID_PPT28 0x1e5c 135 #define DEVICEID_PPT29 0x1e5d 136 #define DEVICEID_PPT30 0x1e5e 137 #define DEVICEID_PPT31 0x1e5f 138 #define DEVICEID_AVN0 0x1f38 139 #define DEVICEID_AVN1 0x1f39 140 #define DEVICEID_AVN2 0x1f3a 141 #define DEVICEID_AVN3 0x1f3b 142 #define DEVICEID_BRASWELL 0x229c 143 #define DEVICEID_DH89XXCC_LPC 0x2310 144 #define DEVICEID_COLETOCRK_LPC 0x2390 145 #define DEVICEID_82801AA 0x2410 146 #define DEVICEID_82801AB 0x2420 147 #define DEVICEID_82801BA 0x2440 148 #define DEVICEID_82801BAM 0x244c 149 #define DEVICEID_82801CA 0x2480 150 #define DEVICEID_82801CAM 0x248c 151 #define DEVICEID_82801DB 0x24c0 152 #define DEVICEID_82801DBM 0x24cc 153 #define DEVICEID_82801E 0x2450 154 #define DEVICEID_82801EB 0x24dc 155 #define DEVICEID_82801EBR 0x24d0 156 #define DEVICEID_6300ESB 0x25a1 157 #define DEVICEID_82801FBR 0x2640 158 #define DEVICEID_ICH6M 0x2641 159 #define DEVICEID_ICH6W 0x2642 160 #define DEVICEID_63XXESB 0x2670 161 #define DEVICEID_ICH7 0x27b8 162 #define DEVICEID_ICH7DH 0x27b0 163 #define DEVICEID_ICH7M 0x27b9 164 #define DEVICEID_NM10 0x27bc 165 #define DEVICEID_ICH7MDH 0x27bd 166 #define DEVICEID_ICH8 0x2810 167 #define DEVICEID_ICH8DH 0x2812 168 #define DEVICEID_ICH8DO 0x2814 169 #define DEVICEID_ICH8M 0x2815 170 #define DEVICEID_ICH8ME 0x2811 171 #define DEVICEID_ICH9 0x2918 172 #define DEVICEID_ICH9DH 0x2912 173 #define DEVICEID_ICH9DO 0x2914 174 #define DEVICEID_ICH9M 0x2919 175 #define DEVICEID_ICH9ME 0x2917 176 #define DEVICEID_ICH9R 0x2916 177 #define DEVICEID_ICH10 0x3a18 178 #define DEVICEID_ICH10D 0x3a1a 179 #define DEVICEID_ICH10DO 0x3a14 180 #define DEVICEID_ICH10R 0x3a16 181 #define DEVICEID_PCH 0x3b00 182 #define DEVICEID_PCHM 0x3b01 183 #define DEVICEID_P55 0x3b02 184 #define DEVICEID_PM55 0x3b03 185 #define DEVICEID_H55 0x3b06 186 #define DEVICEID_QM57 0x3b07 187 #define DEVICEID_H57 0x3b08 188 #define DEVICEID_HM55 0x3b09 189 #define DEVICEID_Q57 0x3b0a 190 #define DEVICEID_HM57 0x3b0b 191 #define DEVICEID_PCHMSFF 0x3b0d 192 #define DEVICEID_QS57 0x3b0f 193 #define DEVICEID_3400 0x3b12 194 #define DEVICEID_3420 0x3b14 195 #define DEVICEID_3450 0x3b16 196 #define DEVICEID_LPT0 0x8c40 197 #define DEVICEID_LPT1 0x8c41 198 #define DEVICEID_LPT2 0x8c42 199 #define DEVICEID_LPT3 0x8c43 200 #define DEVICEID_LPT4 0x8c44 201 #define DEVICEID_LPT5 0x8c45 202 #define DEVICEID_LPT6 0x8c46 203 #define DEVICEID_LPT7 0x8c47 204 #define DEVICEID_LPT8 0x8c48 205 #define DEVICEID_LPT9 0x8c49 206 #define DEVICEID_LPT10 0x8c4a 207 #define DEVICEID_LPT11 0x8c4b 208 #define DEVICEID_LPT12 0x8c4c 209 #define DEVICEID_LPT13 0x8c4d 210 #define DEVICEID_LPT14 0x8c4e 211 #define DEVICEID_LPT15 0x8c4f 212 #define DEVICEID_LPT16 0x8c50 213 #define DEVICEID_LPT17 0x8c51 214 #define DEVICEID_LPT18 0x8c52 215 #define DEVICEID_LPT19 0x8c53 216 #define DEVICEID_LPT20 0x8c54 217 #define DEVICEID_LPT21 0x8c55 218 #define DEVICEID_LPT22 0x8c56 219 #define DEVICEID_LPT23 0x8c57 220 #define DEVICEID_LPT24 0x8c58 221 #define DEVICEID_LPT25 0x8c59 222 #define DEVICEID_LPT26 0x8c5a 223 #define DEVICEID_LPT27 0x8c5b 224 #define DEVICEID_LPT28 0x8c5c 225 #define DEVICEID_LPT29 0x8c5d 226 #define DEVICEID_LPT30 0x8c5e 227 #define DEVICEID_LPT31 0x8c5f 228 #define DEVICEID_WCPT1 0x8cc1 229 #define DEVICEID_WCPT2 0x8cc2 230 #define DEVICEID_WCPT3 0x8cc3 231 #define DEVICEID_WCPT4 0x8cc4 232 #define DEVICEID_WCPT6 0x8cc6 233 #define DEVICEID_WBG0 0x8d40 234 #define DEVICEID_WBG1 0x8d41 235 #define DEVICEID_WBG2 0x8d42 236 #define DEVICEID_WBG3 0x8d43 237 #define DEVICEID_WBG4 0x8d44 238 #define DEVICEID_WBG5 0x8d45 239 #define DEVICEID_WBG6 0x8d46 240 #define DEVICEID_WBG7 0x8d47 241 #define DEVICEID_WBG8 0x8d48 242 #define DEVICEID_WBG9 0x8d49 243 #define DEVICEID_WBG10 0x8d4a 244 #define DEVICEID_WBG11 0x8d4b 245 #define DEVICEID_WBG12 0x8d4c 246 #define DEVICEID_WBG13 0x8d4d 247 #define DEVICEID_WBG14 0x8d4e 248 #define DEVICEID_WBG15 0x8d4f 249 #define DEVICEID_WBG16 0x8d50 250 #define DEVICEID_WBG17 0x8d51 251 #define DEVICEID_WBG18 0x8d52 252 #define DEVICEID_WBG19 0x8d53 253 #define DEVICEID_WBG20 0x8d54 254 #define DEVICEID_WBG21 0x8d55 255 #define DEVICEID_WBG22 0x8d56 256 #define DEVICEID_WBG23 0x8d57 257 #define DEVICEID_WBG24 0x8d58 258 #define DEVICEID_WBG25 0x8d59 259 #define DEVICEID_WBG26 0x8d5a 260 #define DEVICEID_WBG27 0x8d5b 261 #define DEVICEID_WBG28 0x8d5c 262 #define DEVICEID_WBG29 0x8d5d 263 #define DEVICEID_WBG30 0x8d5e 264 #define DEVICEID_WBG31 0x8d5f 265 #define DEVICEID_LPT_LP0 0x9c40 266 #define DEVICEID_LPT_LP1 0x9c41 267 #define DEVICEID_LPT_LP2 0x9c42 268 #define DEVICEID_LPT_LP3 0x9c43 269 #define DEVICEID_LPT_LP4 0x9c44 270 #define DEVICEID_LPT_LP5 0x9c45 271 #define DEVICEID_LPT_LP6 0x9c46 272 #define DEVICEID_LPT_LP7 0x9c47 273 #define DEVICEID_WCPT_LP1 0x9cc1 274 #define DEVICEID_WCPT_LP2 0x9cc2 275 #define DEVICEID_WCPT_LP3 0x9cc3 276 #define DEVICEID_WCPT_LP5 0x9cc5 277 #define DEVICEID_WCPT_LP6 0x9cc6 278 #define DEVICEID_WCPT_LP7 0x9cc7 279 #define DEVICEID_WCPT_LP9 0x9cc9 280 #define DEVICEID_LEWISBURG_SMB 0xa1a3 281 #define DEVICEID_LEWISBURG_SMB_SSKU 0xa223 282 #define DEVICEID_CANNON_SMB 0xa323 283 #define DEVICEID_COMET_SMB 0x06a3 284 #define DEVICEID_SRPTLP_SMB 0x9d23 285 286 /* ICH LPC Interface Bridge Registers (ICH5 and older) */ 287 #define ICH_GEN_STA 0xd4 288 #define ICH_GEN_STA_NO_REBOOT 0x02 289 #define ICH_PMBASE 0x40 /* ACPI base address register */ 290 #define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */ 291 292 /* ICH Chipset Configuration Registers (ICH6 and newer) */ 293 #define ICH_RCBA 0xf0 294 #define ICH_GCS_OFFSET 0x3410 295 #define ICH_GCS_SIZE 0x4 296 #define ICH_GCS_NO_REBOOT 0x20 297 298 /* SoC Power Management Configuration Registers */ 299 #define ICH_PBASE 0x44 300 #define ICH_PMC_OFFSET 0x08 301 #define ICH_PMC_SIZE 0x4 302 #define ICH_PMC_NO_REBOOT 0x10 303 304 /* Lewisburg configration registers in SMBus controller. */ 305 #define ICH_TCOBASE 0x50 /* TCO Base Addr */ 306 #define ICH_TCOBASE_ADDRMASK 0xffe0 307 #define ICH_TCOBASE_SIZE 32 308 #define ICH_TCOCTL 0x54 /* TCO Control */ 309 #define ICH_TCOCTL_TCO_BASE_EN 0x0100 /* TCO Base decoding enabled */ 310 #define ICH_TCOCTL_TCO_BASE_LOCK 0x0001 /* TCOBASE is locked */ 311 312 /* 313 * Configuration registers in Sunrise Point and Lewisburg PCH Sideband Interface 314 * and Private Configuration Space. 315 */ 316 #define SBREG_BAR 0x10 317 #define SMB_GC_REG 0xc 318 #define SMB_GC_SIZE 4 319 #define SMB_GC_NO_REBOOT 0x2 320 #define SMB_PORT_ID 0xc6 321 #define PCR_PORTID_SHIFT 16 322 #define PCR_REG_OFF(pid, reg) (((pid) << PCR_PORTID_SHIFT) | (reg)) 323 324 /* register names and locations (relative to PMBASE) */ 325 #define SMI_BASE 0x30 /* base address for SMI registers */ 326 #define SMI_LEN 0x08 327 #define SMI_EN 0x00 /* SMI Control and Enable Register */ 328 #define SMI_STS 0x04 /* SMI Status Register */ 329 #define TCO_BASE 0x60 /* base address for TCO registers */ 330 #define TCO_LEN 0x20 331 #define TCO_RLD 0x00 /* TCO Reload and Current Value */ 332 #define TCO_TMR1 0x01 /* TCO Timer Initial Value 333 (ICH5 and older, 8 bits) */ 334 #define TCO_TMR2 0x12 /* TCO Timer Initial Value 335 (ICH6 and newer, 16 bits) */ 336 #define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */ 337 #define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */ 338 #define TCO1_STS 0x04 /* TCO Status 1 */ 339 #define TCO2_STS 0x06 /* TCO Status 2 */ 340 #define TCO1_CNT 0x08 /* TCO Control 1 */ 341 #define TCO2_CNT 0x08 /* TCO Control 2 */ 342 #define TCO_MESSAGE1 0x0c /* TCO Message 1 */ 343 #define TCO_MESSAGE2 0x0d /* TCO Message 2 */ 344 #define TCO_WDSTATUS 0x0e /* TCO Watchdog status */ 345 #define TCO_TMR 0x12 /* TCP Reload value */ 346 347 /* bit definitions for SMI_EN and SMI_STS */ 348 #define SMI_TCO_EN 0x2000 349 #define SMI_TCO_STS 0x2000 350 #define SMI_GBL_EN 0x0001 351 352 /* timer value mask for TCO_RLD and TCO_TMR */ 353 #define TCO_TIMER_MASK 0x1f 354 #define TCO_TIMER_MASK2 0x2f 355 356 /* status bits for TCO1_STS */ 357 #define TCO_SLVSEL 0x2000 /* TCO Slave Select Soft Strap */ 358 #define TCO_CPUSERR_STS 0x1000 359 #define TCO_CPUSMI_STS 0x0400 360 #define TCO_CPUSCI_STS 0x0200 361 #define TCO_BIOSWR_STS 0x0100 362 #define TCO_NEWCENTURY 0x0080 /* set for RTC year roll over 363 (99 to 00) */ 364 #define TCO_TIMEOUT 0x0008 /* timed out */ 365 #define TCO_INT_STS 0x0004 /* data out (DO NOT USE) */ 366 #define TCO_SMI_STS 0x0002 /* data in (DO NOT USE) */ 367 #define TCO_NMI2SMI_STS 0x0001 368 369 /* status bits for TCO2_STS */ 370 #define TCO_SMLINK_SLAVE_SMI 0x0010 371 #define TCO_BOOT_STS 0x0004 /* failed to come out of reset */ 372 #define TCO_SECOND_TO_STS 0x0002 /* ran down twice */ 373 #define TCO_INTRD_DET 0x0001 374 375 /* control bits for TCO1_CNT */ 376 #define TCO_LOCK 0x1000 /* SMI_BASE.TCO_EN locked */ 377 #define TCO_TMR_HALT 0x0800 /* clear to enable WDT */ 378 #define TCO_NMI2SMI_EN 0x0200 /* convert NMIs to SMIs */ 379 #define TCO_CNT_PRESERVE TCO_NMI2SMI_EN /* preserve these bits */ 380 #define TCO_NMI_NOW 0x0100 /* trigger an NMI */ 381 382 /* control bits for TCO2_CNT */ 383 #define TCO_OS_POLICY 0x0030 /* mask */ 384 #define TCO_OS_POLICY_BOOT 0x0000 385 #define TCO_OS_POLICY_SHUTD 0x0010 386 #define TCO_OS_POLICY_NOLOAD 0x0020 387 #define TCO_SMB_ALERT_DISABLE 0x0008 388 #define TCO_INTRD_SEL 0x0003 /* mask */ 389 #define TCO_INTRD_SEL_SILENT 0x0000 390 #define TCO_INTRD_SEL_INTR 0x0001 391 #define TCO_INTRD_SEL_SMI 0x0002 392 393 /* default ACPI Base values */ 394 #define ACPI_DEFAULT_CANNON 0x1800 395 396 /* 397 * Masks for the TCO timer value field in TCO_RLD. 398 * If the datasheets are to be believed, the minimum value actually varies 399 * from chipset to chipset - 4 for ICH5 and 2 for all other chipsets. 400 * I suspect this is a bug in the ICH5 datasheet and that the minimum is 401 * uniformly 2, but I'd rather err on the side of caution. 402 */ 403 #define TCO_RLD_TMR_MIN 0x0004 404 #define TCO_RLD1_TMR_MAX 0x003f 405 #define TCO_RLD2_TMR_MAX 0x03ff 406 407 /* 408 * Approximate length in nanoseconds of one WDT tick (about 0.6 sec) 409 * for TCO v1/v2/v4 410 */ 411 #define ICHWD_TICK 600000000 412 /* 413 * Approximate length in nanoseconds of one WDT tick (about 1.0 sec) 414 * for TCO v3 415 */ 416 #define ICHWD_TCO_V3_TICK 1000000000 417 418 /* 419 * Quirks 420 */ 421 422 /* On Cannon Lake and Commet Lake PHCs, the PMC is hidden */ 423 #define PMC_HIDDEN (1 << 0) 424 425 #endif
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