ichwd.h

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    1 /*-
    2  * Copyright (c) 2004 Texas A&M University
    3  * All rights reserved.
    4  *
    5  * Developer: Wm. Daryl Hawkins
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  * $FreeBSD$
   29  */
   30 
   31 #ifndef _ICHWD_H_
   32 #define _ICHWD_H_
   33 
   34 struct ichwd_device {
   35         uint16_t                 device;
   36         char                    *desc;
   37         unsigned int             version;
   38 };
   39 
   40 struct ichwd_softc {
   41         device_t                 device;
   42         device_t                 ich;
   43         int                      ich_version;
   44 
   45         int                      active;
   46         unsigned int             timeout;
   47 
   48         int                      smi_rid;
   49         struct resource         *smi_res;
   50         bus_space_tag_t          smi_bst;
   51         bus_space_handle_t       smi_bsh;
   52 
   53         int                      tco_rid;
   54         struct resource         *tco_res;
   55         bus_space_tag_t          tco_bst;
   56         bus_space_handle_t       tco_bsh;
   57 
   58         int                      gcs_rid;
   59         struct resource         *gcs_res;
   60         bus_space_tag_t          gcs_bst;
   61         bus_space_handle_t       gcs_bsh;
   62 
   63         eventhandler_tag         ev_tag;
   64 };
   65 
   66 #define VENDORID_INTEL          0x8086
   67 #define DEVICEID_82801AA        0x2410
   68 #define DEVICEID_82801AB        0x2420
   69 #define DEVICEID_82801BA        0x2440
   70 #define DEVICEID_82801BAM       0x244c
   71 #define DEVICEID_82801CA        0x2480
   72 #define DEVICEID_82801CAM       0x248c
   73 #define DEVICEID_82801DB        0x24c0
   74 #define DEVICEID_82801DBM       0x24cc
   75 #define DEVICEID_82801E         0x2450
   76 #define DEVICEID_82801EB        0x24dc
   77 #define DEVICEID_82801EBR       0x24d0
   78 #define DEVICEID_6300ESB        0x25a1
   79 #define DEVICEID_82801FBR       0x2640
   80 #define DEVICEID_ICH6M          0x2641
   81 #define DEVICEID_ICH6W          0x2642
   82 #define DEVICEID_63XXESB        0x2670
   83 #define DEVICEID_ICH7           0x27b8
   84 #define DEVICEID_ICH7DH         0x27b0
   85 #define DEVICEID_ICH7M          0x27b9
   86 #define DEVICEID_ICH7MDH        0x27bd
   87 #define DEVICEID_ICH8           0x2810
   88 #define DEVICEID_ICH8DH         0x2812
   89 #define DEVICEID_ICH8DO         0x2814
   90 #define DEVICEID_ICH8M          0x2815
   91 #define DEVICEID_ICH8ME         0x2811
   92 #define DEVICEID_ICH9           0x2918
   93 #define DEVICEID_ICH9DH         0x2912
   94 #define DEVICEID_ICH9DO         0x2914
   95 #define DEVICEID_ICH9M          0x2919
   96 #define DEVICEID_ICH9ME         0x2917
   97 #define DEVICEID_ICH9R          0x2916
   98 #define DEVICEID_ICH10          0x3a18
   99 #define DEVICEID_ICH10D         0x3a1a
  100 #define DEVICEID_ICH10DO        0x3a14
  101 #define DEVICEID_ICH10R         0x3a16
  102 
  103 /* ICH LPC Interface Bridge Registers (ICH5 and older) */
  104 #define ICH_GEN_STA             0xd4
  105 #define ICH_GEN_STA_NO_REBOOT   0x02
  106 #define ICH_PMBASE              0x40 /* ACPI base address register */
  107 #define ICH_PMBASE_MASK         0x7f80 /* bits 7-15 */
  108 
  109 /* ICH Chipset Configuration Registers (ICH6 and newer) */
  110 #define ICH_RCBA                0xf0
  111 #define ICH_GCS_OFFSET          0x3410
  112 #define ICH_GCS_SIZE            0x4
  113 #define ICH_GCS_NO_REBOOT       0x20
  114 
  115 /* register names and locations (relative to PMBASE) */
  116 #define SMI_BASE                0x30 /* base address for SMI registers */
  117 #define SMI_LEN                 0x08
  118 #define SMI_EN                  0x00 /* SMI Control and Enable Register */
  119 #define SMI_STS                 0x04 /* SMI Status Register */
  120 #define TCO_BASE                0x60 /* base address for TCO registers */
  121 #define TCO_LEN                 0x20
  122 #define TCO_RLD                 0x00 /* TCO Reload and Current Value */
  123 #define TCO_TMR1                0x01 /* TCO Timer Initial Value
  124                                         (ICH5 and older, 8 bits) */
  125 #define TCO_TMR2                0x12 /* TCO Timer Initial Value
  126                                         (ICH6 and newer, 16 bits) */
  127 #define TCO_DAT_IN              0x02 /* TCO Data In (DO NOT USE) */
  128 #define TCO_DAT_OUT             0x03 /* TCO Data Out (DO NOT USE) */
  129 #define TCO1_STS                0x04 /* TCO Status 1 */
  130 #define TCO2_STS                0x06 /* TCO Status 2 */
  131 #define TCO1_CNT                0x08 /* TCO Control 1 */
  132 #define TCO2_CNT                0x08 /* TCO Control 2 */
  133 
  134 /* bit definitions for SMI_EN and SMI_STS */
  135 #define SMI_TCO_EN              0x2000
  136 #define SMI_TCO_STS             0x2000
  137 
  138 /* timer value mask for TCO_RLD and TCO_TMR */
  139 #define TCO_TIMER_MASK          0x1f
  140 
  141 /* status bits for TCO1_STS */
  142 #define TCO_TIMEOUT             0x08 /* timed out */
  143 #define TCO_INT_STS             0x04 /* data out (DO NOT USE) */
  144 #define TCO_SMI_STS             0x02 /* data in (DO NOT USE) */
  145 
  146 /* status bits for TCO2_STS */
  147 #define TCO_BOOT_STS            0x04 /* failed to come out of reset */
  148 #define TCO_SECOND_TO_STS       0x02 /* ran down twice */
  149 
  150 /* control bits for TCO1_CNT */
  151 #define TCO_TMR_HALT            0x0800 /* clear to enable WDT */
  152 #define TCO_CNT_PRESERVE        0x0200 /* preserve these bits */
  153 
  154 /* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */
  155 #define ICHWD_TICK              600000000
  156 
  157 #endif

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FreeBSD/Linux Kernel Cross Reference sys/dev/ichwd/ichwd.h

FreeBSD/Linux Kernel Cross Reference
sys/dev/ichwd/ichwd.h