1 /* $NetBSD: fwohci.c,v 1.103.2.1 2006/12/30 05:14:16 riz Exp $ */
2
3 /*-
4 * Copyright (c) 2003 Hidetoshi Shimokawa
5 * Copyright (c) 1998-2002 Katsushi Kobayashi and Hidetoshi Shimokawa
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the acknowledgement as bellow:
18 *
19 * This product includes software developed by K. Kobayashi and H. Shimokawa
20 *
21 * 4. The name of the author may not be used to endorse or promote products
22 * derived from this software without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
25 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
28 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
29 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
32 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
33 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 *
36 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/firewire/fwohci.c,v 1.81 2005/03/29 01:44:59 sam Exp $
37 *
38 */
39
40 #define ATRQ_CH 0
41 #define ATRS_CH 1
42 #define ARRQ_CH 2
43 #define ARRS_CH 3
44 #define ITX_CH 4
45 #define IRX_CH 0x24
46
47 #if defined(__FreeBSD__)
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/mbuf.h>
51 #include <sys/malloc.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/bus.h>
55 #include <sys/kernel.h>
56 #include <sys/conf.h>
57 #include <sys/endian.h>
58 #include <sys/ktr.h>
59
60 #include <sys/cdefs.h>
61 __KERNEL_RCSID(0, "$NetBSD: fwohci.c,v 1.103.2.1 2006/12/30 05:14:16 riz Exp $");
62
63 #if defined(__DragonFly__) || __FreeBSD_version < 500000
64 #include <machine/clock.h> /* for DELAY() */
65 #endif
66
67 #ifdef __DragonFly__
68 #include "fw_port.h"
69 #include "firewire.h"
70 #include "firewirereg.h"
71 #include "fwdma.h"
72 #include "fwohcireg.h"
73 #include "fwohcivar.h"
74 #include "firewire_phy.h"
75 #else
76 #include <dev/firewire/fw_port.h>
77 #include <dev/firewire/firewire.h>
78 #include <dev/firewire/firewirereg.h>
79 #include <dev/firewire/fwdma.h>
80 #include <dev/firewire/fwohcireg.h>
81 #include <dev/firewire/fwohcivar.h>
82 #include <dev/firewire/firewire_phy.h>
83 #endif
84 #elif defined(__NetBSD__)
85 #include <sys/param.h>
86 #include <sys/device.h>
87 #include <sys/errno.h>
88 #include <sys/conf.h>
89 #include <sys/kernel.h>
90 #include <sys/malloc.h>
91 #include <sys/mbuf.h>
92 #include <sys/proc.h>
93 #include <sys/reboot.h>
94 #include <sys/sysctl.h>
95 #include <sys/systm.h>
96
97 #include <machine/bus.h>
98
99 #include <dev/ieee1394/fw_port.h>
100 #include <dev/ieee1394/firewire.h>
101 #include <dev/ieee1394/firewirereg.h>
102 #include <dev/ieee1394/fwdma.h>
103 #include <dev/ieee1394/fwohcireg.h>
104 #include <dev/ieee1394/fwohcivar.h>
105 #include <dev/ieee1394/firewire_phy.h>
106 #endif
107
108 #undef OHCI_DEBUG
109
110 static int nocyclemaster = 0;
111 #if defined(__FreeBSD__)
112 SYSCTL_DECL(_hw_firewire);
113 SYSCTL_INT(_hw_firewire, OID_AUTO, nocyclemaster, CTLFLAG_RW, &nocyclemaster, 0,
114 "Do not send cycle start packets");
115 #elif defined(__NetBSD__)
116 /*
117 * Setup sysctl(3) MIB, hw.fwohci.*
118 *
119 * TBD condition CTLFLAG_PERMANENT on being an LKM or not
120 */
121 SYSCTL_SETUP(sysctl_fwohci, "sysctl fwohci(4) subtree setup")
122 {
123 int rc;
124 const struct sysctlnode *node;
125
126 if ((rc = sysctl_createv(clog, 0, NULL, NULL,
127 CTLFLAG_PERMANENT, CTLTYPE_NODE, "hw", NULL,
128 NULL, 0, NULL, 0, CTL_HW, CTL_EOL)) != 0) {
129 goto err;
130 }
131
132 if ((rc = sysctl_createv(clog, 0, NULL, &node,
133 CTLFLAG_PERMANENT, CTLTYPE_NODE, "fwohci",
134 SYSCTL_DESCR("fwohci controls"),
135 NULL, 0, NULL, 0, CTL_HW, CTL_CREATE, CTL_EOL)) != 0) {
136 goto err;
137 }
138
139 /* fwohci no cyclemaster flag */
140 if ((rc = sysctl_createv(clog, 0, NULL, &node,
141 CTLFLAG_PERMANENT | CTLFLAG_READWRITE, CTLTYPE_INT,
142 "nocyclemaster", SYSCTL_DESCR("Do not send cycle start packets"),
143 NULL, 0, &nocyclemaster,
144 0, CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL)) != 0) {
145 goto err;
146 }
147 return;
148
149 err:
150 printf("%s: sysctl_createv failed (rc = %d)\n", __func__, rc);
151 }
152 #endif
153
154 static const char * const dbcode[16] = {"OUTM", "OUTL","INPM","INPL",
155 "STOR","LOAD","NOP ","STOP",
156 "", "", "", "", "", "", "", ""};
157
158 static const char * const dbkey[8] = {"ST0", "ST1","ST2","ST3",
159 "UNDEF","REG","SYS","DEV"};
160 static const char * const dbcond[4] = {"NEV","C=1", "C=0", "ALL"};
161 static const char * const fwohcicode[32] = {
162 "No stat","Undef","long","miss Ack err",
163 "underrun","overrun","desc err", "data read err",
164 "data write err","bus reset","timeout","tcode err",
165 "Undef","Undef","unknown event","flushed",
166 "Undef","ack complete","ack pend","Undef",
167 "ack busy_X","ack busy_A","ack busy_B","Undef",
168 "Undef","Undef","Undef","ack tardy",
169 "Undef","ack data_err","ack type_err",""};
170
171 #define MAX_SPEED 3
172 extern const char *fw_linkspeed[];
173 static uint32_t const tagbit[4] = { 1 << 28, 1 << 29, 1 << 30, 1 << 31};
174
175 static const struct tcode_info tinfo[] = {
176 /* hdr_len block flag*/
177 /* 0 WREQQ */ {16, FWTI_REQ | FWTI_TLABEL},
178 /* 1 WREQB */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
179 /* 2 WRES */ {12, FWTI_RES},
180 /* 3 XXX */ { 0, 0},
181 /* 4 RREQQ */ {12, FWTI_REQ | FWTI_TLABEL},
182 /* 5 RREQB */ {16, FWTI_REQ | FWTI_TLABEL},
183 /* 6 RRESQ */ {16, FWTI_RES},
184 /* 7 RRESB */ {16, FWTI_RES | FWTI_BLOCK_ASY},
185 /* 8 CYCS */ { 0, 0},
186 /* 9 LREQ */ {16, FWTI_REQ | FWTI_TLABEL | FWTI_BLOCK_ASY},
187 /* a STREAM */ { 4, FWTI_REQ | FWTI_BLOCK_STR},
188 /* b LRES */ {16, FWTI_RES | FWTI_BLOCK_ASY},
189 /* c XXX */ { 0, 0},
190 /* d XXX */ { 0, 0},
191 /* e PHY */ {12, FWTI_REQ},
192 /* f XXX */ { 0, 0}
193 };
194
195 #define OHCI_WRITE_SIGMASK 0xffff0000
196 #define OHCI_READ_SIGMASK 0xffff0000
197
198 #define OWRITE(sc, r, x) bus_space_write_4((sc)->bst, (sc)->bsh, (r), (x))
199 #define OREAD(sc, r) bus_space_read_4((sc)->bst, (sc)->bsh, (r))
200
201 static void fwohci_ibr (struct firewire_comm *);
202 static void fwohci_db_init (struct fwohci_softc *, struct fwohci_dbch *);
203 static void fwohci_db_free (struct fwohci_dbch *);
204 static void fwohci_arcv (struct fwohci_softc *, struct fwohci_dbch *, int);
205 static void fwohci_txd (struct fwohci_softc *, struct fwohci_dbch *);
206 static void fwohci_start_atq (struct firewire_comm *);
207 static void fwohci_start_ats (struct firewire_comm *);
208 static void fwohci_start (struct fwohci_softc *, struct fwohci_dbch *);
209 static uint32_t fwphy_wrdata ( struct fwohci_softc *, uint32_t, uint32_t);
210 static uint32_t fwphy_rddata ( struct fwohci_softc *, uint32_t);
211 static int fwohci_rx_enable (struct fwohci_softc *, struct fwohci_dbch *);
212 static int fwohci_tx_enable (struct fwohci_softc *, struct fwohci_dbch *);
213 static int fwohci_irx_enable (struct firewire_comm *, int);
214 static int fwohci_irx_disable (struct firewire_comm *, int);
215 #if BYTE_ORDER == BIG_ENDIAN
216 static void fwohci_irx_post (struct firewire_comm *, uint32_t *);
217 #endif
218 static int fwohci_itxbuf_enable (struct firewire_comm *, int);
219 static int fwohci_itx_disable (struct firewire_comm *, int);
220 static void fwohci_timeout (void *);
221 static void fwohci_set_intr (struct firewire_comm *, int);
222
223 static int fwohci_add_rx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int, struct fwdma_alloc *);
224 static int fwohci_add_tx_buf (struct fwohci_dbch *, struct fwohcidb_tr *, int);
225 static void dump_db (struct fwohci_softc *, uint32_t);
226 static void print_db (struct fwohcidb_tr *, struct fwohcidb *, uint32_t , uint32_t);
227 static void dump_dma (struct fwohci_softc *, uint32_t);
228 static uint32_t fwohci_cyctimer (struct firewire_comm *);
229 static void fwohci_rbuf_update (struct fwohci_softc *, int);
230 static void fwohci_tbuf_update (struct fwohci_softc *, int);
231 void fwohci_txbufdb (struct fwohci_softc *, int , struct fw_bulkxfer *);
232 #if FWOHCI_TASKQUEUE
233 static void fwohci_complete(void *, int);
234 #endif
235 #if defined(__NetBSD__)
236 static void fwohci_power(int, void *);
237 int fwohci_print(void *, const char *);
238 #endif
239
240 /*
241 * memory allocated for DMA programs
242 */
243 #define DMA_PROG_ALLOC (8 * PAGE_SIZE)
244
245 #define NDB FWMAXQUEUE
246
247 #define OHCI_VERSION 0x00
248 #define OHCI_ATRETRY 0x08
249 #define OHCI_CROMHDR 0x18
250 #define OHCI_BUS_OPT 0x20
251 #define OHCI_BUSIRMC (1 << 31)
252 #define OHCI_BUSCMC (1 << 30)
253 #define OHCI_BUSISC (1 << 29)
254 #define OHCI_BUSBMC (1 << 28)
255 #define OHCI_BUSPMC (1 << 27)
256 #define OHCI_BUSFNC OHCI_BUSIRMC | OHCI_BUSCMC | OHCI_BUSISC |\
257 OHCI_BUSBMC | OHCI_BUSPMC
258
259 #define OHCI_EUID_HI 0x24
260 #define OHCI_EUID_LO 0x28
261
262 #define OHCI_CROMPTR 0x34
263 #define OHCI_HCCCTL 0x50
264 #define OHCI_HCCCTLCLR 0x54
265 #define OHCI_AREQHI 0x100
266 #define OHCI_AREQHICLR 0x104
267 #define OHCI_AREQLO 0x108
268 #define OHCI_AREQLOCLR 0x10c
269 #define OHCI_PREQHI 0x110
270 #define OHCI_PREQHICLR 0x114
271 #define OHCI_PREQLO 0x118
272 #define OHCI_PREQLOCLR 0x11c
273 #define OHCI_PREQUPPER 0x120
274
275 #define OHCI_SID_BUF 0x64
276 #define OHCI_SID_CNT 0x68
277 #define OHCI_SID_ERR (1 << 31)
278 #define OHCI_SID_CNT_MASK 0xffc
279
280 #define OHCI_IT_STAT 0x90
281 #define OHCI_IT_STATCLR 0x94
282 #define OHCI_IT_MASK 0x98
283 #define OHCI_IT_MASKCLR 0x9c
284
285 #define OHCI_IR_STAT 0xa0
286 #define OHCI_IR_STATCLR 0xa4
287 #define OHCI_IR_MASK 0xa8
288 #define OHCI_IR_MASKCLR 0xac
289
290 #define OHCI_LNKCTL 0xe0
291 #define OHCI_LNKCTLCLR 0xe4
292
293 #define OHCI_PHYACCESS 0xec
294 #define OHCI_CYCLETIMER 0xf0
295
296 #define OHCI_DMACTL(off) (off)
297 #define OHCI_DMACTLCLR(off) (off + 4)
298 #define OHCI_DMACMD(off) (off + 0xc)
299 #define OHCI_DMAMATCH(off) (off + 0x10)
300
301 #define OHCI_ATQOFF 0x180
302 #define OHCI_ATQCTL OHCI_ATQOFF
303 #define OHCI_ATQCTLCLR (OHCI_ATQOFF + 4)
304 #define OHCI_ATQCMD (OHCI_ATQOFF + 0xc)
305 #define OHCI_ATQMATCH (OHCI_ATQOFF + 0x10)
306
307 #define OHCI_ATSOFF 0x1a0
308 #define OHCI_ATSCTL OHCI_ATSOFF
309 #define OHCI_ATSCTLCLR (OHCI_ATSOFF + 4)
310 #define OHCI_ATSCMD (OHCI_ATSOFF + 0xc)
311 #define OHCI_ATSMATCH (OHCI_ATSOFF + 0x10)
312
313 #define OHCI_ARQOFF 0x1c0
314 #define OHCI_ARQCTL OHCI_ARQOFF
315 #define OHCI_ARQCTLCLR (OHCI_ARQOFF + 4)
316 #define OHCI_ARQCMD (OHCI_ARQOFF + 0xc)
317 #define OHCI_ARQMATCH (OHCI_ARQOFF + 0x10)
318
319 #define OHCI_ARSOFF 0x1e0
320 #define OHCI_ARSCTL OHCI_ARSOFF
321 #define OHCI_ARSCTLCLR (OHCI_ARSOFF + 4)
322 #define OHCI_ARSCMD (OHCI_ARSOFF + 0xc)
323 #define OHCI_ARSMATCH (OHCI_ARSOFF + 0x10)
324
325 #define OHCI_ITOFF(CH) (0x200 + 0x10 * (CH))
326 #define OHCI_ITCTL(CH) (OHCI_ITOFF(CH))
327 #define OHCI_ITCTLCLR(CH) (OHCI_ITOFF(CH) + 4)
328 #define OHCI_ITCMD(CH) (OHCI_ITOFF(CH) + 0xc)
329
330 #define OHCI_IROFF(CH) (0x400 + 0x20 * (CH))
331 #define OHCI_IRCTL(CH) (OHCI_IROFF(CH))
332 #define OHCI_IRCTLCLR(CH) (OHCI_IROFF(CH) + 4)
333 #define OHCI_IRCMD(CH) (OHCI_IROFF(CH) + 0xc)
334 #define OHCI_IRMATCH(CH) (OHCI_IROFF(CH) + 0x10)
335
336 #if defined(__FreeBSD__)
337 d_ioctl_t fwohci_ioctl;
338 #elif defined(__NetBSD__)
339 extern struct cfdriver fwohci_cd;
340 dev_type_ioctl(fwohci_ioctl);
341 #endif
342
343 /*
344 * Communication with PHY device
345 */
346 static uint32_t
347 fwphy_wrdata( struct fwohci_softc *sc, uint32_t addr, uint32_t data)
348 {
349 uint32_t fun;
350
351 addr &= 0xf;
352 data &= 0xff;
353
354 fun = (PHYDEV_WRCMD | (addr << PHYDEV_REGADDR) | (data << PHYDEV_WRDATA));
355 OWRITE(sc, OHCI_PHYACCESS, fun);
356 DELAY(100);
357
358 return(fwphy_rddata( sc, addr));
359 }
360
361 static uint32_t
362 fwohci_set_bus_manager(struct firewire_comm *fc, u_int node)
363 {
364 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
365 int i;
366 uint32_t bm;
367
368 #define OHCI_CSR_DATA 0x0c
369 #define OHCI_CSR_COMP 0x10
370 #define OHCI_CSR_CONT 0x14
371 #define OHCI_BUS_MANAGER_ID 0
372
373 OWRITE(sc, OHCI_CSR_DATA, node);
374 OWRITE(sc, OHCI_CSR_COMP, 0x3f);
375 OWRITE(sc, OHCI_CSR_CONT, OHCI_BUS_MANAGER_ID);
376 for (i = 0; !(OREAD(sc, OHCI_CSR_CONT) & (1<<31)) && (i < 1000); i++)
377 DELAY(10);
378 bm = OREAD(sc, OHCI_CSR_DATA);
379 if((bm & 0x3f) == 0x3f)
380 bm = node;
381 if (firewire_debug)
382 device_printf(sc->fc.dev,
383 "fw_set_bus_manager: %d->%d (loop=%d)\n", bm, node, i);
384
385 return(bm);
386 }
387
388 static uint32_t
389 fwphy_rddata(struct fwohci_softc *sc, u_int addr)
390 {
391 uint32_t fun, stat;
392 u_int i, retry = 0;
393
394 addr &= 0xf;
395 #define MAX_RETRY 100
396 again:
397 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_REG_FAIL);
398 fun = PHYDEV_RDCMD | (addr << PHYDEV_REGADDR);
399 OWRITE(sc, OHCI_PHYACCESS, fun);
400 for ( i = 0 ; i < MAX_RETRY ; i ++ ){
401 fun = OREAD(sc, OHCI_PHYACCESS);
402 if ((fun & PHYDEV_RDCMD) == 0 && (fun & PHYDEV_RDDONE) != 0)
403 break;
404 DELAY(100);
405 }
406 if(i >= MAX_RETRY) {
407 if (firewire_debug)
408 device_printf(sc->fc.dev, "phy read failed(1).\n");
409 if (++retry < MAX_RETRY) {
410 DELAY(100);
411 goto again;
412 }
413 }
414 /* Make sure that SCLK is started */
415 stat = OREAD(sc, FWOHCI_INTSTAT);
416 if ((stat & OHCI_INT_REG_FAIL) != 0 ||
417 ((fun >> PHYDEV_REGADDR) & 0xf) != addr) {
418 if (firewire_debug)
419 device_printf(sc->fc.dev, "phy read failed(2).\n");
420 if (++retry < MAX_RETRY) {
421 DELAY(100);
422 goto again;
423 }
424 }
425 if (firewire_debug || retry >= MAX_RETRY)
426 device_printf(sc->fc.dev,
427 "fwphy_rddata: 0x%x loop=%d, retry=%d\n", addr, i, retry);
428 #undef MAX_RETRY
429 return((fun >> PHYDEV_RDDATA )& 0xff);
430 }
431 /* Device specific ioctl. */
432 FW_IOCTL(fwohci)
433 {
434 FW_IOCTL_START;
435 struct fwohci_softc *fc;
436 int err = 0;
437 struct fw_reg_req_t *reg = (struct fw_reg_req_t *) data;
438 uint32_t *dmach = (uint32_t *) data;
439
440 if(sc == NULL){
441 return(EINVAL);
442 }
443 fc = (struct fwohci_softc *)sc->fc;
444
445 if (!data)
446 return(EINVAL);
447
448 switch (cmd) {
449 case FWOHCI_WRREG:
450 #define OHCI_MAX_REG 0x800
451 if(reg->addr <= OHCI_MAX_REG){
452 OWRITE(fc, reg->addr, reg->data);
453 reg->data = OREAD(fc, reg->addr);
454 }else{
455 err = EINVAL;
456 }
457 break;
458 case FWOHCI_RDREG:
459 if(reg->addr <= OHCI_MAX_REG){
460 reg->data = OREAD(fc, reg->addr);
461 }else{
462 err = EINVAL;
463 }
464 break;
465 /* Read DMA descriptors for debug */
466 case DUMPDMA:
467 if(*dmach <= OHCI_MAX_DMA_CH ){
468 dump_dma(fc, *dmach);
469 dump_db(fc, *dmach);
470 }else{
471 err = EINVAL;
472 }
473 break;
474 /* Read/Write Phy registers */
475 #define OHCI_MAX_PHY_REG 0xf
476 case FWOHCI_RDPHYREG:
477 if (reg->addr <= OHCI_MAX_PHY_REG)
478 reg->data = fwphy_rddata(fc, reg->addr);
479 else
480 err = EINVAL;
481 break;
482 case FWOHCI_WRPHYREG:
483 if (reg->addr <= OHCI_MAX_PHY_REG)
484 reg->data = fwphy_wrdata(fc, reg->addr, reg->data);
485 else
486 err = EINVAL;
487 break;
488 default:
489 err = EINVAL;
490 break;
491 }
492 return err;
493 }
494
495 static int
496 fwohci_probe_phy(struct fwohci_softc *sc, device_t dev)
497 {
498 uint32_t reg, reg2;
499 int e1394a = 1;
500 /*
501 * probe PHY parameters
502 * 0. to prove PHY version, whether compliance of 1394a.
503 * 1. to probe maximum speed supported by the PHY and
504 * number of port supported by core-logic.
505 * It is not actually available port on your PC .
506 */
507 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS);
508 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
509
510 if((reg >> 5) != 7 ){
511 sc->fc.mode &= ~FWPHYASYST;
512 sc->fc.nport = reg & FW_PHY_NP;
513 sc->fc.speed = reg & FW_PHY_SPD >> 6;
514 if (sc->fc.speed > MAX_SPEED) {
515 device_printf(dev, "invalid speed %d (fixed to %d).\n",
516 sc->fc.speed, MAX_SPEED);
517 sc->fc.speed = MAX_SPEED;
518 }
519 device_printf(dev,
520 "Phy 1394 only %s, %d ports.\n",
521 fw_linkspeed[sc->fc.speed], sc->fc.nport);
522 }else{
523 reg2 = fwphy_rddata(sc, FW_PHY_ESPD_REG);
524 sc->fc.mode |= FWPHYASYST;
525 sc->fc.nport = reg & FW_PHY_NP;
526 sc->fc.speed = (reg2 & FW_PHY_ESPD) >> 5;
527 if (sc->fc.speed > MAX_SPEED) {
528 device_printf(dev, "invalid speed %d (fixed to %d).\n",
529 sc->fc.speed, MAX_SPEED);
530 sc->fc.speed = MAX_SPEED;
531 }
532 device_printf(dev,
533 "Phy 1394a available %s, %d ports.\n",
534 fw_linkspeed[sc->fc.speed], sc->fc.nport);
535
536 /* check programPhyEnable */
537 reg2 = fwphy_rddata(sc, 5);
538 #if 0
539 if (e1394a && (OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_PRPHY)) {
540 #else /* XXX force to enable 1394a */
541 if (e1394a) {
542 #endif
543 if (firewire_debug)
544 device_printf(dev,
545 "Enable 1394a Enhancements\n");
546 /* enable EAA EMC */
547 reg2 |= 0x03;
548 /* set aPhyEnhanceEnable */
549 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_PHYEN);
550 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_PRPHY);
551 }
552 #if 0
553 else {
554 /* for safe */
555 reg2 &= ~0x83;
556 }
557 #endif
558 reg2 = fwphy_wrdata(sc, 5, reg2);
559 }
560
561 reg = fwphy_rddata(sc, FW_PHY_SPD_REG);
562 if((reg >> 5) == 7 ){
563 reg = fwphy_rddata(sc, 4);
564 reg |= 1 << 6;
565 fwphy_wrdata(sc, 4, reg);
566 reg = fwphy_rddata(sc, 4);
567 }
568 return 0;
569 }
570
571
572 void
573 fwohci_reset(struct fwohci_softc *sc, device_t dev)
574 {
575 int i, max_rec, speed;
576 uint32_t reg, reg2;
577 struct fwohcidb_tr *db_tr;
578
579 /* Disable interrupts */
580 OWRITE(sc, FWOHCI_INTMASKCLR, ~0);
581
582 /* Now stopping all DMA channels */
583 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
584 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
585 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
586 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
587
588 OWRITE(sc, OHCI_IR_MASKCLR, ~0);
589 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
590 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
591 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
592 }
593
594 /* FLUSH FIFO and reset Transmitter/Reciever */
595 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
596 if (firewire_debug)
597 device_printf(dev, "resetting OHCI...");
598 i = 0;
599 while(OREAD(sc, OHCI_HCCCTL) & OHCI_HCC_RESET) {
600 if (i++ > 100) break;
601 DELAY(1000);
602 }
603 if (firewire_debug)
604 printf("done (loop=%d)\n", i);
605
606 /* Probe phy */
607 fwohci_probe_phy(sc, dev);
608
609 /* Probe link */
610 reg = OREAD(sc, OHCI_BUS_OPT);
611 reg2 = reg | OHCI_BUSFNC;
612 max_rec = (reg & 0x0000f000) >> 12;
613 speed = (reg & 0x00000007);
614 device_printf(dev, "Link %s, max_rec %d bytes.\n",
615 fw_linkspeed[speed], MAXREC(max_rec));
616 /* XXX fix max_rec */
617 sc->fc.maxrec = sc->fc.speed + 8;
618 if (max_rec != sc->fc.maxrec) {
619 reg2 = (reg2 & 0xffff0fff) | (sc->fc.maxrec << 12);
620 device_printf(dev, "max_rec %d -> %d\n",
621 MAXREC(max_rec), MAXREC(sc->fc.maxrec));
622 }
623 if (firewire_debug)
624 device_printf(dev, "BUS_OPT 0x%x -> 0x%x\n", reg, reg2);
625 OWRITE(sc, OHCI_BUS_OPT, reg2);
626
627 /* Initialize registers */
628 OWRITE(sc, OHCI_CROMHDR, sc->fc.config_rom[0]);
629 OWRITE(sc, OHCI_CROMPTR, sc->crom_dma.bus_addr);
630 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_BIGEND);
631 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_POSTWR);
632 OWRITE(sc, OHCI_SID_BUF, sc->sid_dma.bus_addr);
633 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_SID);
634
635 /* Enable link */
636 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LINKEN);
637
638 /* Force to start async RX DMA */
639 sc->arrq.xferq.flag &= ~FWXFERQ_RUNNING;
640 sc->arrs.xferq.flag &= ~FWXFERQ_RUNNING;
641 fwohci_rx_enable(sc, &sc->arrq);
642 fwohci_rx_enable(sc, &sc->arrs);
643
644 /* Initialize async TX */
645 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
646 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN | OHCI_CNTL_DMA_DEAD);
647
648 /* AT Retries */
649 OWRITE(sc, FWOHCI_RETRY,
650 /* CycleLimit PhyRespRetries ATRespRetries ATReqRetries */
651 (0xffff << 16 ) | (0x0f << 8) | (0x0f << 4) | 0x0f) ;
652
653 sc->atrq.top = STAILQ_FIRST(&sc->atrq.db_trq);
654 sc->atrs.top = STAILQ_FIRST(&sc->atrs.db_trq);
655 sc->atrq.bottom = sc->atrq.top;
656 sc->atrs.bottom = sc->atrs.top;
657
658 for( i = 0, db_tr = sc->atrq.top; i < sc->atrq.ndb ;
659 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
660 db_tr->xfer = NULL;
661 }
662 for( i = 0, db_tr = sc->atrs.top; i < sc->atrs.ndb ;
663 i ++, db_tr = STAILQ_NEXT(db_tr, link)){
664 db_tr->xfer = NULL;
665 }
666
667
668 /* Enable interrupts */
669 OWRITE(sc, FWOHCI_INTMASK,
670 OHCI_INT_ERR | OHCI_INT_PHY_SID
671 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
672 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
673 | OHCI_INT_PHY_BUS_R | OHCI_INT_PW_ERR);
674 fwohci_set_intr(&sc->fc, 1);
675
676 }
677
678 int
679 fwohci_init(struct fwohci_softc *sc, device_t dev)
680 {
681 int i, mver;
682 uint32_t reg;
683 uint8_t ui[8];
684
685 #if FWOHCI_TASKQUEUE
686 TASK_INIT(&sc->fwohci_task_complete, 0, fwohci_complete, sc);
687 #endif
688
689 /* OHCI version */
690 reg = OREAD(sc, OHCI_VERSION);
691 mver = (reg >> 16) & 0xff;
692 device_printf(dev, "OHCI version %x.%x (ROM=%d)\n",
693 mver, reg & 0xff, (reg>>24) & 1);
694 if (mver < 1 || mver > 9) {
695 device_printf(dev, "invalid OHCI version\n");
696 return (ENXIO);
697 }
698
699 /* Available Isochronous DMA channel probe */
700 OWRITE(sc, OHCI_IT_MASK, 0xffffffff);
701 OWRITE(sc, OHCI_IR_MASK, 0xffffffff);
702 reg = OREAD(sc, OHCI_IT_MASK) & OREAD(sc, OHCI_IR_MASK);
703 OWRITE(sc, OHCI_IT_MASKCLR, 0xffffffff);
704 OWRITE(sc, OHCI_IR_MASKCLR, 0xffffffff);
705 for (i = 0; i < 0x20; i++)
706 if ((reg & (1 << i)) == 0)
707 break;
708 sc->fc.nisodma = i;
709 device_printf(dev, "No. of Isochronous channels is %d.\n", i);
710 if (i == 0)
711 return (ENXIO);
712
713 sc->fc.arq = &sc->arrq.xferq;
714 sc->fc.ars = &sc->arrs.xferq;
715 sc->fc.atq = &sc->atrq.xferq;
716 sc->fc.ats = &sc->atrs.xferq;
717
718 sc->arrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
719 sc->arrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
720 sc->atrq.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
721 sc->atrs.xferq.psize = roundup2(FWPMAX_S400, PAGE_SIZE);
722
723 sc->arrq.xferq.start = NULL;
724 sc->arrs.xferq.start = NULL;
725 sc->atrq.xferq.start = fwohci_start_atq;
726 sc->atrs.xferq.start = fwohci_start_ats;
727
728 sc->arrq.xferq.buf = NULL;
729 sc->arrs.xferq.buf = NULL;
730 sc->atrq.xferq.buf = NULL;
731 sc->atrs.xferq.buf = NULL;
732
733 sc->arrq.xferq.dmach = -1;
734 sc->arrs.xferq.dmach = -1;
735 sc->atrq.xferq.dmach = -1;
736 sc->atrs.xferq.dmach = -1;
737
738 sc->arrq.ndesc = 1;
739 sc->arrs.ndesc = 1;
740 sc->atrq.ndesc = 8; /* equal to maximum of mbuf chains */
741 sc->atrs.ndesc = 2;
742
743 sc->arrq.ndb = NDB;
744 sc->arrs.ndb = NDB / 2;
745 sc->atrq.ndb = NDB;
746 sc->atrs.ndb = NDB / 2;
747
748 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
749 sc->fc.it[i] = &sc->it[i].xferq;
750 sc->fc.ir[i] = &sc->ir[i].xferq;
751 sc->it[i].xferq.dmach = i;
752 sc->ir[i].xferq.dmach = i;
753 sc->it[i].ndb = 0;
754 sc->ir[i].ndb = 0;
755 }
756
757 sc->fc.tcode = tinfo;
758 sc->fc.dev = dev;
759
760 sc->fc.config_rom = fwdma_malloc(&sc->fc, CROMSIZE, CROMSIZE,
761 &sc->crom_dma, BUS_DMA_WAITOK);
762 if(sc->fc.config_rom == NULL){
763 device_printf(dev, "config_rom alloc failed.");
764 return ENOMEM;
765 }
766
767 #if 0
768 bzero(&sc->fc.config_rom[0], CROMSIZE);
769 sc->fc.config_rom[1] = 0x31333934;
770 sc->fc.config_rom[2] = 0xf000a002;
771 sc->fc.config_rom[3] = OREAD(sc, OHCI_EUID_HI);
772 sc->fc.config_rom[4] = OREAD(sc, OHCI_EUID_LO);
773 sc->fc.config_rom[5] = 0;
774 sc->fc.config_rom[0] = (4 << 24) | (5 << 16);
775
776 sc->fc.config_rom[0] |= fw_crc16(&sc->fc.config_rom[1], 5*4);
777 #endif
778
779
780 /* SID recieve buffer must align 2^11 */
781 #define OHCI_SIDSIZE (1 << 11)
782 sc->sid_buf = fwdma_malloc(&sc->fc, OHCI_SIDSIZE, OHCI_SIDSIZE,
783 &sc->sid_dma, BUS_DMA_WAITOK);
784 if (sc->sid_buf == NULL) {
785 device_printf(dev, "sid_buf alloc failed.");
786 return ENOMEM;
787 }
788
789 fwdma_malloc(&sc->fc, sizeof(uint32_t), sizeof(uint32_t),
790 &sc->dummy_dma, BUS_DMA_WAITOK);
791
792 if (sc->dummy_dma.v_addr == NULL) {
793 device_printf(dev, "dummy_dma alloc failed.");
794 return ENOMEM;
795 }
796
797 fwohci_db_init(sc, &sc->arrq);
798 if ((sc->arrq.flags & FWOHCI_DBCH_INIT) == 0)
799 return ENOMEM;
800
801 fwohci_db_init(sc, &sc->arrs);
802 if ((sc->arrs.flags & FWOHCI_DBCH_INIT) == 0)
803 return ENOMEM;
804
805 fwohci_db_init(sc, &sc->atrq);
806 if ((sc->atrq.flags & FWOHCI_DBCH_INIT) == 0)
807 return ENOMEM;
808
809 fwohci_db_init(sc, &sc->atrs);
810 if ((sc->atrs.flags & FWOHCI_DBCH_INIT) == 0)
811 return ENOMEM;
812
813 sc->fc.eui.hi = OREAD(sc, FWOHCIGUID_H);
814 sc->fc.eui.lo = OREAD(sc, FWOHCIGUID_L);
815 for( i = 0 ; i < 8 ; i ++)
816 ui[i] = FW_EUI64_BYTE(&sc->fc.eui,i);
817 device_printf(dev, "EUI64 %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
818 ui[0], ui[1], ui[2], ui[3], ui[4], ui[5], ui[6], ui[7]);
819
820 sc->fc.ioctl = fwohci_ioctl;
821 sc->fc.cyctimer = fwohci_cyctimer;
822 sc->fc.set_bmr = fwohci_set_bus_manager;
823 sc->fc.ibr = fwohci_ibr;
824 sc->fc.irx_enable = fwohci_irx_enable;
825 sc->fc.irx_disable = fwohci_irx_disable;
826
827 sc->fc.itx_enable = fwohci_itxbuf_enable;
828 sc->fc.itx_disable = fwohci_itx_disable;
829 #if BYTE_ORDER == BIG_ENDIAN
830 sc->fc.irx_post = fwohci_irx_post;
831 #else
832 sc->fc.irx_post = NULL;
833 #endif
834 sc->fc.itx_post = NULL;
835 sc->fc.timeout = fwohci_timeout;
836 sc->fc.poll = fwohci_poll;
837 sc->fc.set_intr = fwohci_set_intr;
838
839 sc->intmask = sc->irstat = sc->itstat = 0;
840
841 fw_init(&sc->fc);
842 fwohci_reset(sc, dev);
843 FWOHCI_INIT_END;
844
845 return 0;
846 }
847
848 void
849 fwohci_timeout(void *arg)
850 {
851 struct fwohci_softc *sc;
852
853 sc = (struct fwohci_softc *)arg;
854 }
855
856 uint32_t
857 fwohci_cyctimer(struct firewire_comm *fc)
858 {
859 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
860 return(OREAD(sc, OHCI_CYCLETIMER));
861 }
862
863 FWOHCI_DETACH()
864 {
865 int i;
866
867 FWOHCI_DETACH_START;
868 if (sc->sid_buf != NULL)
869 fwdma_free(&sc->fc, &sc->sid_dma);
870 if (sc->fc.config_rom != NULL)
871 fwdma_free(&sc->fc, &sc->crom_dma);
872
873 fwohci_db_free(&sc->arrq);
874 fwohci_db_free(&sc->arrs);
875
876 fwohci_db_free(&sc->atrq);
877 fwohci_db_free(&sc->atrs);
878
879 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
880 fwohci_db_free(&sc->it[i]);
881 fwohci_db_free(&sc->ir[i]);
882 }
883 FWOHCI_DETACH_END;
884
885 return 0;
886 }
887
888 #define LAST_DB(dbtr, db) do { \
889 struct fwohcidb_tr *_dbtr = (dbtr); \
890 int _cnt = _dbtr->dbcnt; \
891 db = &_dbtr->db[ (_cnt > 2) ? (_cnt -1) : 0]; \
892 } while (0)
893
894 static void
895 fwohci_execute_db(void *arg, bus_dma_segment_t *segs, int nseg, int error)
896 {
897 struct fwohcidb_tr *db_tr;
898 struct fwohcidb *db;
899 bus_dma_segment_t *s;
900 int i;
901
902 db_tr = (struct fwohcidb_tr *)arg;
903 db = &db_tr->db[db_tr->dbcnt];
904 if (error) {
905 if (firewire_debug || error != EFBIG)
906 printf("fwohci_execute_db: error=%d\n", error);
907 return;
908 }
909 for (i = 0; i < nseg; i++) {
910 s = &segs[i];
911 FWOHCI_DMA_WRITE(db->db.desc.addr, s->ds_addr);
912 FWOHCI_DMA_WRITE(db->db.desc.cmd, s->ds_len);
913 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
914 db++;
915 db_tr->dbcnt++;
916 }
917 }
918
919 static void
920 fwohci_execute_db2(void *arg, bus_dma_segment_t *segs, int nseg,
921 bus_size_t size, int error)
922 {
923 fwohci_execute_db(arg, segs, nseg, error);
924 }
925
926 static void
927 fwohci_start(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
928 {
929 int i, s;
930 int tcode, hdr_len, pl_off;
931 int fsegment = -1;
932 uint32_t off;
933 struct fw_xfer *xfer;
934 struct fw_pkt *fp;
935 struct fwohci_txpkthdr *ohcifp;
936 struct fwohcidb_tr *db_tr;
937 struct fwohcidb *db;
938 uint32_t *ld;
939 const struct tcode_info *info;
940 static int maxdesc=0;
941
942 if(&sc->atrq == dbch){
943 off = OHCI_ATQOFF;
944 }else if(&sc->atrs == dbch){
945 off = OHCI_ATSOFF;
946 }else{
947 return;
948 }
949
950 if (dbch->flags & FWOHCI_DBCH_FULL)
951 return;
952
953 s = splfw();
954 fwdma_sync_multiseg_all(dbch->am,
955 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
956 db_tr = dbch->top;
957 txloop:
958 xfer = STAILQ_FIRST(&dbch->xferq.q);
959 if(xfer == NULL){
960 goto kick;
961 }
962 if(dbch->xferq.queued == 0 ){
963 device_printf(sc->fc.dev, "TX queue empty\n");
964 }
965 STAILQ_REMOVE_HEAD(&dbch->xferq.q, link);
966 db_tr->xfer = xfer;
967 xfer->state = FWXF_START;
968
969 fp = &xfer->send.hdr;
970 tcode = fp->mode.common.tcode;
971
972 ohcifp = (struct fwohci_txpkthdr *) db_tr->db[1].db.immed;
973 info = &tinfo[tcode];
974 hdr_len = pl_off = info->hdr_len;
975
976 ld = &ohcifp->mode.ld[0];
977 ld[0] = ld[1] = ld[2] = ld[3] = 0;
978 for( i = 0 ; i < pl_off ; i+= 4)
979 ld[i/4] = fp->mode.ld[i/4];
980
981 ohcifp->mode.common.spd = xfer->send.spd & 0x7;
982 if (tcode == FWTCODE_STREAM ){
983 hdr_len = 8;
984 ohcifp->mode.stream.len = fp->mode.stream.len;
985 } else if (tcode == FWTCODE_PHY) {
986 hdr_len = 12;
987 ld[1] = fp->mode.ld[1];
988 ld[2] = fp->mode.ld[2];
989 ohcifp->mode.common.spd = 0;
990 ohcifp->mode.common.tcode = FWOHCITCODE_PHY;
991 } else {
992 ohcifp->mode.asycomm.dst = fp->mode.hdr.dst;
993 ohcifp->mode.asycomm.srcbus = OHCI_ASYSRCBUS;
994 ohcifp->mode.asycomm.tlrt |= FWRETRY_X;
995 }
996 db = &db_tr->db[0];
997 FWOHCI_DMA_WRITE(db->db.desc.cmd,
998 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | hdr_len);
999 FWOHCI_DMA_WRITE(db->db.desc.addr, 0);
1000 FWOHCI_DMA_WRITE(db->db.desc.res, 0);
1001 /* Specify bound timer of asy. responce */
1002 if(&sc->atrs == dbch){
1003 FWOHCI_DMA_WRITE(db->db.desc.res,
1004 (OREAD(sc, OHCI_CYCLETIMER) >> 12) + (1 << 13));
1005 }
1006 #if BYTE_ORDER == BIG_ENDIAN
1007 if (tcode == FWTCODE_WREQQ || tcode == FWTCODE_RRESQ)
1008 hdr_len = 12;
1009 for (i = 0; i < hdr_len/4; i ++)
1010 FWOHCI_DMA_WRITE(ld[i], ld[i]);
1011 #endif
1012
1013 again:
1014 db_tr->dbcnt = 2;
1015 db = &db_tr->db[db_tr->dbcnt];
1016 if (xfer->send.pay_len > 0) {
1017 int err;
1018 /* handle payload */
1019 if (xfer->mbuf == NULL) {
1020 err = fw_bus_dmamap_load(dbch->dmat, db_tr->dma_map,
1021 &xfer->send.payload[0], xfer->send.pay_len,
1022 fwohci_execute_db, db_tr,
1023 BUS_DMA_WAITOK);
1024 } else {
1025 /* XXX we can handle only 6 (=8-2) mbuf chains */
1026 err = fw_bus_dmamap_load_mbuf(dbch->dmat,
1027 db_tr->dma_map, xfer->mbuf,
1028 fwohci_execute_db2, db_tr,
1029 BUS_DMA_WAITOK);
1030 if (err == EFBIG) {
1031 struct mbuf *m0;
1032
1033 if (firewire_debug)
1034 device_printf(sc->fc.dev, "EFBIG.\n");
1035 m0 = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1036 if (m0 != NULL) {
1037 m_copydata(xfer->mbuf, 0,
1038 xfer->mbuf->m_pkthdr.len,
1039 mtod(m0, caddr_t));
1040 m0->m_len = m0->m_pkthdr.len =
1041 xfer->mbuf->m_pkthdr.len;
1042 m_freem(xfer->mbuf);
1043 xfer->mbuf = m0;
1044 goto again;
1045 }
1046 device_printf(sc->fc.dev, "m_getcl failed.\n");
1047 }
1048 }
1049 if (err)
1050 printf("dmamap_load: err=%d\n", err);
1051 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
1052 BUS_DMASYNC_PREWRITE);
1053 #if 0 /* OHCI_OUTPUT_MODE == 0 */
1054 for (i = 2; i < db_tr->dbcnt; i++)
1055 FWOHCI_DMA_SET(db_tr->db[i].db.desc.cmd,
1056 OHCI_OUTPUT_MORE);
1057 #endif
1058 }
1059 if (maxdesc < db_tr->dbcnt) {
1060 maxdesc = db_tr->dbcnt;
1061 if (firewire_debug)
1062 device_printf(sc->fc.dev, "maxdesc: %d\n", maxdesc);
1063 }
1064 /* last db */
1065 LAST_DB(db_tr, db);
1066 FWOHCI_DMA_SET(db->db.desc.cmd,
1067 OHCI_OUTPUT_LAST | OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1068 FWOHCI_DMA_WRITE(db->db.desc.depend,
1069 STAILQ_NEXT(db_tr, link)->bus_addr);
1070
1071 if(fsegment == -1 )
1072 fsegment = db_tr->dbcnt;
1073 if (dbch->pdb_tr != NULL) {
1074 LAST_DB(dbch->pdb_tr, db);
1075 FWOHCI_DMA_SET(db->db.desc.depend, db_tr->dbcnt);
1076 }
1077 dbch->pdb_tr = db_tr;
1078 db_tr = STAILQ_NEXT(db_tr, link);
1079 if(db_tr != dbch->bottom){
1080 goto txloop;
1081 } else {
1082 device_printf(sc->fc.dev, "fwohci_start: lack of db_trq\n");
1083 dbch->flags |= FWOHCI_DBCH_FULL;
1084 }
1085 kick:
1086 /* kick asy q */
1087 fwdma_sync_multiseg_all(dbch->am,
1088 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1089
1090 if(dbch->xferq.flag & FWXFERQ_RUNNING) {
1091 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
1092 } else {
1093 if (firewire_debug)
1094 device_printf(sc->fc.dev, "start AT DMA status=%x\n",
1095 OREAD(sc, OHCI_DMACTL(off)));
1096 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | fsegment);
1097 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1098 dbch->xferq.flag |= FWXFERQ_RUNNING;
1099 }
1100 CTR0(KTR_DEV, "start kick done");
1101 CTR0(KTR_DEV, "start kick done2");
1102
1103 dbch->top = db_tr;
1104 splx(s);
1105 return;
1106 }
1107
1108 static void
1109 fwohci_start_atq(struct firewire_comm *fc)
1110 {
1111 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1112 fwohci_start( sc, &(sc->atrq));
1113 return;
1114 }
1115
1116 static void
1117 fwohci_start_ats(struct firewire_comm *fc)
1118 {
1119 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1120 fwohci_start( sc, &(sc->atrs));
1121 return;
1122 }
1123
1124 void
1125 fwohci_txd(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1126 {
1127 int s, ch, err = 0;
1128 struct fwohcidb_tr *tr;
1129 struct fwohcidb *db;
1130 struct fw_xfer *xfer;
1131 uint32_t off;
1132 u_int stat, status;
1133 int packets;
1134 struct firewire_comm *fc = (struct firewire_comm *)sc;
1135
1136 if(&sc->atrq == dbch){
1137 off = OHCI_ATQOFF;
1138 ch = ATRQ_CH;
1139 }else if(&sc->atrs == dbch){
1140 off = OHCI_ATSOFF;
1141 ch = ATRS_CH;
1142 }else{
1143 return;
1144 }
1145 s = splfw();
1146 tr = dbch->bottom;
1147 packets = 0;
1148 fwdma_sync_multiseg_all(dbch->am,
1149 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1150 while(dbch->xferq.queued > 0){
1151 LAST_DB(tr, db);
1152 status = FWOHCI_DMA_READ(db->db.desc.res) >> OHCI_STATUS_SHIFT;
1153 if(!(status & OHCI_CNTL_DMA_ACTIVE)){
1154 if (fc->status != FWBUSRESET)
1155 /* maybe out of order?? */
1156 goto out;
1157 }
1158 if (tr->xfer->send.pay_len > 0) {
1159 fw_bus_dmamap_sync(dbch->dmat, tr->dma_map,
1160 BUS_DMASYNC_POSTWRITE);
1161 fw_bus_dmamap_unload(dbch->dmat, tr->dma_map);
1162 }
1163 #if 1
1164 if (firewire_debug > 1)
1165 dump_db(sc, ch);
1166 #endif
1167 if(status & OHCI_CNTL_DMA_DEAD) {
1168 /* Stop DMA */
1169 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1170 device_printf(sc->fc.dev, "force reset AT FIFO\n");
1171 OWRITE(sc, OHCI_HCCCTLCLR, OHCI_HCC_LINKEN);
1172 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_LPS | OHCI_HCC_LINKEN);
1173 OWRITE(sc, OHCI_DMACTLCLR(off), OHCI_CNTL_DMA_RUN);
1174 }
1175 stat = status & FWOHCIEV_MASK;
1176 switch(stat){
1177 case FWOHCIEV_ACKPEND:
1178 CTR0(KTR_DEV, "txd: ack pending");
1179 /* fall through */
1180 case FWOHCIEV_ACKCOMPL:
1181 err = 0;
1182 break;
1183 case FWOHCIEV_ACKBSA:
1184 case FWOHCIEV_ACKBSB:
1185 case FWOHCIEV_ACKBSX:
1186 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1187 err = EBUSY;
1188 break;
1189 case FWOHCIEV_FLUSHED:
1190 case FWOHCIEV_ACKTARD:
1191 device_printf(sc->fc.dev, "txd err=%2x %s\n", stat, fwohcicode[stat]);
1192 err = EAGAIN;
1193 break;
1194 case FWOHCIEV_MISSACK:
1195 case FWOHCIEV_UNDRRUN:
1196 case FWOHCIEV_OVRRUN:
1197 case FWOHCIEV_DESCERR:
1198 case FWOHCIEV_DTRDERR:
1199 case FWOHCIEV_TIMEOUT:
1200 case FWOHCIEV_TCODERR:
1201 case FWOHCIEV_UNKNOWN:
1202 case FWOHCIEV_ACKDERR:
1203 case FWOHCIEV_ACKTERR:
1204 default:
1205 device_printf(sc->fc.dev, "txd err=%2x %s\n",
1206 stat, fwohcicode[stat]);
1207 err = EINVAL;
1208 break;
1209 }
1210 if (tr->xfer != NULL) {
1211 xfer = tr->xfer;
1212 CTR0(KTR_DEV, "txd");
1213 if (xfer->state == FWXF_RCVD) {
1214 #if 0
1215 if (firewire_debug)
1216 printf("already rcvd\n");
1217 #endif
1218 fw_xfer_done(xfer);
1219 } else {
1220 xfer->state = FWXF_SENT;
1221 if (err == EBUSY && fc->status != FWBUSRESET) {
1222 xfer->state = FWXF_BUSY;
1223 xfer->resp = err;
1224 xfer->recv.pay_len = 0;
1225 fw_xfer_done(xfer);
1226 } else if (stat != FWOHCIEV_ACKPEND) {
1227 if (stat != FWOHCIEV_ACKCOMPL)
1228 xfer->state = FWXF_SENTERR;
1229 xfer->resp = err;
1230 xfer->recv.pay_len = 0;
1231 fw_xfer_done(xfer);
1232 }
1233 }
1234 /*
1235 * The watchdog timer takes care of split
1236 * transcation timeout for ACKPEND case.
1237 */
1238 } else {
1239 printf("this shouldn't happen\n");
1240 }
1241 dbch->xferq.queued --;
1242 tr->xfer = NULL;
1243
1244 fwdma_sync_multiseg_all(dbch->am, BUS_DMASYNC_PREREAD);
1245 packets ++;
1246 tr = STAILQ_NEXT(tr, link);
1247 dbch->bottom = tr;
1248 if (dbch->bottom == dbch->top) {
1249 /* we reaches the end of context program */
1250 if (firewire_debug && dbch->xferq.queued > 0)
1251 printf("queued > 0\n");
1252 break;
1253 }
1254 }
1255 out:
1256 if ((dbch->flags & FWOHCI_DBCH_FULL) && packets > 0) {
1257 printf("make free slot\n");
1258 dbch->flags &= ~FWOHCI_DBCH_FULL;
1259 fwohci_start(sc, dbch);
1260 }
1261 fwdma_sync_multiseg_all(
1262 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1263 splx(s);
1264 }
1265
1266 static void
1267 fwohci_db_free(struct fwohci_dbch *dbch)
1268 {
1269 struct fwohcidb_tr *db_tr;
1270 int idb;
1271
1272 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1273 return;
1274
1275 for(db_tr = STAILQ_FIRST(&dbch->db_trq), idb = 0; idb < dbch->ndb;
1276 db_tr = STAILQ_NEXT(db_tr, link), idb++){
1277 if ((dbch->xferq.flag & FWXFERQ_EXTBUF) == 0 &&
1278 db_tr->buf != NULL) {
1279 fwdma_free_size(dbch->dmat, db_tr->dma_map,
1280 db_tr->buf, dbch->xferq.psize);
1281 db_tr->buf = NULL;
1282 } else if (db_tr->dma_map != NULL)
1283 fw_bus_dmamap_destroy(dbch->dmat, db_tr->dma_map);
1284 }
1285 dbch->ndb = 0;
1286 db_tr = STAILQ_FIRST(&dbch->db_trq);
1287 fwdma_free_multiseg(dbch->am);
1288 free(db_tr, M_FW);
1289 STAILQ_INIT(&dbch->db_trq);
1290 dbch->flags &= ~FWOHCI_DBCH_INIT;
1291 }
1292
1293 static void
1294 fwohci_db_init(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1295 {
1296 int idb;
1297 struct fwohcidb_tr *db_tr;
1298
1299 if ((dbch->flags & FWOHCI_DBCH_INIT) != 0)
1300 goto out;
1301
1302 /* create dma_tag for buffers */
1303 #define MAX_REQCOUNT 0xffff
1304 if (fw_bus_dma_tag_create(/*parent*/ sc->fc.dmat,
1305 /*alignment*/ 1, /*boundary*/ 0,
1306 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT,
1307 /*highaddr*/ BUS_SPACE_MAXADDR,
1308 /*filter*/NULL, /*filterarg*/NULL,
1309 /*maxsize*/ dbch->xferq.psize,
1310 /*nsegments*/ dbch->ndesc > 3 ? dbch->ndesc - 2 : 1,
1311 /*maxsegsz*/ MAX_REQCOUNT,
1312 /*flags*/ 0,
1313 /*lockfunc*/busdma_lock_mutex,
1314 /*lockarg*/&Giant,
1315 &dbch->dmat))
1316 return;
1317
1318 /* allocate DB entries and attach one to each DMA channels */
1319 /* DB entry must start at 16 bytes bounary. */
1320 STAILQ_INIT(&dbch->db_trq);
1321 db_tr = (struct fwohcidb_tr *)
1322 malloc(sizeof(struct fwohcidb_tr) * dbch->ndb,
1323 M_FW, M_WAITOK | M_ZERO);
1324 if(db_tr == NULL){
1325 printf("fwohci_db_init: malloc(1) failed\n");
1326 return;
1327 }
1328
1329 #define DB_SIZE(x) (sizeof(struct fwohcidb) * (x)->ndesc)
1330 dbch->am = fwdma_malloc_multiseg(&sc->fc, DB_SIZE(dbch),
1331 DB_SIZE(dbch), dbch->ndb, BUS_DMA_WAITOK | BUS_DMA_COHERENT);
1332 if (dbch->am == NULL) {
1333 printf("fwohci_db_init: fwdma_malloc_multiseg failed\n");
1334 free(db_tr, M_FW);
1335 return;
1336 }
1337 /* Attach DB to DMA ch. */
1338 for(idb = 0 ; idb < dbch->ndb ; idb++){
1339 db_tr->dbcnt = 0;
1340 db_tr->db = (struct fwohcidb *)fwdma_v_addr(dbch->am, idb);
1341 db_tr->bus_addr = fwdma_bus_addr(dbch->am, idb);
1342 /* create dmamap for buffers */
1343 /* XXX do we need 4bytes alignment tag? */
1344 /* XXX don't alloc dma_map for AR */
1345 if (fw_bus_dmamap_create(dbch->dmat, 0, &db_tr->dma_map) != 0) {
1346 printf("fw_bus_dmamap_create failed\n");
1347 dbch->flags = FWOHCI_DBCH_INIT; /* XXX fake */
1348 fwohci_db_free(dbch);
1349 return;
1350 }
1351 STAILQ_INSERT_TAIL(&dbch->db_trq, db_tr, link);
1352 if (dbch->xferq.flag & FWXFERQ_EXTBUF) {
1353 if (idb % dbch->xferq.bnpacket == 0)
1354 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1355 ].start = (caddr_t)db_tr;
1356 if ((idb + 1) % dbch->xferq.bnpacket == 0)
1357 dbch->xferq.bulkxfer[idb / dbch->xferq.bnpacket
1358 ].end = (caddr_t)db_tr;
1359 }
1360 db_tr++;
1361 }
1362 STAILQ_LAST(&dbch->db_trq, fwohcidb_tr,link)->link.stqe_next
1363 = STAILQ_FIRST(&dbch->db_trq);
1364 out:
1365 dbch->xferq.queued = 0;
1366 dbch->pdb_tr = NULL;
1367 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1368 dbch->bottom = dbch->top;
1369 dbch->flags = FWOHCI_DBCH_INIT;
1370 }
1371
1372 static int
1373 fwohci_itx_disable(struct firewire_comm *fc, int dmach)
1374 {
1375 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1376 int sleepch;
1377
1378 OWRITE(sc, OHCI_ITCTLCLR(dmach),
1379 OHCI_CNTL_DMA_RUN | OHCI_CNTL_CYCMATCH_S);
1380 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1381 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1382 /* XXX we cannot free buffers until the DMA really stops */
1383 tsleep((void *)&sleepch, FWPRI, "fwitxd", hz);
1384 fwohci_db_free(&sc->it[dmach]);
1385 sc->it[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1386 return 0;
1387 }
1388
1389 static int
1390 fwohci_irx_disable(struct firewire_comm *fc, int dmach)
1391 {
1392 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1393 int sleepch;
1394
1395 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1396 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1397 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1398 /* XXX we cannot free buffers until the DMA really stops */
1399 tsleep((void *)&sleepch, FWPRI, "fwirxd", hz);
1400 fwohci_db_free(&sc->ir[dmach]);
1401 sc->ir[dmach].xferq.flag &= ~FWXFERQ_RUNNING;
1402 return 0;
1403 }
1404
1405 #if BYTE_ORDER == BIG_ENDIAN
1406 static void
1407 fwohci_irx_post (struct firewire_comm *fc , uint32_t *qld)
1408 {
1409 qld[0] = FWOHCI_DMA_READ(qld[0]);
1410 return;
1411 }
1412 #endif
1413
1414 static int
1415 fwohci_tx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1416 {
1417 int err = 0;
1418 int idb, z, i, dmach = 0, ldesc;
1419 uint32_t off = 0;
1420 struct fwohcidb_tr *db_tr;
1421 struct fwohcidb *db;
1422
1423 if(!(dbch->xferq.flag & FWXFERQ_EXTBUF)){
1424 err = EINVAL;
1425 return err;
1426 }
1427 z = dbch->ndesc;
1428 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1429 if( &sc->it[dmach] == dbch){
1430 off = OHCI_ITOFF(dmach);
1431 break;
1432 }
1433 }
1434 if(off == 0){
1435 err = EINVAL;
1436 return err;
1437 }
1438 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1439 return err;
1440 dbch->xferq.flag |= FWXFERQ_RUNNING;
1441 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1442 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1443 }
1444 db_tr = dbch->top;
1445 for (idb = 0; idb < dbch->ndb; idb ++) {
1446 fwohci_add_tx_buf(dbch, db_tr, idb);
1447 if(STAILQ_NEXT(db_tr, link) == NULL){
1448 break;
1449 }
1450 db = db_tr->db;
1451 ldesc = db_tr->dbcnt - 1;
1452 FWOHCI_DMA_WRITE(db[0].db.desc.depend,
1453 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1454 db[ldesc].db.desc.depend = db[0].db.desc.depend;
1455 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1456 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1457 FWOHCI_DMA_SET(
1458 db[ldesc].db.desc.cmd,
1459 OHCI_INTERRUPT_ALWAYS);
1460 /* OHCI 1.1 and above */
1461 FWOHCI_DMA_SET(
1462 db[0].db.desc.cmd,
1463 OHCI_INTERRUPT_ALWAYS);
1464 }
1465 }
1466 db_tr = STAILQ_NEXT(db_tr, link);
1467 }
1468 FWOHCI_DMA_CLEAR(
1469 dbch->bottom->db[dbch->bottom->dbcnt - 1].db.desc.depend, 0xf);
1470 return err;
1471 }
1472
1473 static int
1474 fwohci_rx_enable(struct fwohci_softc *sc, struct fwohci_dbch *dbch)
1475 {
1476 int err = 0;
1477 int idb, z, i, dmach = 0, ldesc;
1478 uint32_t off = 0;
1479 struct fwohcidb_tr *db_tr;
1480 struct fwohcidb *db;
1481
1482 z = dbch->ndesc;
1483 if(&sc->arrq == dbch){
1484 off = OHCI_ARQOFF;
1485 }else if(&sc->arrs == dbch){
1486 off = OHCI_ARSOFF;
1487 }else{
1488 for(dmach = 0 ; dmach < sc->fc.nisodma ; dmach++){
1489 if( &sc->ir[dmach] == dbch){
1490 off = OHCI_IROFF(dmach);
1491 break;
1492 }
1493 }
1494 }
1495 if(off == 0){
1496 err = EINVAL;
1497 return err;
1498 }
1499 if(dbch->xferq.flag & FWXFERQ_STREAM){
1500 if(dbch->xferq.flag & FWXFERQ_RUNNING)
1501 return err;
1502 }else{
1503 if(dbch->xferq.flag & FWXFERQ_RUNNING){
1504 err = EBUSY;
1505 return err;
1506 }
1507 }
1508 dbch->xferq.flag |= FWXFERQ_RUNNING;
1509 dbch->top = STAILQ_FIRST(&dbch->db_trq);
1510 for( i = 0, dbch->bottom = dbch->top; i < (dbch->ndb - 1); i++){
1511 dbch->bottom = STAILQ_NEXT(dbch->bottom, link);
1512 }
1513 db_tr = dbch->top;
1514 for (idb = 0; idb < dbch->ndb; idb ++) {
1515 fwohci_add_rx_buf(dbch, db_tr, idb, &sc->dummy_dma);
1516 if (STAILQ_NEXT(db_tr, link) == NULL)
1517 break;
1518 db = db_tr->db;
1519 ldesc = db_tr->dbcnt - 1;
1520 FWOHCI_DMA_WRITE(db[ldesc].db.desc.depend,
1521 STAILQ_NEXT(db_tr, link)->bus_addr | z);
1522 if(dbch->xferq.flag & FWXFERQ_EXTBUF){
1523 if(((idb + 1 ) % dbch->xferq.bnpacket) == 0){
1524 FWOHCI_DMA_SET(
1525 db[ldesc].db.desc.cmd,
1526 OHCI_INTERRUPT_ALWAYS);
1527 FWOHCI_DMA_CLEAR(
1528 db[ldesc].db.desc.depend,
1529 0xf);
1530 }
1531 }
1532 db_tr = STAILQ_NEXT(db_tr, link);
1533 }
1534 FWOHCI_DMA_CLEAR(
1535 dbch->bottom->db[db_tr->dbcnt - 1].db.desc.depend, 0xf);
1536 dbch->buf_offset = 0;
1537 fwdma_sync_multiseg_all(dbch->am,
1538 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1539 if(dbch->xferq.flag & FWXFERQ_STREAM){
1540 return err;
1541 }else{
1542 OWRITE(sc, OHCI_DMACMD(off), dbch->top->bus_addr | z);
1543 }
1544 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_RUN);
1545 return err;
1546 }
1547
1548 static int
1549 fwohci_next_cycle(struct firewire_comm *fc, int cycle_now)
1550 {
1551 int sec, cycle, cycle_match;
1552
1553 cycle = cycle_now & 0x1fff;
1554 sec = cycle_now >> 13;
1555 #define CYCLE_MOD 0x10
1556 #if 1
1557 #define CYCLE_DELAY 8 /* min delay to start DMA */
1558 #else
1559 #define CYCLE_DELAY 7000 /* min delay to start DMA */
1560 #endif
1561 cycle = cycle + CYCLE_DELAY;
1562 if (cycle >= 8000) {
1563 sec ++;
1564 cycle -= 8000;
1565 }
1566 cycle = roundup2(cycle, CYCLE_MOD);
1567 if (cycle >= 8000) {
1568 sec ++;
1569 if (cycle == 8000)
1570 cycle = 0;
1571 else
1572 cycle = CYCLE_MOD;
1573 }
1574 cycle_match = ((sec << 13) | cycle) & 0x7ffff;
1575
1576 return(cycle_match);
1577 }
1578
1579 static int
1580 fwohci_itxbuf_enable(struct firewire_comm *fc, int dmach)
1581 {
1582 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1583 int err = 0;
1584 unsigned short tag, ich;
1585 struct fwohci_dbch *dbch;
1586 int cycle_match, cycle_now, s, ldesc;
1587 uint32_t stat;
1588 struct fw_bulkxfer *first, *chunk, *prev;
1589 struct fw_xferq *it;
1590
1591 dbch = &sc->it[dmach];
1592 it = &dbch->xferq;
1593
1594 tag = (it->flag >> 6) & 3;
1595 ich = it->flag & 0x3f;
1596 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0) {
1597 dbch->ndb = it->bnpacket * it->bnchunk;
1598 dbch->ndesc = 3;
1599 fwohci_db_init(sc, dbch);
1600 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1601 return ENOMEM;
1602 err = fwohci_tx_enable(sc, dbch);
1603 }
1604 if(err)
1605 return err;
1606
1607 ldesc = dbch->ndesc - 1;
1608 s = splfw();
1609 prev = STAILQ_LAST(&it->stdma, fw_bulkxfer, link);
1610 while ((chunk = STAILQ_FIRST(&it->stvalid)) != NULL) {
1611 struct fwohcidb *db;
1612
1613 fwdma_sync_multiseg(it->buf, chunk->poffset, it->bnpacket,
1614 BUS_DMASYNC_PREWRITE);
1615 fwohci_txbufdb(sc, dmach, chunk);
1616 if (prev != NULL) {
1617 db = ((struct fwohcidb_tr *)(prev->end))->db;
1618 #if 0 /* XXX necessary? */
1619 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd,
1620 OHCI_BRANCH_ALWAYS);
1621 #endif
1622 #if 0 /* if bulkxfer->npacket changes */
1623 db[ldesc].db.desc.depend = db[0].db.desc.depend =
1624 ((struct fwohcidb_tr *)
1625 (chunk->start))->bus_addr | dbch->ndesc;
1626 #else
1627 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
1628 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1629 #endif
1630 }
1631 STAILQ_REMOVE_HEAD(&it->stvalid, link);
1632 STAILQ_INSERT_TAIL(&it->stdma, chunk, link);
1633 prev = chunk;
1634 }
1635 fwdma_sync_multiseg_all(dbch->am,
1636 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1637 splx(s);
1638 stat = OREAD(sc, OHCI_ITCTL(dmach));
1639 if (firewire_debug && (stat & OHCI_CNTL_CYCMATCH_S))
1640 printf("stat 0x%x\n", stat);
1641
1642 if (stat & (OHCI_CNTL_DMA_ACTIVE | OHCI_CNTL_CYCMATCH_S))
1643 return 0;
1644
1645 #if 0
1646 OWRITE(sc, OHCI_ITCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1647 #endif
1648 OWRITE(sc, OHCI_IT_MASKCLR, 1 << dmach);
1649 OWRITE(sc, OHCI_IT_STATCLR, 1 << dmach);
1650 OWRITE(sc, OHCI_IT_MASK, 1 << dmach);
1651 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IT);
1652
1653 first = STAILQ_FIRST(&it->stdma);
1654 OWRITE(sc, OHCI_ITCMD(dmach),
1655 ((struct fwohcidb_tr *)(first->start))->bus_addr | dbch->ndesc);
1656 if (firewire_debug > 1) {
1657 printf("fwohci_itxbuf_enable: kick 0x%08x\n", stat);
1658 #if 1
1659 dump_dma(sc, ITX_CH + dmach);
1660 #endif
1661 }
1662 if ((stat & OHCI_CNTL_DMA_RUN) == 0) {
1663 #if 1
1664 /* Don't start until all chunks are buffered */
1665 if (STAILQ_FIRST(&it->stfree) != NULL)
1666 goto out;
1667 #endif
1668 #if 1
1669 /* Clear cycle match counter bits */
1670 OWRITE(sc, OHCI_ITCTLCLR(dmach), 0xffff0000);
1671
1672 /* 2bit second + 13bit cycle */
1673 cycle_now = (fc->cyctimer(fc) >> 12) & 0x7fff;
1674 cycle_match = fwohci_next_cycle(fc, cycle_now);
1675
1676 OWRITE(sc, OHCI_ITCTL(dmach),
1677 OHCI_CNTL_CYCMATCH_S | (cycle_match << 16)
1678 | OHCI_CNTL_DMA_RUN);
1679 #else
1680 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_RUN);
1681 #endif
1682 if (firewire_debug > 1) {
1683 printf("cycle_match: 0x%04x->0x%04x\n",
1684 cycle_now, cycle_match);
1685 dump_dma(sc, ITX_CH + dmach);
1686 dump_db(sc, ITX_CH + dmach);
1687 }
1688 } else if ((stat & OHCI_CNTL_CYCMATCH_S) == 0) {
1689 device_printf(sc->fc.dev,
1690 "IT DMA underrun (0x%08x)\n", stat);
1691 OWRITE(sc, OHCI_ITCTL(dmach), OHCI_CNTL_DMA_WAKE);
1692 }
1693 out:
1694 return err;
1695 }
1696
1697 static int
1698 fwohci_irx_enable(struct firewire_comm *fc, int dmach)
1699 {
1700 struct fwohci_softc *sc = (struct fwohci_softc *)fc;
1701 int err = 0, s, ldesc;
1702 unsigned short tag, ich;
1703 uint32_t stat;
1704 struct fwohci_dbch *dbch;
1705 struct fwohcidb_tr *db_tr;
1706 struct fw_bulkxfer *first, *prev, *chunk;
1707 struct fw_xferq *ir;
1708
1709 dbch = &sc->ir[dmach];
1710 ir = &dbch->xferq;
1711
1712 if ((ir->flag & FWXFERQ_RUNNING) == 0) {
1713 tag = (ir->flag >> 6) & 3;
1714 ich = ir->flag & 0x3f;
1715 OWRITE(sc, OHCI_IRMATCH(dmach), tagbit[tag] | ich);
1716
1717 ir->queued = 0;
1718 dbch->ndb = ir->bnpacket * ir->bnchunk;
1719 dbch->ndesc = 2;
1720 fwohci_db_init(sc, dbch);
1721 if ((dbch->flags & FWOHCI_DBCH_INIT) == 0)
1722 return ENOMEM;
1723 err = fwohci_rx_enable(sc, dbch);
1724 }
1725 if(err)
1726 return err;
1727
1728 first = STAILQ_FIRST(&ir->stfree);
1729 if (first == NULL) {
1730 device_printf(fc->dev, "IR DMA no free chunk\n");
1731 return 0;
1732 }
1733
1734 ldesc = dbch->ndesc - 1;
1735 s = splfw();
1736 prev = STAILQ_LAST(&ir->stdma, fw_bulkxfer, link);
1737 while ((chunk = STAILQ_FIRST(&ir->stfree)) != NULL) {
1738 struct fwohcidb *db;
1739
1740 #if 1 /* XXX for if_fwe */
1741 if (chunk->mbuf != NULL) {
1742 db_tr = (struct fwohcidb_tr *)(chunk->start);
1743 db_tr->dbcnt = 1;
1744 err = fw_bus_dmamap_load_mbuf(
1745 dbch->dmat, db_tr->dma_map,
1746 chunk->mbuf, fwohci_execute_db2, db_tr,
1747 BUS_DMA_WAITOK);
1748 FWOHCI_DMA_SET(db_tr->db[1].db.desc.cmd,
1749 OHCI_UPDATE | OHCI_INPUT_LAST |
1750 OHCI_INTERRUPT_ALWAYS | OHCI_BRANCH_ALWAYS);
1751 }
1752 #endif
1753 db = ((struct fwohcidb_tr *)(chunk->end))->db;
1754 FWOHCI_DMA_WRITE(db[ldesc].db.desc.res, 0);
1755 FWOHCI_DMA_CLEAR(db[ldesc].db.desc.depend, 0xf);
1756 if (prev != NULL) {
1757 db = ((struct fwohcidb_tr *)(prev->end))->db;
1758 FWOHCI_DMA_SET(db[ldesc].db.desc.depend, dbch->ndesc);
1759 }
1760 STAILQ_REMOVE_HEAD(&ir->stfree, link);
1761 STAILQ_INSERT_TAIL(&ir->stdma, chunk, link);
1762 prev = chunk;
1763 }
1764 fwdma_sync_multiseg_all(dbch->am,
1765 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1766 splx(s);
1767 stat = OREAD(sc, OHCI_IRCTL(dmach));
1768 if (stat & OHCI_CNTL_DMA_ACTIVE)
1769 return 0;
1770 if (stat & OHCI_CNTL_DMA_RUN) {
1771 OWRITE(sc, OHCI_IRCTLCLR(dmach), OHCI_CNTL_DMA_RUN);
1772 device_printf(sc->fc.dev, "IR DMA overrun (0x%08x)\n", stat);
1773 }
1774
1775 if (firewire_debug)
1776 printf("start IR DMA 0x%x\n", stat);
1777 OWRITE(sc, OHCI_IR_MASKCLR, 1 << dmach);
1778 OWRITE(sc, OHCI_IR_STATCLR, 1 << dmach);
1779 OWRITE(sc, OHCI_IR_MASK, 1 << dmach);
1780 OWRITE(sc, OHCI_IRCTLCLR(dmach), 0xf0000000);
1781 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_ISOHDR);
1782 OWRITE(sc, OHCI_IRCMD(dmach),
1783 ((struct fwohcidb_tr *)(first->start))->bus_addr
1784 | dbch->ndesc);
1785 OWRITE(sc, OHCI_IRCTL(dmach), OHCI_CNTL_DMA_RUN);
1786 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_DMA_IR);
1787 #if 0
1788 dump_db(sc, IRX_CH + dmach);
1789 #endif
1790 return err;
1791 }
1792
1793 FWOHCI_STOP()
1794 {
1795 FWOHCI_STOP_START;
1796 u_int i;
1797
1798 /* Now stopping all DMA channel */
1799 OWRITE(sc, OHCI_ARQCTLCLR, OHCI_CNTL_DMA_RUN);
1800 OWRITE(sc, OHCI_ARSCTLCLR, OHCI_CNTL_DMA_RUN);
1801 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1802 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1803
1804 for( i = 0 ; i < sc->fc.nisodma ; i ++ ){
1805 OWRITE(sc, OHCI_IRCTLCLR(i), OHCI_CNTL_DMA_RUN);
1806 OWRITE(sc, OHCI_ITCTLCLR(i), OHCI_CNTL_DMA_RUN);
1807 }
1808
1809 /* FLUSH FIFO and reset Transmitter/Reciever */
1810 OWRITE(sc, OHCI_HCCCTL, OHCI_HCC_RESET);
1811
1812 /* Stop interrupt */
1813 OWRITE(sc, FWOHCI_INTMASKCLR,
1814 OHCI_INT_EN | OHCI_INT_ERR | OHCI_INT_PHY_SID
1815 | OHCI_INT_PHY_INT
1816 | OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS
1817 | OHCI_INT_DMA_PRRQ | OHCI_INT_DMA_PRRS
1818 | OHCI_INT_DMA_ARRQ | OHCI_INT_DMA_ARRS
1819 | OHCI_INT_PHY_BUS_R);
1820
1821 if (sc->fc.arq !=0 && sc->fc.arq->maxq > 0)
1822 fw_drain_txq(&sc->fc);
1823
1824 /* XXX Link down? Bus reset? */
1825 FWOHCI_STOP_RETURN(0);
1826 }
1827
1828 #if defined(__NetBSD__)
1829 static void
1830 fwohci_power(int why, void *arg)
1831 {
1832 struct fwohci_softc *sc = arg;
1833 int s;
1834
1835 s = splbio();
1836 switch (why) {
1837 case PWR_SUSPEND:
1838 case PWR_STANDBY:
1839 fwohci_stop(arg);
1840 break;
1841 case PWR_RESUME:
1842 fwohci_resume(sc, sc->fc.dev);
1843 break;
1844 case PWR_SOFTSUSPEND:
1845 case PWR_SOFTSTANDBY:
1846 case PWR_SOFTRESUME:
1847 break;
1848 }
1849 splx(s);
1850 }
1851 #endif
1852
1853 int
1854 fwohci_resume(struct fwohci_softc *sc, device_t dev)
1855 {
1856 int i;
1857 struct fw_xferq *ir;
1858 struct fw_bulkxfer *chunk;
1859
1860 fwohci_reset(sc, dev);
1861 /* XXX resume isochronous receive automatically. (how about TX?) */
1862 for(i = 0; i < sc->fc.nisodma; i ++) {
1863 ir = &sc->ir[i].xferq;
1864 if((ir->flag & FWXFERQ_RUNNING) != 0) {
1865 device_printf(sc->fc.dev,
1866 "resume iso receive ch: %d\n", i);
1867 ir->flag &= ~FWXFERQ_RUNNING;
1868 /* requeue stdma to stfree */
1869 while((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
1870 STAILQ_REMOVE_HEAD(&ir->stdma, link);
1871 STAILQ_INSERT_TAIL(&ir->stfree, chunk, link);
1872 }
1873 sc->fc.irx_enable(&sc->fc, i);
1874 }
1875 }
1876
1877 #if defined(__FreeBSD__)
1878 bus_generic_resume(dev);
1879 #endif
1880 sc->fc.ibr(&sc->fc);
1881 return 0;
1882 }
1883
1884 #define ACK_ALL
1885 static void
1886 fwohci_intr_body(struct fwohci_softc *sc, uint32_t stat, int count)
1887 {
1888 uint32_t irstat, itstat;
1889 u_int i;
1890 struct firewire_comm *fc = (struct firewire_comm *)sc;
1891
1892 CTR0(KTR_DEV, "fwohci_intr_body");
1893 #ifdef OHCI_DEBUG
1894 if(stat & OREAD(sc, FWOHCI_INTMASK))
1895 device_printf(fc->dev, "INTERRUPT < %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s> 0x%08x, 0x%08x\n",
1896 stat & OHCI_INT_EN ? "DMA_EN ":"",
1897 stat & OHCI_INT_PHY_REG ? "PHY_REG ":"",
1898 stat & OHCI_INT_CYC_LONG ? "CYC_LONG ":"",
1899 stat & OHCI_INT_ERR ? "INT_ERR ":"",
1900 stat & OHCI_INT_CYC_ERR ? "CYC_ERR ":"",
1901 stat & OHCI_INT_CYC_LOST ? "CYC_LOST ":"",
1902 stat & OHCI_INT_CYC_64SECOND ? "CYC_64SECOND ":"",
1903 stat & OHCI_INT_CYC_START ? "CYC_START ":"",
1904 stat & OHCI_INT_PHY_INT ? "PHY_INT ":"",
1905 stat & OHCI_INT_PHY_BUS_R ? "BUS_RESET ":"",
1906 stat & OHCI_INT_PHY_SID ? "SID ":"",
1907 stat & OHCI_INT_LR_ERR ? "DMA_LR_ERR ":"",
1908 stat & OHCI_INT_PW_ERR ? "DMA_PW_ERR ":"",
1909 stat & OHCI_INT_DMA_IR ? "DMA_IR ":"",
1910 stat & OHCI_INT_DMA_IT ? "DMA_IT " :"",
1911 stat & OHCI_INT_DMA_PRRS ? "DMA_PRRS " :"",
1912 stat & OHCI_INT_DMA_PRRQ ? "DMA_PRRQ " :"",
1913 stat & OHCI_INT_DMA_ARRS ? "DMA_ARRS " :"",
1914 stat & OHCI_INT_DMA_ARRQ ? "DMA_ARRQ " :"",
1915 stat & OHCI_INT_DMA_ATRS ? "DMA_ATRS " :"",
1916 stat & OHCI_INT_DMA_ATRQ ? "DMA_ATRQ " :"",
1917 stat, OREAD(sc, FWOHCI_INTMASK)
1918 );
1919 #endif
1920 /* Bus reset */
1921 if(stat & OHCI_INT_PHY_BUS_R ){
1922 if (fc->status == FWBUSRESET)
1923 goto busresetout;
1924 /* Disable bus reset interrupt until sid recv. */
1925 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_PHY_BUS_R);
1926
1927 device_printf(fc->dev, "BUS reset\n");
1928 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
1929 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCSRC);
1930
1931 OWRITE(sc, OHCI_ATQCTLCLR, OHCI_CNTL_DMA_RUN);
1932 sc->atrq.xferq.flag &= ~FWXFERQ_RUNNING;
1933 OWRITE(sc, OHCI_ATSCTLCLR, OHCI_CNTL_DMA_RUN);
1934 sc->atrs.xferq.flag &= ~FWXFERQ_RUNNING;
1935
1936 #ifndef ACK_ALL
1937 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_BUS_R);
1938 #endif
1939 fw_busreset(fc);
1940 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
1941 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
1942 }
1943 busresetout:
1944 if((stat & OHCI_INT_DMA_IR )){
1945 #ifndef ACK_ALL
1946 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IR);
1947 #endif
1948 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__)
1949 irstat = sc->irstat;
1950 sc->irstat = 0;
1951 #else
1952 irstat = atomic_readandclear_int(&sc->irstat);
1953 #endif
1954 for(i = 0; i < fc->nisodma ; i++){
1955 struct fwohci_dbch *dbch;
1956
1957 if((irstat & (1 << i)) != 0){
1958 dbch = &sc->ir[i];
1959 if ((dbch->xferq.flag & FWXFERQ_OPEN) == 0) {
1960 device_printf(sc->fc.dev,
1961 "dma(%d) not active\n", i);
1962 continue;
1963 }
1964 fwohci_rbuf_update(sc, i);
1965 }
1966 }
1967 }
1968 if((stat & OHCI_INT_DMA_IT )){
1969 #ifndef ACK_ALL
1970 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_IT);
1971 #endif
1972 #if defined(__DragonFly__) || __FreeBSD_version < 500000 || defined(__NetBSD__)
1973 itstat = sc->itstat;
1974 sc->itstat = 0;
1975 #else
1976 itstat = atomic_readandclear_int(&sc->itstat);
1977 #endif
1978 for(i = 0; i < fc->nisodma ; i++){
1979 if((itstat & (1 << i)) != 0){
1980 fwohci_tbuf_update(sc, i);
1981 }
1982 }
1983 }
1984 if((stat & OHCI_INT_DMA_PRRS )){
1985 #ifndef ACK_ALL
1986 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRS);
1987 #endif
1988 #if 0
1989 dump_dma(sc, ARRS_CH);
1990 dump_db(sc, ARRS_CH);
1991 #endif
1992 fwohci_arcv(sc, &sc->arrs, count);
1993 }
1994 if((stat & OHCI_INT_DMA_PRRQ )){
1995 #ifndef ACK_ALL
1996 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_PRRQ);
1997 #endif
1998 #if 0
1999 dump_dma(sc, ARRQ_CH);
2000 dump_db(sc, ARRQ_CH);
2001 #endif
2002 fwohci_arcv(sc, &sc->arrq, count);
2003 }
2004 if (stat & OHCI_INT_CYC_LOST) {
2005 if (sc->cycle_lost >= 0)
2006 sc->cycle_lost ++;
2007 if (sc->cycle_lost > 10) {
2008 sc->cycle_lost = -1;
2009 #if 0
2010 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCTIMER);
2011 #endif
2012 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_CYC_LOST);
2013 device_printf(fc->dev, "too many cycle lost, "
2014 "no cycle master presents?\n");
2015 }
2016 }
2017 if(stat & OHCI_INT_PHY_SID){
2018 uint32_t *buf, node_id;
2019 int plen;
2020
2021 #ifndef ACK_ALL
2022 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_SID);
2023 #endif
2024 /* Enable bus reset interrupt */
2025 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_PHY_BUS_R);
2026 /* Allow async. request to us */
2027 OWRITE(sc, OHCI_AREQHI, 1 << 31);
2028 /* XXX insecure ?? */
2029 /* allow from all nodes */
2030 OWRITE(sc, OHCI_PREQHI, 0x7fffffff);
2031 OWRITE(sc, OHCI_PREQLO, 0xffffffff);
2032 /* 0 to 4GB regison */
2033 OWRITE(sc, OHCI_PREQUPPER, 0x10000);
2034 /* Set ATRetries register */
2035 OWRITE(sc, OHCI_ATRETRY, 1<<(13+16) | 0xfff);
2036 /*
2037 ** Checking whether the node is root or not. If root, turn on
2038 ** cycle master.
2039 */
2040 node_id = OREAD(sc, FWOHCI_NODEID);
2041 plen = OREAD(sc, OHCI_SID_CNT);
2042
2043 device_printf(fc->dev, "node_id=0x%08x, gen=%d, ",
2044 node_id, (plen >> 16) & 0xff);
2045 if (!(node_id & OHCI_NODE_VALID)) {
2046 printf("Bus reset failure\n");
2047 goto sidout;
2048 }
2049
2050 /* cycle timer */
2051 sc->cycle_lost = 0;
2052 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_CYC_LOST);
2053 if ((node_id & OHCI_NODE_ROOT) && !nocyclemaster) {
2054 printf("CYCLEMASTER mode\n");
2055 OWRITE(sc, OHCI_LNKCTL,
2056 OHCI_CNTL_CYCMTR | OHCI_CNTL_CYCTIMER);
2057 } else {
2058 printf("non CYCLEMASTER mode\n");
2059 OWRITE(sc, OHCI_LNKCTLCLR, OHCI_CNTL_CYCMTR);
2060 OWRITE(sc, OHCI_LNKCTL, OHCI_CNTL_CYCTIMER);
2061 }
2062
2063 fc->nodeid = node_id & 0x3f;
2064
2065 if (plen & OHCI_SID_ERR) {
2066 device_printf(fc->dev, "SID Error\n");
2067 goto sidout;
2068 }
2069 plen &= OHCI_SID_CNT_MASK;
2070 if (plen < 4 || plen > OHCI_SIDSIZE) {
2071 device_printf(fc->dev, "invalid SID len = %d\n", plen);
2072 goto sidout;
2073 }
2074 plen -= 4; /* chop control info */
2075 buf = (uint32_t *)malloc(OHCI_SIDSIZE, M_FW, M_NOWAIT);
2076 if (buf == NULL) {
2077 device_printf(fc->dev, "malloc failed\n");
2078 goto sidout;
2079 }
2080 for (i = 0; i < plen / 4; i ++)
2081 buf[i] = FWOHCI_DMA_READ(sc->sid_buf[i+1]);
2082 #if defined(__NetBSD__) && defined(macppc)
2083 /* XXX required as bootdisk for macppc. */
2084 delay(500000);
2085 #endif
2086 #if 1 /* XXX needed?? */
2087 /* pending all pre-bus_reset packets */
2088 fwohci_txd(sc, &sc->atrq);
2089 fwohci_txd(sc, &sc->atrs);
2090 fwohci_arcv(sc, &sc->arrs, -1);
2091 fwohci_arcv(sc, &sc->arrq, -1);
2092 fw_drain_txq(fc);
2093 #endif
2094 fw_sidrcv(fc, buf, plen);
2095 free(buf, M_FW);
2096 }
2097 sidout:
2098 if((stat & OHCI_INT_DMA_ATRQ )){
2099 #ifndef ACK_ALL
2100 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRQ);
2101 #endif
2102 fwohci_txd(sc, &(sc->atrq));
2103 }
2104 if((stat & OHCI_INT_DMA_ATRS )){
2105 #ifndef ACK_ALL
2106 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_DMA_ATRS);
2107 #endif
2108 fwohci_txd(sc, &(sc->atrs));
2109 }
2110 if((stat & OHCI_INT_PW_ERR )){
2111 #ifndef ACK_ALL
2112 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PW_ERR);
2113 #endif
2114 device_printf(fc->dev, "posted write error\n");
2115 }
2116 if((stat & OHCI_INT_ERR )){
2117 #ifndef ACK_ALL
2118 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_ERR);
2119 #endif
2120 device_printf(fc->dev, "unrecoverable error\n");
2121 }
2122 if((stat & OHCI_INT_PHY_INT)) {
2123 #ifndef ACK_ALL
2124 OWRITE(sc, FWOHCI_INTSTATCLR, OHCI_INT_PHY_INT);
2125 #endif
2126 device_printf(fc->dev, "phy int\n");
2127 }
2128
2129 CTR0(KTR_DEV, "fwohci_intr_body done");
2130 return;
2131 }
2132
2133 #if FWOHCI_TASKQUEUE
2134 static void
2135 fwohci_complete(void *arg, int pending)
2136 {
2137 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2138 uint32_t stat;
2139
2140 again:
2141 stat = atomic_readandclear_int(&sc->intstat);
2142 if (stat) {
2143 FW_LOCK;
2144 fwohci_intr_body(sc, stat, -1);
2145 FW_UNLOCK;
2146 } else
2147 return;
2148 goto again;
2149 }
2150 #endif
2151
2152 static uint32_t
2153 fwochi_check_stat(struct fwohci_softc *sc)
2154 {
2155 uint32_t stat, irstat, itstat;
2156
2157 stat = OREAD(sc, FWOHCI_INTSTAT);
2158 CTR1(KTR_DEV, "fwoch_check_stat 0x%08x", stat);
2159 if (stat == 0xffffffff) {
2160 device_printf(sc->fc.dev,
2161 "device physically ejected?\n");
2162 return(stat);
2163 }
2164 #ifdef ACK_ALL
2165 if (stat)
2166 OWRITE(sc, FWOHCI_INTSTATCLR, stat);
2167 #endif
2168 if (stat & OHCI_INT_DMA_IR) {
2169 irstat = OREAD(sc, OHCI_IR_STAT);
2170 OWRITE(sc, OHCI_IR_STATCLR, irstat);
2171 atomic_set_int(&sc->irstat, irstat);
2172 }
2173 if (stat & OHCI_INT_DMA_IT) {
2174 itstat = OREAD(sc, OHCI_IT_STAT);
2175 OWRITE(sc, OHCI_IT_STATCLR, itstat);
2176 atomic_set_int(&sc->itstat, itstat);
2177 }
2178 return(stat);
2179 }
2180
2181 FW_INTR(fwohci)
2182 {
2183 struct fwohci_softc *sc = (struct fwohci_softc *)arg;
2184 uint32_t stat;
2185 #if !FWOHCI_TASKQUEUE
2186 uint32_t bus_reset = 0;
2187 #endif
2188
2189 if (!(sc->intmask & OHCI_INT_EN)) {
2190 /* polling mode */
2191 FW_INTR_RETURN(0);
2192 }
2193
2194 #if !FWOHCI_TASKQUEUE
2195 again:
2196 #endif
2197 CTR0(KTR_DEV, "fwohci_intr");
2198 stat = fwochi_check_stat(sc);
2199 if (stat == 0 || stat == 0xffffffff)
2200 FW_INTR_RETURN(1);
2201 #if FWOHCI_TASKQUEUE
2202 atomic_set_int(&sc->intstat, stat);
2203 /* XXX mask bus reset intr. during bus reset phase */
2204 if (stat)
2205 #if 1
2206 taskqueue_enqueue_fast(taskqueue_fast,
2207 &sc->fwohci_task_complete);
2208 #else
2209 taskqueue_enqueue(taskqueue_swi,
2210 &sc->fwohci_task_complete);
2211 #endif
2212 #else
2213 /* We cannot clear bus reset event during bus reset phase */
2214 if ((stat & ~bus_reset) == 0)
2215 FW_INTR_RETURN(1);
2216 bus_reset = stat & OHCI_INT_PHY_BUS_R;
2217 fwohci_intr_body(sc, stat, -1);
2218 goto again;
2219 #endif
2220 CTR0(KTR_DEV, "fwohci_intr end");
2221 }
2222
2223 void
2224 fwohci_poll(struct firewire_comm *fc, int quick, int count)
2225 {
2226 int s;
2227 uint32_t stat;
2228 struct fwohci_softc *sc;
2229
2230
2231 sc = (struct fwohci_softc *)fc;
2232 stat = OHCI_INT_DMA_IR | OHCI_INT_DMA_IT |
2233 OHCI_INT_DMA_PRRS | OHCI_INT_DMA_PRRQ |
2234 OHCI_INT_DMA_ATRQ | OHCI_INT_DMA_ATRS;
2235 #if 0
2236 if (!quick) {
2237 #else
2238 if (1) {
2239 #endif
2240 stat = fwochi_check_stat(sc);
2241 if (stat == 0 || stat == 0xffffffff)
2242 return;
2243 }
2244 s = splfw();
2245 fwohci_intr_body(sc, stat, count);
2246 splx(s);
2247 }
2248
2249 static void
2250 fwohci_set_intr(struct firewire_comm *fc, int enable)
2251 {
2252 struct fwohci_softc *sc;
2253
2254 sc = (struct fwohci_softc *)fc;
2255 if (firewire_debug)
2256 device_printf(sc->fc.dev, "fwohci_set_intr: %d\n", enable);
2257 if (enable) {
2258 sc->intmask |= OHCI_INT_EN;
2259 OWRITE(sc, FWOHCI_INTMASK, OHCI_INT_EN);
2260 } else {
2261 sc->intmask &= ~OHCI_INT_EN;
2262 OWRITE(sc, FWOHCI_INTMASKCLR, OHCI_INT_EN);
2263 }
2264 }
2265
2266 static void
2267 fwohci_tbuf_update(struct fwohci_softc *sc, int dmach)
2268 {
2269 struct firewire_comm *fc = &sc->fc;
2270 struct fwohcidb *db;
2271 struct fw_bulkxfer *chunk;
2272 struct fw_xferq *it;
2273 uint32_t stat, count;
2274 int s, w=0, ldesc;
2275
2276 it = fc->it[dmach];
2277 ldesc = sc->it[dmach].ndesc - 1;
2278 s = splfw(); /* unnecessary ? */
2279 fwdma_sync_multiseg_all(sc->it[dmach].am, BUS_DMASYNC_POSTREAD);
2280 if (firewire_debug)
2281 dump_db(sc, ITX_CH + dmach);
2282 while ((chunk = STAILQ_FIRST(&it->stdma)) != NULL) {
2283 db = ((struct fwohcidb_tr *)(chunk->end))->db;
2284 stat = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2285 >> OHCI_STATUS_SHIFT;
2286 db = ((struct fwohcidb_tr *)(chunk->start))->db;
2287 /* timestamp */
2288 count = FWOHCI_DMA_READ(db[ldesc].db.desc.res)
2289 & OHCI_COUNT_MASK;
2290 if (stat == 0)
2291 break;
2292 STAILQ_REMOVE_HEAD(&it->stdma, link);
2293 switch (stat & FWOHCIEV_MASK){
2294 case FWOHCIEV_ACKCOMPL:
2295 #if 0
2296 device_printf(fc->dev, "0x%08x\n", count);
2297 #endif
2298 break;
2299 default:
2300 device_printf(fc->dev,
2301 "Isochronous transmit err %02x(%s)\n",
2302 stat, fwohcicode[stat & 0x1f]);
2303 }
2304 STAILQ_INSERT_TAIL(&it->stfree, chunk, link);
2305 w++;
2306 }
2307 splx(s);
2308 if (w)
2309 wakeup(it);
2310 }
2311
2312 static void
2313 fwohci_rbuf_update(struct fwohci_softc *sc, int dmach)
2314 {
2315 struct firewire_comm *fc = &sc->fc;
2316 struct fwohcidb_tr *db_tr;
2317 struct fw_bulkxfer *chunk;
2318 struct fw_xferq *ir;
2319 uint32_t stat;
2320 int s, w=0, ldesc;
2321
2322 ir = fc->ir[dmach];
2323 ldesc = sc->ir[dmach].ndesc - 1;
2324 #if 0
2325 dump_db(sc, dmach);
2326 #endif
2327 s = splfw();
2328 fwdma_sync_multiseg_all(sc->ir[dmach].am, BUS_DMASYNC_POSTREAD);
2329 while ((chunk = STAILQ_FIRST(&ir->stdma)) != NULL) {
2330 db_tr = (struct fwohcidb_tr *)chunk->end;
2331 stat = FWOHCI_DMA_READ(db_tr->db[ldesc].db.desc.res)
2332 >> OHCI_STATUS_SHIFT;
2333 if (stat == 0)
2334 break;
2335
2336 if (chunk->mbuf != NULL) {
2337 fw_bus_dmamap_sync(sc->ir[dmach].dmat, db_tr->dma_map,
2338 BUS_DMASYNC_POSTREAD);
2339 fw_bus_dmamap_unload(
2340 sc->ir[dmach].dmat, db_tr->dma_map);
2341 } else if (ir->buf != NULL) {
2342 fwdma_sync_multiseg(ir->buf, chunk->poffset,
2343 ir->bnpacket, BUS_DMASYNC_POSTREAD);
2344 } else {
2345 /* XXX */
2346 printf("fwohci_rbuf_update: this shouldn't happend\n");
2347 }
2348
2349 STAILQ_REMOVE_HEAD(&ir->stdma, link);
2350 STAILQ_INSERT_TAIL(&ir->stvalid, chunk, link);
2351 switch (stat & FWOHCIEV_MASK) {
2352 case FWOHCIEV_ACKCOMPL:
2353 chunk->resp = 0;
2354 break;
2355 default:
2356 chunk->resp = EINVAL;
2357 device_printf(fc->dev,
2358 "Isochronous receive err %02x(%s)\n",
2359 stat, fwohcicode[stat & 0x1f]);
2360 }
2361 w++;
2362 }
2363 splx(s);
2364 if (w) {
2365 if (ir->flag & FWXFERQ_HANDLER)
2366 ir->hand(ir);
2367 else
2368 wakeup(ir);
2369 }
2370 }
2371
2372 void
2373 dump_dma(struct fwohci_softc *sc, uint32_t ch)
2374 {
2375 uint32_t off, cntl, stat, cmd, match;
2376
2377 if(ch == 0){
2378 off = OHCI_ATQOFF;
2379 }else if(ch == 1){
2380 off = OHCI_ATSOFF;
2381 }else if(ch == 2){
2382 off = OHCI_ARQOFF;
2383 }else if(ch == 3){
2384 off = OHCI_ARSOFF;
2385 }else if(ch < IRX_CH){
2386 off = OHCI_ITCTL(ch - ITX_CH);
2387 }else{
2388 off = OHCI_IRCTL(ch - IRX_CH);
2389 }
2390 cntl = stat = OREAD(sc, off);
2391 cmd = OREAD(sc, off + 0xc);
2392 match = OREAD(sc, off + 0x10);
2393
2394 device_printf(sc->fc.dev, "ch %1x cntl:0x%08x cmd:0x%08x match:0x%08x\n",
2395 ch,
2396 cntl,
2397 cmd,
2398 match);
2399 stat &= 0xffff ;
2400 if (stat) {
2401 device_printf(sc->fc.dev, "dma %d ch:%s%s%s%s%s%s %s(%x)\n",
2402 ch,
2403 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2404 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2405 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2406 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2407 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2408 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2409 fwohcicode[stat & 0x1f],
2410 stat & 0x1f
2411 );
2412 }else{
2413 device_printf(sc->fc.dev, "dma %d ch: Nostat\n", ch);
2414 }
2415 }
2416
2417 void
2418 dump_db(struct fwohci_softc *sc, uint32_t ch)
2419 {
2420 struct fwohci_dbch *dbch;
2421 struct fwohcidb_tr *cp = NULL, *pp, *np = NULL;
2422 struct fwohcidb *curr = NULL, *prev, *next = NULL;
2423 int idb, jdb;
2424 uint32_t cmd, off;
2425 if(ch == 0){
2426 off = OHCI_ATQOFF;
2427 dbch = &sc->atrq;
2428 }else if(ch == 1){
2429 off = OHCI_ATSOFF;
2430 dbch = &sc->atrs;
2431 }else if(ch == 2){
2432 off = OHCI_ARQOFF;
2433 dbch = &sc->arrq;
2434 }else if(ch == 3){
2435 off = OHCI_ARSOFF;
2436 dbch = &sc->arrs;
2437 }else if(ch < IRX_CH){
2438 off = OHCI_ITCTL(ch - ITX_CH);
2439 dbch = &sc->it[ch - ITX_CH];
2440 }else {
2441 off = OHCI_IRCTL(ch - IRX_CH);
2442 dbch = &sc->ir[ch - IRX_CH];
2443 }
2444 cmd = OREAD(sc, off + 0xc);
2445
2446 if( dbch->ndb == 0 ){
2447 device_printf(sc->fc.dev, "No DB is attached ch=%d\n", ch);
2448 return;
2449 }
2450 pp = dbch->top;
2451 prev = pp->db;
2452 for(idb = 0 ; idb < dbch->ndb ; idb ++ ){
2453 cp = STAILQ_NEXT(pp, link);
2454 if(cp == NULL){
2455 curr = NULL;
2456 goto outdb;
2457 }
2458 np = STAILQ_NEXT(cp, link);
2459 for(jdb = 0 ; jdb < dbch->ndesc ; jdb ++ ){
2460 if ((cmd & 0xfffffff0) == cp->bus_addr) {
2461 curr = cp->db;
2462 if(np != NULL){
2463 next = np->db;
2464 }else{
2465 next = NULL;
2466 }
2467 goto outdb;
2468 }
2469 }
2470 pp = STAILQ_NEXT(pp, link);
2471 if(pp == NULL){
2472 curr = NULL;
2473 goto outdb;
2474 }
2475 prev = pp->db;
2476 }
2477 outdb:
2478 if( curr != NULL){
2479 #if 0
2480 printf("Prev DB %d\n", ch);
2481 print_db(pp, prev, ch, dbch->ndesc);
2482 #endif
2483 printf("Current DB %d\n", ch);
2484 print_db(cp, curr, ch, dbch->ndesc);
2485 #if 0
2486 printf("Next DB %d\n", ch);
2487 print_db(np, next, ch, dbch->ndesc);
2488 #endif
2489 }else{
2490 printf("dbdump err ch = %d cmd = 0x%08x\n", ch, cmd);
2491 }
2492 return;
2493 }
2494
2495 void
2496 print_db(struct fwohcidb_tr *db_tr, struct fwohcidb *db,
2497 uint32_t ch, uint32_t hogemax)
2498 {
2499 fwohcireg_t stat;
2500 int i, key;
2501 uint32_t cmd, res;
2502
2503 if(db == NULL){
2504 printf("No Descriptor is found\n");
2505 return;
2506 }
2507
2508 printf("ch = %d\n%8s %s %s %s %s %4s %8s %8s %4s:%4s\n",
2509 ch,
2510 "Current",
2511 "OP ",
2512 "KEY",
2513 "INT",
2514 "BR ",
2515 "len",
2516 "Addr",
2517 "Depend",
2518 "Stat",
2519 "Cnt");
2520 for( i = 0 ; i <= hogemax ; i ++){
2521 cmd = FWOHCI_DMA_READ(db[i].db.desc.cmd);
2522 res = FWOHCI_DMA_READ(db[i].db.desc.res);
2523 key = cmd & OHCI_KEY_MASK;
2524 stat = res >> OHCI_STATUS_SHIFT;
2525 #if defined(__DragonFly__) || \
2526 (defined(__FreeBSD__) && __FreeBSD_version < 500000)
2527 printf("%08x %s %s %s %s %5d %08x %08x %04x:%04x",
2528 db_tr->bus_addr,
2529 #else
2530 printf("%08jx %s %s %s %s %5d %08x %08x %04x:%04x",
2531 (uintmax_t)db_tr->bus_addr,
2532 #endif
2533 dbcode[(cmd >> 28) & 0xf],
2534 dbkey[(cmd >> 24) & 0x7],
2535 dbcond[(cmd >> 20) & 0x3],
2536 dbcond[(cmd >> 18) & 0x3],
2537 cmd & OHCI_COUNT_MASK,
2538 FWOHCI_DMA_READ(db[i].db.desc.addr),
2539 FWOHCI_DMA_READ(db[i].db.desc.depend),
2540 stat,
2541 res & OHCI_COUNT_MASK);
2542 if(stat & 0xff00){
2543 printf(" %s%s%s%s%s%s %s(%x)\n",
2544 stat & OHCI_CNTL_DMA_RUN ? "RUN," : "",
2545 stat & OHCI_CNTL_DMA_WAKE ? "WAKE," : "",
2546 stat & OHCI_CNTL_DMA_DEAD ? "DEAD," : "",
2547 stat & OHCI_CNTL_DMA_ACTIVE ? "ACTIVE," : "",
2548 stat & OHCI_CNTL_DMA_BT ? "BRANCH," : "",
2549 stat & OHCI_CNTL_DMA_BAD ? "BADDMA," : "",
2550 fwohcicode[stat & 0x1f],
2551 stat & 0x1f
2552 );
2553 }else{
2554 printf(" Nostat\n");
2555 }
2556 if(key == OHCI_KEY_ST2 ){
2557 printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
2558 FWOHCI_DMA_READ(db[i+1].db.immed[0]),
2559 FWOHCI_DMA_READ(db[i+1].db.immed[1]),
2560 FWOHCI_DMA_READ(db[i+1].db.immed[2]),
2561 FWOHCI_DMA_READ(db[i+1].db.immed[3]));
2562 }
2563 if(key == OHCI_KEY_DEVICE){
2564 return;
2565 }
2566 if((cmd & OHCI_BRANCH_MASK)
2567 == OHCI_BRANCH_ALWAYS){
2568 return;
2569 }
2570 if((cmd & OHCI_CMD_MASK)
2571 == OHCI_OUTPUT_LAST){
2572 return;
2573 }
2574 if((cmd & OHCI_CMD_MASK)
2575 == OHCI_INPUT_LAST){
2576 return;
2577 }
2578 if(key == OHCI_KEY_ST2 ){
2579 i++;
2580 }
2581 }
2582 return;
2583 }
2584
2585 void
2586 fwohci_ibr(struct firewire_comm *fc)
2587 {
2588 struct fwohci_softc *sc;
2589 uint32_t fun;
2590
2591 device_printf(fc->dev, "Initiate bus reset\n");
2592 sc = (struct fwohci_softc *)fc;
2593
2594 /*
2595 * Make sure our cached values from the config rom are
2596 * initialised.
2597 */
2598 OWRITE(sc, OHCI_CROMHDR, ntohl(sc->fc.config_rom[0]));
2599 OWRITE(sc, OHCI_BUS_OPT, ntohl(sc->fc.config_rom[2]));
2600
2601 /*
2602 * Set root hold-off bit so that non cyclemaster capable node
2603 * shouldn't became the root node.
2604 */
2605 #if 1
2606 fun = fwphy_rddata(sc, FW_PHY_IBR_REG);
2607 fun |= FW_PHY_IBR | FW_PHY_RHB;
2608 fun = fwphy_wrdata(sc, FW_PHY_IBR_REG, fun);
2609 #else /* Short bus reset */
2610 fun = fwphy_rddata(sc, FW_PHY_ISBR_REG);
2611 fun |= FW_PHY_ISBR | FW_PHY_RHB;
2612 fun = fwphy_wrdata(sc, FW_PHY_ISBR_REG, fun);
2613 #endif
2614 }
2615
2616 void
2617 fwohci_txbufdb(struct fwohci_softc *sc, int dmach, struct fw_bulkxfer *bulkxfer)
2618 {
2619 struct fwohcidb_tr *db_tr, *fdb_tr;
2620 struct fwohci_dbch *dbch;
2621 struct fwohcidb *db;
2622 struct fw_pkt *fp;
2623 struct fwohci_txpkthdr *ohcifp;
2624 unsigned short chtag;
2625 int idb;
2626
2627 dbch = &sc->it[dmach];
2628 chtag = sc->it[dmach].xferq.flag & 0xff;
2629
2630 db_tr = (struct fwohcidb_tr *)(bulkxfer->start);
2631 fdb_tr = (struct fwohcidb_tr *)(bulkxfer->end);
2632 /*
2633 device_printf(sc->fc.dev, "DB %08x %08x %08x\n", bulkxfer, db_tr->bus_addr, fdb_tr->bus_addr);
2634 */
2635 for (idb = 0; idb < dbch->xferq.bnpacket; idb ++) {
2636 db = db_tr->db;
2637 fp = (struct fw_pkt *)db_tr->buf;
2638 ohcifp = (struct fwohci_txpkthdr *) db[1].db.immed;
2639 ohcifp->mode.ld[0] = fp->mode.ld[0];
2640 ohcifp->mode.common.spd = 0 & 0x7;
2641 ohcifp->mode.stream.len = fp->mode.stream.len;
2642 ohcifp->mode.stream.chtag = chtag;
2643 ohcifp->mode.stream.tcode = 0xa;
2644 #if BYTE_ORDER == BIG_ENDIAN
2645 FWOHCI_DMA_WRITE(db[1].db.immed[0], db[1].db.immed[0]);
2646 FWOHCI_DMA_WRITE(db[1].db.immed[1], db[1].db.immed[1]);
2647 #endif
2648
2649 FWOHCI_DMA_CLEAR(db[2].db.desc.cmd, OHCI_COUNT_MASK);
2650 FWOHCI_DMA_SET(db[2].db.desc.cmd, fp->mode.stream.len);
2651 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2652 #if 0 /* if bulkxfer->npackets changes */
2653 db[2].db.desc.cmd = OHCI_OUTPUT_LAST
2654 | OHCI_UPDATE
2655 | OHCI_BRANCH_ALWAYS;
2656 db[0].db.desc.depend =
2657 = db[dbch->ndesc - 1].db.desc.depend
2658 = STAILQ_NEXT(db_tr, link)->bus_addr | dbch->ndesc;
2659 #else
2660 FWOHCI_DMA_SET(db[0].db.desc.depend, dbch->ndesc);
2661 FWOHCI_DMA_SET(db[dbch->ndesc - 1].db.desc.depend, dbch->ndesc);
2662 #endif
2663 bulkxfer->end = (caddr_t)db_tr;
2664 db_tr = STAILQ_NEXT(db_tr, link);
2665 }
2666 db = ((struct fwohcidb_tr *)bulkxfer->end)->db;
2667 FWOHCI_DMA_CLEAR(db[0].db.desc.depend, 0xf);
2668 FWOHCI_DMA_CLEAR(db[dbch->ndesc - 1].db.desc.depend, 0xf);
2669 #if 0 /* if bulkxfer->npackets changes */
2670 db[dbch->ndesc - 1].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2671 /* OHCI 1.1 and above */
2672 db[0].db.desc.control |= OHCI_INTERRUPT_ALWAYS;
2673 #endif
2674 /*
2675 db_tr = (struct fwohcidb_tr *)bulkxfer->start;
2676 fdb_tr = (struct fwohcidb_tr *)bulkxfer->end;
2677 device_printf(sc->fc.dev, "DB %08x %3d %08x %08x\n", bulkxfer, bulkxfer->npacket, db_tr->bus_addr, fdb_tr->bus_addr);
2678 */
2679 return;
2680 }
2681
2682 static int
2683 fwohci_add_tx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2684 int poffset)
2685 {
2686 struct fwohcidb *db = db_tr->db;
2687 struct fw_xferq *it;
2688 int err = 0;
2689
2690 it = &dbch->xferq;
2691 if(it->buf == 0){
2692 err = EINVAL;
2693 return err;
2694 }
2695 db_tr->buf = fwdma_v_addr(it->buf, poffset);
2696 db_tr->dbcnt = 3;
2697
2698 FWOHCI_DMA_WRITE(db[0].db.desc.cmd,
2699 OHCI_OUTPUT_MORE | OHCI_KEY_ST2 | 8);
2700 FWOHCI_DMA_WRITE(db[0].db.desc.addr, 0);
2701 bzero((void *)&db[1].db.immed[0], sizeof(db[1].db.immed));
2702 FWOHCI_DMA_WRITE(db[2].db.desc.addr,
2703 fwdma_bus_addr(it->buf, poffset) + sizeof(uint32_t));
2704
2705 FWOHCI_DMA_WRITE(db[2].db.desc.cmd,
2706 OHCI_OUTPUT_LAST | OHCI_UPDATE | OHCI_BRANCH_ALWAYS);
2707 #if 1
2708 FWOHCI_DMA_WRITE(db[0].db.desc.res, 0);
2709 FWOHCI_DMA_WRITE(db[2].db.desc.res, 0);
2710 #endif
2711 return 0;
2712 }
2713
2714 int
2715 fwohci_add_rx_buf(struct fwohci_dbch *dbch, struct fwohcidb_tr *db_tr,
2716 int poffset, struct fwdma_alloc *dummy_dma)
2717 {
2718 struct fwohcidb *db = db_tr->db;
2719 struct fw_xferq *ir;
2720 int i, ldesc;
2721 bus_addr_t dbuf[2];
2722 int dsiz[2];
2723
2724 ir = &dbch->xferq;
2725 if (ir->buf == NULL && (dbch->xferq.flag & FWXFERQ_EXTBUF) == 0) {
2726 if (db_tr->buf == NULL)
2727 db_tr->buf = fwdma_malloc_size(
2728 dbch->dmat, &db_tr->dma_map,
2729 ir->psize, &dbuf[0], BUS_DMA_NOWAIT);
2730 if (db_tr->buf == NULL)
2731 return(ENOMEM);
2732 db_tr->dbcnt = 1;
2733 dsiz[0] = ir->psize;
2734 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2735 BUS_DMASYNC_PREREAD);
2736 } else {
2737 db_tr->dbcnt = 0;
2738 if (dummy_dma != NULL) {
2739 dsiz[db_tr->dbcnt] = sizeof(uint32_t);
2740 dbuf[db_tr->dbcnt++] = dummy_dma->bus_addr;
2741 }
2742 dsiz[db_tr->dbcnt] = ir->psize;
2743 if (ir->buf != NULL) {
2744 db_tr->buf = fwdma_v_addr(ir->buf, poffset);
2745 dbuf[db_tr->dbcnt] = fwdma_bus_addr( ir->buf, poffset);
2746 }
2747 db_tr->dbcnt++;
2748 }
2749 for(i = 0 ; i < db_tr->dbcnt ; i++){
2750 FWOHCI_DMA_WRITE(db[i].db.desc.addr, dbuf[i]);
2751 FWOHCI_DMA_WRITE(db[i].db.desc.cmd, OHCI_INPUT_MORE | dsiz[i]);
2752 if (ir->flag & FWXFERQ_STREAM) {
2753 FWOHCI_DMA_SET(db[i].db.desc.cmd, OHCI_UPDATE);
2754 }
2755 FWOHCI_DMA_WRITE(db[i].db.desc.res, dsiz[i]);
2756 }
2757 ldesc = db_tr->dbcnt - 1;
2758 if (ir->flag & FWXFERQ_STREAM) {
2759 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_INPUT_LAST);
2760 }
2761 FWOHCI_DMA_SET(db[ldesc].db.desc.cmd, OHCI_BRANCH_ALWAYS);
2762 return 0;
2763 }
2764
2765
2766 static int
2767 fwohci_arcv_swap(struct fw_pkt *fp, int len)
2768 {
2769 struct fw_pkt *fp0;
2770 uint32_t ld0;
2771 int slen, hlen;
2772 #if BYTE_ORDER == BIG_ENDIAN
2773 int i;
2774 #endif
2775
2776 ld0 = FWOHCI_DMA_READ(fp->mode.ld[0]);
2777 #if 0
2778 printf("ld0: x%08x\n", ld0);
2779 #endif
2780 fp0 = (struct fw_pkt *)&ld0;
2781 /* determine length to swap */
2782 switch (fp0->mode.common.tcode) {
2783 case FWTCODE_WRES:
2784 CTR0(KTR_DEV, "WRES");
2785 case FWTCODE_RREQQ:
2786 case FWTCODE_WREQQ:
2787 case FWTCODE_RRESQ:
2788 case FWOHCITCODE_PHY:
2789 slen = 12;
2790 break;
2791 case FWTCODE_RREQB:
2792 case FWTCODE_WREQB:
2793 case FWTCODE_LREQ:
2794 case FWTCODE_RRESB:
2795 case FWTCODE_LRES:
2796 slen = 16;
2797 break;
2798 default:
2799 printf("Unknown tcode %d\n", fp0->mode.common.tcode);
2800 return(0);
2801 }
2802 hlen = tinfo[fp0->mode.common.tcode].hdr_len;
2803 if (hlen > len) {
2804 if (firewire_debug)
2805 printf("splitted header\n");
2806 return(-hlen);
2807 }
2808 #if BYTE_ORDER == BIG_ENDIAN
2809 for(i = 0; i < slen/4; i ++)
2810 fp->mode.ld[i] = FWOHCI_DMA_READ(fp->mode.ld[i]);
2811 #endif
2812 return(hlen);
2813 }
2814
2815 static int
2816 fwohci_get_plen(struct fwohci_softc *sc, struct fwohci_dbch *dbch, struct fw_pkt *fp)
2817 {
2818 const struct tcode_info *info;
2819 int r;
2820
2821 info = &tinfo[fp->mode.common.tcode];
2822 r = info->hdr_len + sizeof(uint32_t);
2823 if ((info->flag & FWTI_BLOCK_ASY) != 0)
2824 r += roundup2(fp->mode.wreqb.len, sizeof(uint32_t));
2825
2826 if (r == sizeof(uint32_t)) {
2827 /* XXX */
2828 device_printf(sc->fc.dev, "Unknown tcode %d\n",
2829 fp->mode.common.tcode);
2830 return (-1);
2831 }
2832
2833 if (r > dbch->xferq.psize) {
2834 device_printf(sc->fc.dev, "Invalid packet length %d\n", r);
2835 return (-1);
2836 /* panic ? */
2837 }
2838
2839 return r;
2840 }
2841
2842 static void
2843 fwohci_arcv_free_buf(struct fwohci_softc *sc, struct fwohci_dbch *dbch,
2844 struct fwohcidb_tr *db_tr, uint32_t off, int wake)
2845 {
2846 struct fwohcidb *db = &db_tr->db[0];
2847
2848 FWOHCI_DMA_CLEAR(db->db.desc.depend, 0xf);
2849 FWOHCI_DMA_WRITE(db->db.desc.res, dbch->xferq.psize);
2850 FWOHCI_DMA_SET(dbch->bottom->db[0].db.desc.depend, 1);
2851 fwdma_sync_multiseg_all(dbch->am,
2852 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2853 dbch->bottom = db_tr;
2854
2855 if (wake)
2856 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
2857 }
2858
2859 static void
2860 fwohci_arcv(struct fwohci_softc *sc, struct fwohci_dbch *dbch, int count)
2861 {
2862 struct fwohcidb_tr *db_tr;
2863 struct iovec vec[2];
2864 struct fw_pkt pktbuf;
2865 int nvec;
2866 struct fw_pkt *fp;
2867 uint8_t *ld;
2868 uint32_t stat, off, status, event;
2869 u_int spd;
2870 int len, plen, hlen, pcnt, offset;
2871 int s;
2872 caddr_t buf;
2873 int resCount;
2874
2875 CTR0(KTR_DEV, "fwohci_arv");
2876
2877 if(&sc->arrq == dbch){
2878 off = OHCI_ARQOFF;
2879 }else if(&sc->arrs == dbch){
2880 off = OHCI_ARSOFF;
2881 }else{
2882 return;
2883 }
2884
2885 s = splfw();
2886 db_tr = dbch->top;
2887 pcnt = 0;
2888 /* XXX we cannot handle a packet which lies in more than two buf */
2889 fwdma_sync_multiseg_all(dbch->am,
2890 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2891 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) >> OHCI_STATUS_SHIFT;
2892 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res) & OHCI_COUNT_MASK;
2893 while (status & OHCI_CNTL_DMA_ACTIVE) {
2894 #if 0
2895
2896 if (off == OHCI_ARQOFF)
2897 printf("buf 0x%08x, status 0x%04x, resCount 0x%04x\n",
2898 db_tr->bus_addr, status, resCount);
2899 #endif
2900 len = dbch->xferq.psize - resCount;
2901 ld = (uint8_t *)db_tr->buf;
2902 if (dbch->pdb_tr == NULL) {
2903 len -= dbch->buf_offset;
2904 ld += dbch->buf_offset;
2905 }
2906 if (len > 0)
2907 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map,
2908 BUS_DMASYNC_POSTREAD);
2909 while (len > 0 ) {
2910 if (count >= 0 && count-- == 0)
2911 goto out;
2912 if(dbch->pdb_tr != NULL){
2913 /* we have a fragment in previous buffer */
2914 int rlen;
2915
2916 offset = dbch->buf_offset;
2917 if (offset < 0)
2918 offset = - offset;
2919 buf = dbch->pdb_tr->buf + offset;
2920 rlen = dbch->xferq.psize - offset;
2921 if (firewire_debug)
2922 printf("rlen=%d, offset=%d\n",
2923 rlen, dbch->buf_offset);
2924 if (dbch->buf_offset < 0) {
2925 /* splitted in header, pull up */
2926 char *p;
2927
2928 p = (char *)&pktbuf;
2929 bcopy(buf, p, rlen);
2930 p += rlen;
2931 /* this must be too long but harmless */
2932 rlen = sizeof(pktbuf) - rlen;
2933 if (rlen < 0)
2934 printf("why rlen < 0\n");
2935 bcopy(db_tr->buf, p, rlen);
2936 ld += rlen;
2937 len -= rlen;
2938 hlen = fwohci_arcv_swap(&pktbuf, sizeof(pktbuf));
2939 if (hlen <= 0) {
2940 printf("hlen < 0 shouldn't happen");
2941 goto err;
2942 }
2943 offset = sizeof(pktbuf);
2944 vec[0].iov_base = (char *)&pktbuf;
2945 vec[0].iov_len = offset;
2946 } else {
2947 /* splitted in payload */
2948 offset = rlen;
2949 vec[0].iov_base = buf;
2950 vec[0].iov_len = rlen;
2951 }
2952 fp=(struct fw_pkt *)vec[0].iov_base;
2953 nvec = 1;
2954 } else {
2955 /* no fragment in previous buffer */
2956 fp=(struct fw_pkt *)ld;
2957 hlen = fwohci_arcv_swap(fp, len);
2958 if (hlen == 0)
2959 goto err;
2960 if (hlen < 0) {
2961 dbch->pdb_tr = db_tr;
2962 dbch->buf_offset = - dbch->buf_offset;
2963 /* sanity check */
2964 if (resCount != 0) {
2965 printf("resCount=%d hlen=%d\n",
2966 resCount, hlen);
2967 goto err;
2968 }
2969 goto out;
2970 }
2971 offset = 0;
2972 nvec = 0;
2973 }
2974 plen = fwohci_get_plen(sc, dbch, fp) - offset;
2975 if (plen < 0) {
2976 /* minimum header size + trailer
2977 = sizeof(fw_pkt) so this shouldn't happens */
2978 printf("plen(%d) is negative! offset=%d\n",
2979 plen, offset);
2980 goto err;
2981 }
2982 if (plen > 0) {
2983 len -= plen;
2984 if (len < 0) {
2985 dbch->pdb_tr = db_tr;
2986 if (firewire_debug)
2987 printf("splitted payload\n");
2988 /* sanity check */
2989 if (resCount != 0) {
2990 printf("resCount=%d plen=%d"
2991 " len=%d\n",
2992 resCount, plen, len);
2993 goto err;
2994 }
2995 goto out;
2996 }
2997 vec[nvec].iov_base = ld;
2998 vec[nvec].iov_len = plen;
2999 nvec ++;
3000 ld += plen;
3001 }
3002 dbch->buf_offset = ld - (uint8_t *)db_tr->buf;
3003 if (nvec == 0)
3004 printf("nvec == 0\n");
3005
3006 /* DMA result-code will be written at the tail of packet */
3007 stat = FWOHCI_DMA_READ(*(uint32_t *)(ld - sizeof(struct fwohci_trailer)));
3008 #if 0
3009 printf("plen: %d, stat %x\n",
3010 plen ,stat);
3011 #endif
3012 spd = (stat >> 21) & 0x3;
3013 event = (stat >> 16) & 0x1f;
3014 switch (event) {
3015 case FWOHCIEV_ACKPEND:
3016 #if 0
3017 printf("fwohci_arcv: ack pending tcode=0x%x..\n", fp->mode.common.tcode);
3018 #endif
3019 /* fall through */
3020 case FWOHCIEV_ACKCOMPL:
3021 {
3022 struct fw_rcv_buf rb;
3023
3024 if ((vec[nvec-1].iov_len -=
3025 sizeof(struct fwohci_trailer)) == 0)
3026 nvec--;
3027 rb.fc = &sc->fc;
3028 rb.vec = vec;
3029 rb.nvec = nvec;
3030 rb.spd = spd;
3031 fw_rcv(&rb);
3032 break;
3033 }
3034 case FWOHCIEV_BUSRST:
3035 if (sc->fc.status != FWBUSRESET)
3036 printf("got BUSRST packet!?\n");
3037 break;
3038 default:
3039 device_printf(sc->fc.dev,
3040 "Async DMA Receive error err=%02x %s"
3041 " plen=%d offset=%d len=%d status=0x%08x"
3042 " tcode=0x%x, stat=0x%08x\n",
3043 event, fwohcicode[event], plen,
3044 dbch->buf_offset, len,
3045 OREAD(sc, OHCI_DMACTL(off)),
3046 fp->mode.common.tcode, stat);
3047 #if 1 /* XXX */
3048 goto err;
3049 #endif
3050 break;
3051 }
3052 pcnt ++;
3053 if (dbch->pdb_tr != NULL) {
3054 fwohci_arcv_free_buf(sc, dbch, dbch->pdb_tr,
3055 off, 1);
3056 dbch->pdb_tr = NULL;
3057 }
3058
3059 }
3060 out:
3061 if (resCount == 0) {
3062 /* done on this buffer */
3063 if (dbch->pdb_tr == NULL) {
3064 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 1);
3065 dbch->buf_offset = 0;
3066 } else
3067 if (dbch->pdb_tr != db_tr)
3068 printf("pdb_tr != db_tr\n");
3069 db_tr = STAILQ_NEXT(db_tr, link);
3070 fwdma_sync_multiseg_all(dbch->am,
3071 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3072 status = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
3073 >> OHCI_STATUS_SHIFT;
3074 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
3075 & OHCI_COUNT_MASK;
3076 /* XXX check buffer overrun */
3077 dbch->top = db_tr;
3078 } else {
3079 dbch->buf_offset = dbch->xferq.psize - resCount;
3080 fw_bus_dmamap_sync(
3081 dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD);
3082 break;
3083 }
3084 /* XXX make sure DMA is not dead */
3085 }
3086 #if 0
3087 if (pcnt < 1)
3088 printf("fwohci_arcv: no packets\n");
3089 #endif
3090 fwdma_sync_multiseg_all(dbch->am,
3091 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3092 splx(s);
3093 return;
3094
3095 err:
3096 device_printf(sc->fc.dev, "AR DMA status=%x, ",
3097 OREAD(sc, OHCI_DMACTL(off)));
3098 dbch->pdb_tr = NULL;
3099 /* skip until resCount != 0 */
3100 printf(" skip buffer");
3101 while (resCount == 0) {
3102 printf(" #");
3103 fwohci_arcv_free_buf(sc, dbch, db_tr, off, 0);
3104 db_tr = STAILQ_NEXT(db_tr, link);
3105 resCount = FWOHCI_DMA_READ(db_tr->db[0].db.desc.res)
3106 & OHCI_COUNT_MASK;
3107 }
3108 printf(" done\n");
3109 dbch->top = db_tr;
3110 dbch->buf_offset = dbch->xferq.psize - resCount;
3111 OWRITE(sc, OHCI_DMACTL(off), OHCI_CNTL_DMA_WAKE);
3112 fwdma_sync_multiseg_all(
3113 dbch->am, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
3114 fw_bus_dmamap_sync(dbch->dmat, db_tr->dma_map, BUS_DMASYNC_PREREAD);
3115 splx(s);
3116 }
3117 #if defined(__NetBSD__)
3118
3119 int
3120 fwohci_print(void *aux, const char *pnp)
3121 {
3122 struct fw_attach_args *fwa = (struct fw_attach_args *)aux;
3123
3124 if (pnp)
3125 aprint_normal("%s at %s", fwa->name, pnp);
3126
3127 return UNCONF;
3128 }
3129 #endif
Cache object: d8b593506d1c7045a796f62849c88d6b
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