The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/dev/ieee1394/fwohcireg.h

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    1 /*      $NetBSD: fwohcireg.h,v 1.13 2003/10/22 09:02:49 mjl Exp $       */
    2 
    3 /*-
    4  * Copyright (c) 2000 The NetBSD Foundation, Inc.
    5  * All rights reserved.
    6  *
    7  * This code is derived from software contributed to The NetBSD Foundation
    8  * by Matt Thomas of 3am Software Foundry.
    9  *
   10  * Redistribution and use in source and binary forms, with or without
   11  * modification, are permitted provided that the following conditions
   12  * are met:
   13  * 1. Redistributions of source code must retain the above copyright
   14  *    notice, this list of conditions and the following disclaimer.
   15  * 2. Redistributions in binary form must reproduce the above copyright
   16  *    notice, this list of conditions and the following disclaimer in the
   17  *    documentation and/or other materials provided with the distribution.
   18  * 3. All advertising materials mentioning features or use of this software
   19  *    must display the following acknowledgement:
   20  *        This product includes software developed by the NetBSD
   21  *        Foundation, Inc. and its contributors.
   22  * 4. Neither the name of The NetBSD Foundation nor the names of its
   23  *    contributors may be used to endorse or promote products derived
   24  *    from this software without specific prior written permission.
   25  *
   26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   36  * POSSIBILITY OF SUCH DAMAGE.
   37  */
   38 
   39 #ifndef _DEV_IEEE1394_FWOHCIREG_H_
   40 #define _DEV_IEEE1394_FWOHCIREG_H_
   41 
   42 /* PCI/CardBus-Specific definitions
   43  */
   44 
   45 /* In the PCI Class Code Register ...
   46  */
   47 #define PCI_INTERFACE_OHCI              0x10
   48 
   49 /* The OHCI Registers are in PCI BAR0.
   50  */
   51 #define PCI_OHCI_MAP_REGISTER           0x10
   52 
   53 /* HCI Control Register (in PCI config space)
   54  */
   55 #define PCI_OHCI_CONTROL_REGISTER       0x40
   56 
   57 /* If the following bit, all OHCI register access
   58  * and DMA transactions are byte swapped.
   59  */
   60 #define PCI_GLOBAL_SWAP_BE              0x00000001
   61 
   62 /* Bus Independent Definitions */
   63 
   64 #define OHCI_CONFIG_SIZE                1024
   65 #define OHCI_CONFIG_ALIGNMENT           1024
   66 
   67 /* OHCI Registers
   68  * OHCI Registers are divided into four spaces:
   69  *   1) 0x000 .. 0x17C = Control register space
   70  *   2) 0x180 .. 0x1FC = Asynchronous DMA context register space
   71  *                       (4 contexts)
   72  *   3) 0x200 .. 0x3FC = Isochronous Transmit DMA context register space
   73  *                       (32 contexts)
   74  *   4) 0x400 .. 0x7FC = Isochronous Receive DMA context register space
   75  *                       (32 contexts)
   76  */
   77 #define OHCI_REG_Version                        0x000
   78 #define OHCI_REG_Guid_Rom                       0x004
   79 #define OHCI_REG_ATRetries                      0x008
   80 #define OHCI_REG_CsrReadData                    0x00c
   81 #define OHCI_REG_CsrCompareData                 0x010
   82 #define OHCI_REG_CsrControl                     0x014
   83 #define OHCI_REG_ConfigROMhdr                   0x018
   84 #define OHCI_REG_BusId                          0x01c
   85 #define OHCI_REG_BusOptions                     0x020
   86 #define OHCI_REG_GUIDHi                         0x024
   87 #define OHCI_REG_GUIDLo                         0x028
   88 #define OHCI_REG_reserved_02c                   0x02c
   89 #define OHCI_REG_reserved_030                   0x030
   90 #define OHCI_REG_ConfigROMmap                   0x034
   91 #define OHCI_REG_PostedWriteAddressLo           0x038
   92 #define OHCI_REG_PostedWriteAddressHi           0x03c
   93 #define OHCI_REG_VendorId                       0x040
   94 #define OHCI_REG_reserved_044                   0x044
   95 #define OHCI_REG_reserved_048                   0x048
   96 #define OHCI_REG_reserved_04c                   0x04c
   97 #define OHCI_REG_HCControlSet                   0x050
   98 #define OHCI_REG_HCControlClear                 0x054
   99 #define OHCI_REG_reserved_058                   0x058
  100 #define OHCI_REG_reserved_05c                   0x05c
  101 #define OHCI_REG_reserved_060                   0x060
  102 #define OHCI_REG_SelfIDBuffer                   0x064
  103 #define OHCI_REG_SelfIDCount                    0x068
  104 #define OHCI_REG_reserved_06c                   0x06c
  105 #define OHCI_REG_IRMultiChanMaskHiSet           0x070
  106 #define OHCI_REG_IRMultiChanMaskHiClear         0x074
  107 #define OHCI_REG_IRMultiChanMaskLoSet           0x078
  108 #define OHCI_REG_IRMultiChanMaskLoClear         0x07c
  109 #define OHCI_REG_IntEventSet                    0x080
  110 #define OHCI_REG_IntEventClear                  0x084
  111 #define OHCI_REG_IntMaskSet                     0x088
  112 #define OHCI_REG_IntMaskClear                   0x08c
  113 #define OHCI_REG_IsoXmitIntEventSet             0x090
  114 #define OHCI_REG_IsoXmitIntEventClear           0x094
  115 #define OHCI_REG_IsoXmitIntMaskSet              0x098
  116 #define OHCI_REG_IsoXmitIntMaskClear            0x09c
  117 #define OHCI_REG_IsoRecvIntEventSet             0x0a0
  118 #define OHCI_REG_IsoRecvIntEventClear           0x0a4
  119 #define OHCI_REG_IsoRecvIntMaskSet              0x0a8
  120 #define OHCI_REG_IsoRecvIntMaskClear            0x0ac
  121 #define OHCI_REG_InitialBandwidthAvailable      0x0b0
  122 #define OHCI_REG_InitialChannelsAvailableHi     0x0b4
  123 #define OHCI_REG_InitialChannelsAvailableLo     0x0b8
  124 #define OHCI_REG_reserved_0bc                   0x0bc
  125 #define OHCI_REG_reserved_0c0                   0x0c0
  126 #define OHCI_REG_reserved_0c4                   0x0c4
  127 #define OHCI_REG_reserved_0c8                   0x0c8
  128 #define OHCI_REG_reserved_0cc                   0x0cc
  129 #define OHCI_REG_reserved_0d0                   0x0d0
  130 #define OHCI_REG_reserved_0d4                   0x0d4
  131 #define OHCI_REG_reserved_0d8                   0x0d8
  132 #define OHCI_REG_FairnessConctrol               0x0dc
  133 #define OHCI_REG_LinkControlSet                 0x0e0
  134 #define OHCI_REG_LinkControlClear               0x0e4
  135 #define OHCI_REG_NodeId                         0x0e8
  136 #define OHCI_REG_PhyControl                     0x0ec
  137 #define OHCI_REG_IsochronousCycleTimer          0x0f0
  138 #define OHCI_REG_reserved_0f0                   0x0f4
  139 #define OHCI_REG_reserved_0f8                   0x0f8
  140 #define OHCI_REG_reserved_0fc                   0x0fc
  141 #define OHCI_REG_AsynchronousRequestFilterHiSet 0x100
  142 #define OHCI_REG_AsynchronousRequestFilterHiClear       0x104
  143 #define OHCI_REG_AsynchronousRequestFilterLoSet 0x108
  144 #define OHCI_REG_AsynchronousRequestFilterLoClear       0x10c
  145 #define OHCI_REG_PhysicalRequestFilterHiSet     0x110
  146 #define OHCI_REG_PhysicalRequestFilterHiClear   0x114
  147 #define OHCI_REG_PhysicalRequestFilterLoSet     0x118
  148 #define OHCI_REG_PhysicalRequestFilterLoClear   0x11c
  149 #define OHCI_REG_PhysicalUpperBound             0x120
  150 #define OHCI_REG_reserved_124                   0x124
  151 #define OHCI_REG_reserved_128                   0x128
  152 #define OHCI_REG_reserved_12c                   0x12c
  153 #define OHCI_REG_reserved_130                   0x130
  154 #define OHCI_REG_reserved_134                   0x134
  155 #define OHCI_REG_reserved_138                   0x138
  156 #define OHCI_REG_reserved_13c                   0x13c
  157 #define OHCI_REG_reserved_140                   0x140
  158 #define OHCI_REG_reserved_144                   0x144
  159 #define OHCI_REG_reserved_148                   0x148
  160 #define OHCI_REG_reserved_14c                   0x14c
  161 #define OHCI_REG_reserved_150                   0x150
  162 #define OHCI_REG_reserved_154                   0x154
  163 #define OHCI_REG_reserved_158                   0x158
  164 #define OHCI_REG_reserved_15c                   0x15c
  165 #define OHCI_REG_reserved_160                   0x160
  166 #define OHCI_REG_reserved_164                   0x164
  167 #define OHCI_REG_reserved_168                   0x168
  168 #define OHCI_REG_reserved_16c                   0x16c
  169 #define OHCI_REG_reserved_170                   0x170
  170 #define OHCI_REG_reserved_174                   0x174
  171 #define OHCI_REG_reserved_178                   0x178
  172 #define OHCI_REG_reserved_17c                   0x17c
  173 
  174 
  175 #define OHCI_REG_ASYNC_DMA_BASE                 0x180
  176 #define OHCI_CTX_ASYNC_TX_REQUEST               0
  177 #define OHCI_CTX_ASYNC_TX_RESPONSE              1
  178 #define OHCI_CTX_ASYNC_RX_REQUEST               2
  179 #define OHCI_CTX_ASYNC_RX_RESPONSE              3
  180 #define OHCI_SUBREG_ContextControlSet           0x000
  181 #define OHCI_SUBREG_ContextControlClear         0x004
  182 #define OHCI_SUBREG_reserved_008                0x008
  183 #define OHCI_SUBREG_CommandPtr                  0x00c
  184 #define OHCI_SUBREG_ContextMatch                0x010
  185 #define OHCI_SUBREG_reserved_014                0x014
  186 #define OHCI_SUBREG_reserved_018                0x018
  187 #define OHCI_SUBREG_reserved_01c                0x01c
  188 #define OHCI_ASYNC_DMA_WRITE(sc, ctx, reg, val) \
  189         OHCI_CSR_WRITE(sc, OHCI_REG_ASYNC_DMA_BASE + 32*(ctx) + (reg), val)
  190 #define OHCI_ASYNC_DMA_READ(sc, ctx, reg) \
  191         OHCI_CSR_READ(sc, OHCI_REG_ASYNC_DMA_BASE + 32*(ctx) + (reg))
  192 
  193 #define OHCI_REG_SYNC_TX_DMA_BASE               0x200
  194 #define OHCI_SYNC_TX_DMA_WRITE(sc, ctx, reg, val) \
  195         OHCI_CSR_WRITE(sc, OHCI_REG_SYNC_TX_DMA_BASE + 16*(ctx) + (reg), val)
  196 #define OHCI_SYNC_TX_DMA_READ(sc, ctx, reg) \
  197         OHCI_CSR_READ(sc, OHCI_REG_SYNC_TX_DMA_BASE + 16*(ctx) + (reg))
  198 
  199 #define OHCI_REG_SYNC_RX_DMA_BASE       0x400
  200 #define OHCI_SYNC_RX_DMA_WRITE(sc, ctx, reg, val) \
  201         OHCI_CSR_WRITE(sc, OHCI_REG_SYNC_RX_DMA_BASE + 32*(ctx) + (reg), val)
  202 #define OHCI_SYNC_RX_DMA_READ(sc, ctx, reg) \
  203         OHCI_CSR_READ(sc, OHCI_REG_SYNC_RX_DMA_BASE + 32*(ctx) + (reg))
  204 
  205 #define OHCI_BITVAL(val, name) \
  206         ((((val) & name##_MASK) >> name##_BITPOS))
  207 
  208 /* OHCI_REG_Version
  209  */
  210 #define OHCI_Version_GUID_ROM           0x01000000
  211 #define OHCI_Version_GET_Version(x) \
  212         ((((x) >> 16) & 0xf) + (((x) >> 20) & 0xf) * 10)
  213 #define OHCI_Version_GET_Revision(x) \
  214         ((((x) >> 4) & 0xf) + ((x) & 0xf) * 10)
  215 
  216 /* OHCI_REG_Guid_Rom
  217  */
  218 #define OHCI_Guid_AddrReset             0x80000000
  219 #define OHCI_Guid_RdStart               0x02000000
  220 #define OHCI_Guid_RdData_MASK           0x00ff0000
  221 #define OHCI_Guid_RdData_BITPOS         16
  222 #define OHCI_Guid_MiniROM_MASK          0x000000ff
  223 #define OHCI_Guid_MiniROM_BITPOS        0
  224 
  225 /* OHCI_REG_GUIDxx
  226  */
  227 
  228 /* OHCI_REG_CsrControl
  229  */
  230 #define OHCI_CsrControl_Done            0x80000000
  231 #define OHCI_CsrControl_SelMASK         0x00000003
  232 #define OHCI_CsrControl_BusManId                0
  233 #define OHCI_CsrControl_BWAvail                 1
  234 #define OHCI_CsrControl_ChanAvailHi             2
  235 #define OHCI_CsrControl_ChanAvailLo             3
  236 
  237 /* OHCI_REG_BusOptions
  238  */
  239 #define OHCI_BusOptions_LinkSpd_MASK    0x00000007
  240 #define OHCI_BusOptions_LinkSpd_BITPOS  0
  241 #define OHCI_BusOptions_G_MASK          0x000000c0
  242 #define OHCI_BusOptions_G_BITPOS        6
  243 #define OHCI_BusOptions_MaxRec_MASK     0x0000f000
  244 #define OHCI_BusOptions_MaxRec_BITPOS   12
  245 #define OHCI_BusOptions_CycClkAcc_MASK  0x00ff0000
  246 #define OHCI_BusOptions_CycClkAcc_BITPOS 16
  247 #define OHCI_BusOptions_PMC             0x08000000
  248 #define OHCI_BusOptions_BMC             0x10000000
  249 #define OHCI_BusOptions_ISC             0x20000000
  250 #define OHCI_BusOptions_CMC             0x40000000
  251 #define OHCI_BusOptions_IRMC            0x80000000
  252 #define OHCI_BusOptions_reserved        0x07000f38
  253 
  254 /* OHCI_REG_HCControl
  255  */
  256 
  257 #define OHCI_HCControl_SoftReset        0x00010000
  258 #define OHCI_HCControl_LinkEnable       0x00020000
  259 #define OHCI_HCControl_PostedWriteEnable 0x00040000
  260 #define OHCI_HCControl_LPS              0x00080000
  261 #define OHCI_HCControl_APhyEnhanceEnable 0x00400000
  262 #define OHCI_HCControl_ProgramPhyEnable 0x00800000
  263 #define OHCI_HCControl_NoByteSwapData   0x40000000
  264 #define OHCI_HCControl_BIBImageValid    0x80000000
  265 
  266 /* OHCI_REG_SelfID
  267  */
  268 #define OHCI_SelfID_Error               0x80000000
  269 #define OHCI_SelfID_Gen_MASK            0x00ff0000
  270 #define OHCI_SelfID_Gen_BITPOS          16
  271 #define OHCI_SelfID_Size_MASK           0x000007fc
  272 #define OHCI_SelfID_Size_BITPOS         2
  273 
  274 /* OHCI_REG_Int{Event|Mask}*
  275  */
  276 #define OHCI_Int_MasterEnable           0x80000000
  277 #define OHCI_Int_VendorSpecific         0x40000000
  278 #define OHCI_Int_SoftInterrupt          0x20000000
  279 #define OHCI_Int_Ack_Tardy              0x08000000
  280 #define OHCI_Int_PhyRegRcvd             0x04000000
  281 #define OHCI_Int_CycleTooLong           0x02000000
  282 #define OHCI_Int_UnrecoverableError     0x01000000
  283 #define OHCI_Int_CycleInconsistent      0x00800000
  284 #define OHCI_Int_CycleLost              0x00400000
  285 #define OHCI_Int_Cycle64Seconds         0x00200000
  286 #define OHCI_Int_CycleSynch             0x00100000
  287 #define OHCI_Int_Phy                    0x00080000
  288 #define OHCI_Int_RegAccessFail          0x00040000
  289 #define OHCI_Int_BusReset               0x00020000
  290 #define OHCI_Int_SelfIDComplete         0x00010000
  291 #define OHCI_Int_SelfIDCOmplete2        0x00008000
  292 #define OHCI_Int_LockRespErr            0x00000200
  293 #define OHCI_Int_PostedWriteErr         0x00000100
  294 #define OHCI_Int_IsochRx                0x00000080
  295 #define OHCI_Int_IsochTx                0x00000040
  296 #define OHCI_Int_RSPkt                  0x00000020
  297 #define OHCI_Int_RQPkt                  0x00000010
  298 #define OHCI_Int_ARRS                   0x00000008
  299 #define OHCI_Int_ARRQ                   0x00000004
  300 #define OHCI_Int_RespTxComplete         0x00000002
  301 #define OHCI_Int_ReqTxComplete          0x00000001
  302 
  303 /* OHCI_REG_LinkControl
  304  */
  305 #define OHCI_LinkControl_CycleSource    0x00400000
  306 #define OHCI_LinkControl_CycleMaster    0x00200000
  307 #define OHCI_LinkControl_CycleTimerEnable 0x00100000
  308 #define OHCI_LinkControl_RcvPhyPkt      0x00000400
  309 #define OHCI_LinkControl_RcvSelfID      0x00000200
  310 #define OHCI_LinkControl_Tag1SyncFilterLock 0x00000040
  311 
  312 /* OHCI_REG_NodeId
  313  */
  314 #define OHCI_NodeId_IDValid             0x80000000
  315 #define OHCI_NodeId_ROOT                0x40000000
  316 #define OHCI_NodeId_CPS                 0x08000000
  317 #define OHCI_NodeId_BusNumber           0x0000ffc0
  318 #define OHCI_NodeId_NodeNumber          0x0000003f
  319 
  320 /* OHCI_REG_PhyControl
  321  */
  322 #define OHCI_PhyControl_RdDone          0x80000000
  323 #define OHCI_PhyControl_RdAddr          0x0f000000
  324 #define OHCI_PhyControl_RdAddr_BITPOS   24
  325 #define OHCI_PhyControl_RdData          0x00ff0000
  326 #define OHCI_PhyControl_RdData_BITPOS   16
  327 #define OHCI_PhyControl_RdReg           0x00008000
  328 #define OHCI_PhyControl_WrReg           0x00004000
  329 #define OHCI_PhyControl_RegAddr         0x00000f00
  330 #define OHCI_PhyControl_RegAddr_BITPOS  8
  331 #define OHCI_PhyControl_WrData          0x000000ff
  332 #define OHCI_PhyControl_WrData_BITPOS   0
  333 
  334 /*
  335  * OHCI_REG_IsochronousCycleTimer
  336  */
  337 #define OHCI_IsoCycleTimer_Sec          0xfe000000
  338 #define OHCI_IsoCycleTimer_Sec_BITPOS   25
  339 #define OHCI_IsoCycleTimer_uSec         0x01fff000
  340 #define OHCI_IsoCycleTimer_uSec_BITPOS  12
  341 #define OHCI_IsoCycleTimer_Mod          0x00000fff
  342 #define OHCI_IsoCycleTimer_Mod_BITPOS   0
  343 
  344 /*
  345  * Section 3.1.1: ContextControl register
  346  *
  347  *
  348  */
  349 #define OHCI_CTXCTL_RUN                 0x00008000
  350 #define OHCI_CTXCTL_WAKE                0x00001000
  351 #define OHCI_CTXCTL_DEAD                0x00000800
  352 #define OHCI_CTXCTL_ACTIVE              0x00000400
  353 
  354 #define OHCI_CTXCTL_SPD_BITLEN          3
  355 #define OHCI_CTXCTL_SPD_BITPOS          5
  356 
  357 #define OHCI_CTXCTL_SPD_100             0
  358 #define OHCI_CTXCTL_SPD_200             1
  359 #define OHCI_CTXCTL_SPD_400             2
  360 
  361 #define OHCI_CTXCTL_EVENT_BITLEN        5
  362 #define OHCI_CTXCTL_EVENT_BITPOS        0
  363 
  364 /* Events from 0 to 15 are generated by the OpenHCI controller.
  365  * Events from 16 to 31 are four-bit IEEE 1394 ack codes or'ed with bit 4 set.
  366  */
  367 #define OHCI_CTXCTL_EVENT_NO_STATUS             0
  368 #define OHCI_CTXCTL_EVENT_RESERVED1             1
  369 
  370 /* The received data length was greater than the buffer's data_length.
  371  */
  372 #define OHCI_CTXCTL_EVENT_LONG_PACKET           2
  373 
  374 /* A subaction gap was detected before an ack arrived or the received
  375  * ack had a parity error.
  376  */
  377 #define OHCI_CTXCTL_EVENT_MISSING_ACK           3
  378 
  379 /* Underrun on the corresponding FIFO. The packet was truncated.
  380  */
  381 #define OHCI_CTXCTL_EVENT_UNDERRUN              4
  382 
  383 /* A receive FIFO overflowed during the reception of an isochronous packet.
  384  */
  385 #define OHCI_CTXCTL_EVENT_OVERRUN               5
  386 
  387 /* An unrecoverable error occurred while the Host Controller was reading
  388  * a descriptor block.
  389  */
  390 #define OHCI_CTXCTL_EVENT_DESCRIPTOR_READ       6
  391 
  392 /* An error occurred while the Host Controller was attempting to read
  393  * from host memory in the data stage of descriptor processing.
  394  */
  395 #define OHCI_CTXCTL_EVENT_DATA_READ             7
  396 
  397 /* An error occurred while the Host Controller was attempting to write
  398  * to host memory either in the data stage of descriptor processing
  399  * (AR, IR), or when processing a single 16-bit host * memory write (IT).
  400  */
  401 #define OHCI_CTXCTL_EVENT_DATA_WRITE            8
  402 
  403 /* Identifies a PHY packet in the receive buffer as being the synthesized
  404  * bus reset packet.  (See section 8.4.2.3).
  405  */
  406 #define OHCI_CTXCTL_EVENT_BUS_RESET             9
  407 
  408 /* Indicates that the asynchronous transmit response packet expired and
  409  * was not transmitted, or that an IT DMA context experienced a skip
  410  * processing overflow (See section 9.3.3).
  411  */
  412 #define OHCI_CTXCTL_EVENT_TIMEOUT               10
  413 
  414 /* A bad tCode is associated with this packet. The packet was flushed.
  415  */
  416 #define OHCI_CTXCTL_EVENT_TCODE_ERR             11
  417 #define OHCI_CTXCTL_EVENT_RESERVED12            12
  418 #define OHCI_CTXCTL_EVENT_RESERVED13            13
  419 
  420 /* An error condition has occurred that cannot be represented
  421  * by any other event codes defined herein.
  422  */
  423 #define OHCI_CTXCTL_EVENT_UNKNOWN               14
  424 
  425 /* Sent by the link side of the output FIFO when asynchronous
  426  * packets are being flushed due to a bus reset.
  427  */
  428 #define OHCI_CTXCTL_EVENT_FLUSHED               15
  429 
  430 /* IEEE1394 derived ACK codes follow
  431  */
  432 #define OHCI_CTXCTL_EVENT_RESERVED16            16
  433 
  434 /* For asynchronous request and response packets, this event
  435  * indicates the destination node has successfully accepted
  436  * the packet. If the packet was a request subaction, the
  437  * destination node has successfully completed the transaction
  438  * and no response subaction shall follow.  The event code for
  439  * transmitted PHY, isochronous, asynchronous stream and broadcast
  440  * packets, none of which yields a 1394 ack code, shall be set
  441  * by hardware to ack_complete unless an event occurs.
  442  */
  443 #define OHCI_CTXCTL_EVENT_ACK_COMPLETE          17
  444 
  445 /* The destination node has successfully accepted the packet.
  446  * If the packet was a request subaction, a response subaction
  447  * should follow at a later time. This code is not returned for
  448  * a response subaction.
  449  */
  450 #define OHCI_CTXCTL_EVENT_ACK_PENDING           18
  451 #define OHCI_CTXCTL_EVENT_RESERVED19            19
  452 
  453 /* The packet could not be accepted after max ATRetries (see
  454  * section 5.4) attempts, and the last ack received was ack_busy_X.
  455  */
  456 #define OHCI_CTXCTL_EVENT_ACK_BUSY_X            20
  457 
  458 /* The packet could not be accepted after max ATRetries (see
  459  * section 5.4) attempts, and the last ack received was ack_busy_A.
  460  */
  461 #define OHCI_CTXCTL_EVENT_ACK_BUSY_A            21
  462 
  463 /* The packet could not be accepted after max AT Retries (see
  464  * section 5.4) attempts, and the last ack received was ack_busy_B.
  465  */
  466 #define OHCI_CTXCTL_EVENT_ACK_BUSY_B            22
  467 #define OHCI_CTXCTL_EVENT_RESERVED23            23
  468 #define OHCI_CTXCTL_EVENT_RESERVED24            24
  469 #define OHCI_CTXCTL_EVENT_RESERVED25            25
  470 #define OHCI_CTXCTL_EVENT_RESERVED26            26
  471 
  472 /* The destination node could not accept the packet because
  473  * the link and higher layers are in a suspended state.
  474  */
  475 #define OHCI_CTXCTL_EVENT_ACK_TARDY             27
  476 #define OHCI_CTXCTL_EVENT_RESERVED28            28
  477 
  478 /* An AT context received an ack_data_error, or an IR context
  479  * in packet-per-buffer mode detected a data field CRC or
  480  * data_length error.
  481  */
  482 #define OHCI_CTXCTL_EVENT_ACK_DATA_ERROR        29
  483 
  484 /* A field in the request packet header was set to an unsupported or
  485  * incorrect value, or an invalid transaction was attempted (e.g., a
  486  * write to a read-only address).
  487  */
  488 #define OHCI_CTXCTL_EVENT_ACK_TYPE_ERROR        30
  489 #define OHCI_CTXCTL_EVENT_RESERVED31            31
  490 
  491 /* Context Control for isochronous transmit context
  492  */
  493 #define OHCI_CTXCTL_TX_CYCLE_MATCH_ENABLE       0x80000000
  494 #define OHCI_CTXCTL_TX_CYCLE_MATCH_BITLEN       0x7fff0000
  495 #define OHCI_CTXCTL_TX_CYCLE_MATCH_BITPOS       16
  496 
  497 #define OHCI_CTXCTL_RX_BUFFER_FILL              0x80000000
  498 #define OHCI_CTXCTL_RX_ISOCH_HEADER             0x40000000
  499 #define OHCI_CTXCTL_RX_CYCLE_MATCH_ENABLE       0x20000000
  500 #define OHCI_CTXCTL_RX_MULTI_CHAN_MODE          0x10000000
  501 #define OHCI_CTXCTL_RX_DUAL_BUFFER_MODE         0x08000000
  502 
  503 /* Context Match registers
  504  */
  505 #define OHCI_CTXMATCH_TAG3                      0x80000000
  506 #define OHCI_CTXMATCH_TAG2                      0x40000000
  507 #define OHCI_CTXMATCH_TAG1                      0x20000000
  508 #define OHCI_CTXMATCH_TAG0                      0x10000000
  509 #define OHCI_CTXMATCH_TAG_MASK                  0xf0000000
  510 #define OHCI_CTXMATCH_TAG_BITPOS                28
  511 #define OHCI_CTXMATCH_CYCLE_MATCH_MASK          0x07fff000
  512 #define OHCI_CTXMATCH_CYCLE_MATCH_BITPOS        12
  513 #define OHCI_CTXMATCH_SYNC_MASK                 0x00000f00
  514 #define OHCI_CTXMATCH_SYNC_BITPOS               8
  515 #define OHCI_CTXMATCH_TAG1_SYNC_FILTER          0x00000040
  516 #define OHCI_CTXMATCH_CHANNEL_NUMBER_MASK       0x0000003f
  517 #define OHCI_CTXMATCH_CHANNEL_NUMBER_BITPOS     0
  518 
  519 /*
  520  * Miscellaneous definitions.
  521  */
  522 
  523 #define OHCI_TCODE_PHY                          0xe
  524 
  525 #if BYTE_ORDER == BIG_ENDIAN
  526 struct fwohci_desc {
  527         u_int16_t       fd_flags;
  528         u_int16_t       fd_reqcount;
  529         u_int32_t       fd_data;
  530         u_int32_t       fd_branch;
  531         u_int16_t       fd_status;
  532         u_int16_t       fd_rescount;
  533 };
  534 #endif
  535 #if BYTE_ORDER == LITTLE_ENDIAN
  536 struct fwohci_desc {
  537         u_int16_t       fd_reqcount;
  538         u_int16_t       fd_flags;
  539         u_int32_t       fd_data;
  540         u_int32_t       fd_branch;
  541         u_int16_t       fd_rescount;
  542         u_int16_t       fd_status;
  543 };
  544 #endif
  545 #define fd_timestamp    fd_rescount
  546 
  547 #define OHCI_DESC_STORE_VALUE   0x8600
  548 #define OHCI_DESC_INPUT         0x2000
  549 #define OHCI_DESC_OUTPUT        0x0000 /* for the symmetory */
  550 #define OHCI_DESC_LAST          0x1000
  551 #define OHCI_DESC_STATUS        0x0800
  552 #define OHCI_DESC_IMMED         0x0200
  553 #define OHCI_DESC_PING          0x0080
  554 #define OHCI_DESC_INTR_ALWAYS   0x0030
  555 #define OHCI_DESC_INTR_ERR      0x0010
  556 #define OHCI_DESC_BRANCH        0x000c
  557 #define OHCI_DESC_WAIT          0x0003
  558 
  559 #define OHCI_DESC_MAX           8
  560 
  561 /* Some constants for passing ACK values around with from status reg's */
  562 
  563 #define OHCI_DESC_STATUS_ACK_MASK 0x1f
  564 
  565 #endif  /* _DEV_IEEE1394_FWOHCIREG_ */

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